VHDL Syntax Reference

From The System Designers Guide to VHDL

by Peter. J Ashenden, Gregory D. Peterson
and Darrell A. Teegarden
Morgan Kaufmann Publishers

In this reference we present the full set of syntax rules for VHDL-AMS using the EBNF
notation introduced in Chapter 1. The form of EBNF used here differs from that of
the VHDL-AMS standard in order to make the syntax rules more intelligible to the
VHDL user. The standard includes a separate syntax rule for each minor syntactic cat-
egory. In this reference, we condense the grammar into a smaller number of rules,
each of which defines a larger part of the grammar. We introduce the EBNF symbols
(, ) and as part of this simplification. Our aim is to avoid the large amount of
searching required when using the standard rules to resolve a question of grammar.

Index to Syntax Rules

access_type_definition 7 block_statement 8
across_aspect 6 break_element 12
actual_part 13 break_statement 12
aggregate 14 case_statement 12
alias_declaration 6 character_literal 14
architecture_body 3 choices 14
array_nature_definition 8 component_declaration 6
array_type_definition 7 component_instantiation_statement 10
assertion_statement 12 component_specification 6
association_list 13 concurrent_assertion_statement 9
attribute_declaration 6 concurrent_break_statement 10
attribute_name 14 concurrent_procedure_call_statement 9
attribute_specification 6 concurrent_signal_assignment_statement 10
based_integer 14 concurrent_statement 8
based_literal 14 conditional_signal_assignment 10
binding_indication 6 configuration_declaration 4
bit_string_literal 14 configuration_specification 6
block_configuration 4 constant_declaration 5
block_declarative_item 9

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2 VHDL-AMS Syntax Reference
decimal_literal 14
delay_mechanism 12
design_file 3
design_unit 3
disconnection_specification 7
discrete_range 8
entity_class 6
entity_declaration 3
entity_declarative_item 3
entity_name_list 6
enumeration_type_definition
exit_statement 12
expression 13
factor 14
file_declaration 6
file_type_definition 7
floating_type_definition 7 signal_declaration 5
formal_part 13
function_call 14
generate_statement 10
group_declaration 7
group_template_declaration
identifier 15
if_statement 12
integer 14
integer_type_definition 7 source_aspect 6
interface_list 13
label 15
library_clause 3
library_unit 3
literal 14
loop_statement 12
mode 13
name 14
nature_declaration 5
nature_definition 5
nature_mark 8
next_statement 12
null_statement 12
operator_symbol 14
package_body 4
package_body_declarative_item 4
package_declaration 4
package_declarative_item 4
physical_literal 14
physical_type_definition 7
primary 14
procedural_declarative_item 11
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procedure_call_statement 12
process_declarative_item 9
process_statement 9
qualified_expression 14
quantity_declaration 6
record_nature_definition 8
record_type_definition 7
relation 13
report_statement 12
return_statement 12
7
scalar_nature_definition 8
selected_name 14
selected_signal_assignment 10
sequential_statement 11
shift_expression 13
signal_assignment_statement 12
signature 14
simple_expression 13
simple_simultaneous_statement 10
simultaneous_case_statement 11
7 simultaneous_if_statement 10
simultaneous_null_statement 11
simultaneous_procedural_statement 11
simultaneous_statement 10
step_limit_specification 7
string_literal 14
subnature_declaration 8
subnature_indication 8
subprogram_body 5
subprogram_declaration 5
subprogram_declarative_item 5
subprogram_specification 5
subtype_declaration 8
subtype_indication 8
term 13
terminal_aspect 6
terminal_declaration 5
through_aspect 6
type_declaration 5
type_definition 5
type_mark 8
use_clause 7
variable_assignment_statement 12
variable_declaration 5
wait_statement 11
waveform 12
 VHDL-AMS Syntax Reference 3

Design File

design_file design_unit { }
design_unit
{ library_clause I use_clause }
library_unit
library_unit
entity_declaration I architecture_body
I package_declaration I package_body
I configuration_declaration
library_clause library identifier { , } ;

Library Unit Declarations

entity_declaration
entity identifier is
[ generic ( generic_interface_list ) ; ]
[ port ( port_interface_list ) ; ]
{ entity_declarative_item }
[ begin
{ concurrent_assertion_statement
I passive_concurrent_procedure_call_statement
I passive_process_statement } ]
end [ entity ] [ identifier ] ;
entity_declarative_item
subprogram_declaration I subprogram_body
I type_declaration I subtype_declaration
I constant_declaration I signal_declaration
I shared_variable_declaration I file_declaration
I alias_declaration
I attribute_declaration I attribute_specification
I disconnection_specification I use_clause
I group_template_declaration I group_declaration
I step_limit_specification
I nature_declaration I subnature_declaration
I quantity_declaration I terminal_declaration
architecture_body
architecture identifier of entity_name is
{ block_declarative_item }
begin
{ concurrent_statement I simultaneous_statement }
end [ architecture ] [ identifier ] ;

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configuration_declaration
configuration identifier of entity_name is
{ use_clause I attribute_specification I group_declaration }
block_configuration
end [ configuration ] [ identifier ] ;
block_configuration
for ( architecture_name
I block_statement_label
I generate_statement_label [ ( ( discrete_range I static_expression ) ) ] )
{ use_clause }
{ block_configuration
I for component_specification
[ binding_indication ; ]
[ block_configuration ]
end for ; }
end for ;
package_declaration
package identifier is
{ package_declarative_item }
end [ package ] [ identifier ] ;
package_declarative_item
subprogram_declaration
I type_declaration I subtype_declaration
I constant_declaration I signal_declaration
I shared_variable_declaration I file_declaration
I alias_declaration I component_declaration
I attribute_declaration I attribute_specification
I disconnection_specification I use_clause
I group_template_declaration I group_declaration
I nature_declaration I subnature_declaration
I terminal_declaration
package_body
package body identifier is
{ package_body_declarative_item }
end [ package body ] [ identifier ] ;
package_body_declarative_item
subprogram_declaration I subprogram_body
I type_declaration I subtype_declaration
I constant_declaration I shared_variable_declaration
I file_declaration I alias_declaration
I use_clause
I group_template_declaration I group_declaration

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Declarations and Specifications

subprogram_specification
procedure ( identifier I operator_symbol ) [ ( parameter_interface_list ) ]
I [ pure I impure ]
function ( identifier I operator_symbol )
[ ( parameter_interface_list ) ] return type_mark
subprogram_declaration subprogram_specification ;
subprogram_body
subprogram_specification is
{ subprogram_declarative_item }
begin
{ sequential_statement }
end [ procedure I function ] [ identifier I operator_symbol ] ;
subprogram_declarative_item
subprogram_declaration I subprogram_body
I type_declaration I subtype_declaration
I constant_declaration I variable_declaration
I file_declaration I alias_declaration
I attribute_declaration I attribute_specification
I use_clause
I group_template_declaration I group_declaration
type_declaration
type identifier is type_definition ;
I type identifier ;
type_definition
enumeration_type_definition I integer_type_definition
I floating_type_definition I physical_type_definition
I array_type_definition I record_type_definition
I access_type_definition I file_type_definitionI
protected_type_declarationI protected_type_body
nature_declaration
nature identifier is nature_definition ;
nature_definition
scalar_nature_definition I array_nature_definition I record_nature_definition
constant_declaration
constant identifier { , } : subtype_indication [ := expression ] ;
signal_declaration
signal identifier { , } : subtype_indication [ register I bus ] [ := expression ] ;
variable_declaration
[ shared ] variable identifier { , } : subtype_indication [ := expression ] ;
terminal_declaration
terminal identifier { , } : subnature_indication ;

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quantity_declaration
quantity identifier { , } : subtype_indication [ := expression ] ;
I quantity [ across_aspect ] [ through_aspect ] terminal_aspect ;
I quantity identifier { , } : subtype_indication source_aspect ;
across_aspect
identifier { , } [ tolerance string_expression ] [ := expression ] across
through_aspect
identifier { , } [ tolerance string_expression ] [ := expression ] through
terminal_aspect
plus_terminal_name [ to minus_terminal_name ]
source_aspect
spectrum magnitude_simple_expression , phase_simple_expression
I noise power_simple_expression
file_declaration
file identifier { , } : subtype_indication
[ [ open file_open_kind_expression ] is string_expression ] ;
alias_declaration
alias ( identifier I character_literal I operator_symbol )
[ : ( subtype_indication I subnature_indication ) ] is name [ signature ] ;
component_declaration
component identifier [ is ]
[ generic ( generic_interface_list ) ; ]
[ port ( port_interface_list ) ; ]
end component [ identifier ] ;
attribute_declaration attribute identifier : type_mark ;
attribute_specification
attribute identifier of entity_name_list : entity_class is expression ;
entity_name_list
( ( identifier I character_literal I operator_symbol ) [ signature ] ) { , }
I others
I all
entity_class
entity I architecture I configuration I package
I procedure I function I type I subtype
I constant I signal I variable I file
I component I label I literal I units I group
I nature I subnature I quantity I terminal
configuration_specification
for component_specification binding_indication ;
component_specification
( instantiation_label { , } I others I all ) : component_name

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 VHDL-AMS Syntax Reference 7

binding_indication
[ use ( entity entity_name [ ( architecture_identifier ) ]
I configuration configuration_name
I open ) ]
[ generic map ( generic_association_list ) ]
[ port map ( port_association_list ) ]
disconnection_specification
disconnect ( signal_name { , } I others I all ) : type_mark
after time_expression ;
step_limit_specification
limit ( quantity_name { , } I others I all ) : type_mark with real_expression ;
group_template_declaration
group identifier is ( ( entity_class [ <> ] ) { , } ) ;
group_declaration
group identifier : group_template_name ( ( name I character_literal ) { , } ) ;
use_clause use selected_name { , } ;

Type Definitions

enumeration_type_definition ( ( identifier I character_literal ) { , } )

integer_type_definition
range ( range_attribute_name
I simple_expression ( to I downto ) simple_expression )
floating_type_definition
range ( range_attribute_name
I simple_expression ( to I downto ) simple_expression )
physical_type_definition
range ( range_attribute_name
I simple_expression ( to I downto ) simple_expression )
units
identifier ;
{ identifier = physical_literal ; }
end units [ identifier ]
array_type_definition
array ( ( type_mark range <> ) { , } ) of element_subtype_indication
I array ( discrete_range { , } ) of element_subtype_indication
record_type_definition
record
( identifier { , } : subtype_indication ; )
{}
end record [ identifier ]
access_type_definition access subtype_indication
file_type_definition file of type_mark
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scalar_nature_definition
type_mark across type_mark through identifier reference
array_nature_definition
array ( ( type_mark range <> ) { , } ) of subnature_indication
I array ( discrete_range { , } ) of subnature_indication
record_nature_definition
record
( identifier { , } : subnature_indication ; )
{}
end record [ identifier ]
subtype_declaration subtype identifier is subtype_indication ;
subtype_indication
[ resolution_function_name ]
type_mark [ range ( range_attribute_name
I simple_expression ( to I downto ) simple_expression )
I ( discrete_range { , } ) ]
[ tolerance string_expression ]
discrete_range
discrete_subtype_indication
I range_attribute_name
I simple_expression ( to I downto ) simple_expression
type_mark type_name I subtype_name
subnature_declaration subnature identifier is subnature_indication ;
subnature_indication
nature_mark
[ ( discrete_range { , } ) ]
[ tolerance string_expression across string_expression through ]
nature_mark nature_name I subnature_name

Concurrent Statements

concurrent_statement
block_statement
I process_statement
I concurrent_procedure_call_statement
I concurrent_assertion_statement
I concurrent_signal_assignment_statement
I component_instantiation_statement
I generate_statement
I concurrent_break_statement

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 VHDL-AMS Syntax Reference 9

block_statement
block_label :
block [ ( guard_expression ) ] [ is ]
[ generic ( generic_interface_list ) ;
[ generic map ( generic_association_list ) ; ] ]
[ port ( port_interface_list ) ;
[ port map ( port_association_list ) ; ] ]
{ block_declarative_item }
begin
{ concurrent_statement I simultaneous_statement }
end block [ block_label ] ;
block_declarative_item
subprogram_declaration I subprogram_body
I type_declaration I subtype_declaration
I constant_declaration I signal_declaration
I shared_variable_declaration I file_declaration
I alias_declaration I component_declaration
I attribute_declaration I attribute_specification
I configuration_specification I disconnection_specification
I use_clause
I group_template_declaration I group_declaration
I step_limit_specification
I nature_declaration I subnature_declaration
I quantity_declaration I terminal_declaration
process_statement
[ process_label : ]
[ postponed ] process [ ( signal_name { , } ) ] [ is ]
{ process_declarative_item }
begin
{ sequential_statement }
end [ postponed ] process [ process_label ] ;
process_declarative_item
subprogram_declaration I subprogram_body
I type_declaration I subtype_declaration
I constant_declaration I variable_declaration
I file_declaration I alias_declaration
I attribute_declaration I attribute_specification
I use_clause
I group_template_declaration I group_declaration
concurrent_procedure_call_statement
[ label : ]
[ postponed ] procedure_name [ ( parameter_association_list ) ] ;
concurrent_assertion_statement
[ label : ]
[ postponed ] assert boolean_expression
[ report expression ] [ severity expression ] ;
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concurrent_signal_assignment_statement
[ label : ] [ postponed ] conditional_signal_assignment
I [ label : ] [ postponed ] selected_signal_assignment
conditional_signal_assignment
( name I aggregate ) <= [ guarded ] [ delay_mechanism ]
{ waveform when boolean_expression else }
waveform [ when boolean_expression ] ;
selected_signal_assignment
with expression select
( name I aggregate ) <= [ guarded ] [ delay_mechanism ]
{ waveform when choices , }
waveform when choices ;
component_instantiation_statement
instantiation_label :
( [ component ] component_name
I entity entity_name [ ( architecture_identifier ) ]
I configuration configuration_name )
[ generic map ( generic_association_list ) ]
[ port map ( port_association_list ) ] ;
generate_statement
generate_label :
( for identifier in discrete_range I if boolean_expression ) generate
[ { block_declarative_item }
begin ]
{ concurrent_statement I simultaneous_statement }
end generate [ generate_label ] ;
concurrent_break_statement
[ label : ]
break [ break_element { , } ]
[ on signal_name { , } ]
[ when boolean_expression ] ;

Simultaneous Statements

simultaneous_statement
simple_simultaneous_statement
I simultaneous_if_statement I simultaneous_case_statement
I simultaneous_procedural_statement I simultaneous_null_statement
simple_simultaneous_statement
[ label : ]
simple_expression == simple_expression [ tolerance string_expression ] ;

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simultaneous_if_statement
[ if_label : ]
if boolean_expression use
{ simultaneous_statement }
{ elsif boolean_expression use
{ simultaneous_statement } }
[ else
{ simultaneous_statement } ]
end use [ if_label ] ;
simultaneous_case_statement
[ case_label : ]
case expression use
( when choices => { simultaneous_statement } )
{}
end case [ case_label ] ;
simultaneous_procedural_statement
[ procedural_label : ]
procedural [ is ]
{ procedural_declarative_item }
begin
{ sequential_statement }
end procedural [ procedural_label ] ;
procedural_declarative_item
subprogram_declaration I subprogram_body
I type_declaration I subtype_declaration
I constant_declaration I variable_declaration
I alias_declaration I attribute_declaration
I attribute_specification I use_clause
I group_template_declaration I group_declaration
simultaneous_null_statement [ label : ] null ;

Sequential Statements

sequential_statement
wait_statement I assertion_statement
I report_statement I signal_assignment_statement
I variable_assignment_statement I procedure_call_statement
I if_statement I case_statement
I loop_statement I next_statement
I exit_statement I return_statement
I null_statement I break_statement
wait_statement
[ label : ] wait [ on signal_name { , } ]
[ until boolean_expression ]
[ for time_expression ] ;
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assertion_statement
[ label : ] assert boolean_expression
[ report expression ] [ severity expression ] ;
report_statement [ label : ] report expression [ severity expression ] ;
signal_assignment_statement
[ label : ] ( name I aggregate ) <= [ delay_mechanism ] waveform ;
delay_mechanism transport I [ reject time_expression ] inertial
waveform
( value_expression [ after time_expression ]
I null [ after time_expression ] ) { , }
I unaffected
variable_assignment_statement
[ label : ] ( name I aggregate ) := expression ;
procedure_call_statement
[ label : ] procedure_name [ ( parameter_association_list ) ] ;
if_statement
[ if_label : ]
if boolean_expression then
{ sequential_statement }
{ elsif boolean_expression then
{ sequential_statement } }
[ else
{ sequential_statement } ]
end if [ if_label : ] ;
case_statement
[ case_label : ]
case expression is
( when choices => { sequential_statement } )
{}
end case [ case_label : ] ;
loop_statement
[ loop_label ]
[ while boolean_expression I for identifier in discrete_range ] loop
{ sequential_statement }
end loop [ loop_label ] ;
next_statement [ label : ] next [ loop_label ] [ when boolean_expression ] ;
exit_statement [ label : ] exit [ loop_label ] [ when boolean_expression ] ;
return_statement [ label : ] return [ expression ] ;
null_statement [ label : ] null ;
break_statement
[ label : ] break [ break_element { , } ] [ when boolean_expression ] ;
break_element [ for quantity_name use ] quantity_name => expression

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Interfaces and Associations

interface_list
( [ constant ] identifier { , } : [ in ] subtype_indication
[ := static_expression ]
I [ signal ] identifier { , } : [ mode ] subtype_indication [ bus ]
[ := static_expression ]
I [ variable ] identifier { , } : [ mode ] subtype_indication
[ := static_expression ]
I file identifier { , } : subtype_indication
I terminal identifier { , } : subnature_indication
I quantity identifier { , } : [ in I out ] subtype_indication
[ := static_expression ]
){;}
mode in I out I inout I buffer I linkage
association_list ( [ formal_part => ] actual_part ) { , }
formal_part
generic_name
I port_name
I parameter_name
I function_name ( ( generic_name I port_name I parameter_name ) )
I type_mark ( ( generic_name I port_name I parameter_name ) )
actual_part
expression
I signal_name
I variable_name
I terminal_name
I quantity_name
I open
I function_name ( ( signal_name I variable_name I quantity_name ) )
I type_mark ( ( signal_name I variable_name I quantity_name ) )

Expressions

expression
relation { and relation } I relation [ nand relation ]
I relation { or relation } I relation [ nor relation ]
I relation { xor relation } I relation { xnor relation }
relation shift_expression [ ( = I /= I < I <= I > I >= ) shift_expression ]
shift_expression
simple_expression [ ( sll I srl I sla I sra I rol I ror ) simple_expression ]
simple_expression [ + I ] term { ( + I I & ) term }
term factor { ( * I / I mod I rem ) factor }

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factor primary [ ** primary ] I abs primary I not primary

primary
name I literal
I aggregate I function_call
I qualified_expression I type_mark ( expression )
I new subtype_indication I new qualified_expression
I ( expression )
function_call function_name [ ( parameter_association_list ) ]
qualified_expression type_mark ' ( expression ) I type_mark ' aggregate
name
identifier
I operator_symbol
I selected_name
I ( name I function_call ) ( expression { , } )
I ( name I function_call ) ( discrete_range )
I attribute_name
selected_name
( name I function_call ) . ( identifier I character_literal I operator_symbol I all )
operator_symbol " { graphic_character } "
attribute_name
( name I function_call ) [ signature ] ' identifier [ ( expression { , } ) ]
signature [ [ type_mark { , } ] [ return type_mark ] ]
literal
decimal_literal I based_literal
I physical_literal I identifier
I character_literal I string_literal
I bit_string_literal I null
physical_literal [ decimal_literal I based_literal ] unit_name
decimal_literal integer [ . integer ] [ E [ + ] integer I E integer ]
based_literal
integer # based_integer [ . based_integer ] # [ E [ + ] integer I E integer ]
integer digit { [ _ ] }
based_integer ( digit I letter ) { [ _ ] }
character_literal ' graphic_character '
string_literal " { graphic_character } "
bit_string_literal ( B I O I X ) " [ ( digit I letter ) { [ _ ] } ] "
aggregate ( ( [ choices => ] expression ) { , } )
choices ( simple_expression I discrete_range I identifier I others ) { | }
label identifier
identifier letter { [ _ ] ( letter I digit ) } I \ graphic_character { } \

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