K.S.

SOMESH 16BIS0091

ECE2026
DIGITAL ASSIGNMENT 2

QUESTION :

Design a counterlike circuit controlled by the input w. If w = 1, then counter adds 2 to its
contents, wrapping around if the count reaches 8. Thus if the present state is 8 then the next state
becomes 0. If w = 0, then the counter subtracts 1 from its contents, acting as a normal down
counter. Use D flip flop in your circuit. Write a verilog code for the design

Verilog Code :
module d_ff(clk,q,d);
input clk,d;
output q;
reg q;
always @(posedge clk)
begin
q=d;
end
endmodule

module da2(y0,y1,y2,c,w,z0,z1,z2);
input y0,y1,y2,w,c;
output z0,z1,z2;

wire Y0,Y1,Y2;
assign Y0=(~y0&~w)|(y0&w);
assign Y1=(w&~y1)|(~y1&~y0)|(~w&y1&y0);
assign
Y2=(w&~y2&y1)|(~w&y2&y1)|(w&y2&~y1)|(~w&y1&y0)|(w&~y0&~y1&~y2)|(~w&~y0&~y1&~y
2);
d_ff d1(c,z0,Y0);
d_ff d2(c,z1,Y1);
d_ff d3(c,z2,Y2);
endmodule
K.S.SOMESH 16BIS0091

Simulation :