Mechatronics 12 (2002) 11851199

The HARPSS process for fabrication of precision

MEMS inertial sensors
Farrokh Ayazi *

School of Electrical and Computer Engineering, Georgia Institute of Technology,

Atlanta, GA 30332-0250, USA

Abstract
The high aspect-ratio combined poly- and single-crystal silicon micromachining technology
(HARPSS) and its application to fabrication of precision MEMS inertial sensors are pre-
sented. HARPSS is a single wafer, all silicon, front-side release process which is capable of
producing 10100s of microns thick, electrically isolated, 3-D poly- and single-crystalline
silicon microstructures with various size air-gaps ranging from sub-micron to tens of microns.
High aspect-ratio (>50:1) polysilicon structures are created by relling 100s of microns deep
trenches with polysilicon deposited over a sacricial oxide layer. This technology provides
features required for precision micromachined inertial sensors. The all-silicon feature of this
technology improves long term stability and temperature sensitivity while fabrication of large
area, vertical electrodes with sub-micron gap spacing will increase the sensitivity by orders of
magnitude.
2002 Published by Elsevier Science Ltd.

Keywords: Silicon micromachining; MEMS; Polysilicon micromachining; Deep reactive ion etching;
Inertial sensors; Gyroscope

1. Introduction

Next generation high performance MEMS inertial sensors, consisting of micro-

accelerometers and microgyroscopes [1], will require fabrication technologies that can
combine high aspect-ratio deep dry etching of silicon with polysilicon surface mi-
cromachining to realize all-silicon, 100s of microns thick microstructures which are
electrically isolated from one another and separated by small capacitive gaps. The all-
silicon feature of such a technology improves long-term stability and temperature

*
Tel.: +1-404-894-9496; fax: +1-404-894-4700.
E-mail address: ayazi@ece.gatech.edu (F. Ayazi).

0957-4158/02/$ - see front matter 2002 Published by Elsevier Science Ltd.

PII: S 0 9 5 7 - 4 1 5 8 ( 0 2 ) 0 0 0 2 3 - 5
1186 F. Ayazi / Mechatronics 12 (2002) 11851199

sensitivity. Hundreds of microns thick silicon structures have large mass (up to a few
milligrams) with reduced Brownian displacement noise which make them suitable for
inertial-grade devices. Fabrication of large area, vertical capacitors with sub-micron
gap spacing will increase the sense capacitance and hence the sensitivity of MEMS
devices by orders of magnitude. By shrinking the capacitive gaps to sub-micron levels,
bias, actuation and control voltages will also shift down to CMOS acceptable levels
(<5 V). However, dierent size capacitive air-gaps are needed in high-performance
devices. For example, vibratory gyroscopes that are based on transfer of energy be-
tween two vibration modes of a mechanical structure often need relatively large
amplitude of vibrations ( P 1 lm) to increase the mechanical sensitivity of the sensor
and reduce its noise oor. In parallel-plate electrostatic actuators, the amplitude of
vibration should be kept less than tenth of the capacitive air-gap for linear operation,
demanding for wide air-gaps in the range of 1020 lm. In the case of capacitive ac-
celerometers, the squeeze lm damping between the proof mass and the sense elec-
trodes can be reduced by making the air-gaps larger in selected areas to provide low
damping path for the air molecules. This will further reduce the Brownian noise oor
of microaccelerometers.
This paper presents the all silicon high aspect-ratio poly- and single-crystal silicon
micromachining technology, known as the HARPSS process [2,3], and its applica-
tion to precision inertial sensors. HARPSS is a single wafer mixed-mode micro-
fabrication technology that combines the best features of bulk micromachining with
surface micromachining and is capable of producing 10100s of microns thick,
electrically-isolated poly- and single-crystal silicon structures. It utilizes one layer of
low pressure chemical vapor deposited (LPCVD) silicon nitride (Si3 N4 ), one layer of
LPCVD silicon dioxide (SiO2 ) and one layer of LPCVD polysilicon. Various size
capacitive air-gaps ranging from sub-micron to tens of micron can be realized in this
technology. Sub-micron air-gaps (ranging from 100s of Angstroms to 2 lm) are
dened by the thickness of the sacricial oxide layer and are formed in between
polysilicon and single-crystal-silicon electrode plates. Thick single-crystal silicon
structures (or electrodes) are protected on the sides by deep relled trenches and are
released from the substrate by means of an SF6 dry release that is carried out entirely
in a silicon deep reactive ion etching (DRIE) system. Electrode plates associated with
wider air-gaps are both created out of polysilicon. This technology is also capable
of simultaneously producing electrically isolated 2-D (planar) and 3-D (vertical)
polysilicon structures on the same silicon substrate. It can be integrated with CMOS
integrated circuits to realize high-performance integrated MEMS with reduced
parasitic.

2. Fabrication process

Fig. 1 shows the fabrication process ow for the six-mask HARPSS technology.
First, a thin layer of LPCVD silicon nitride (2500 A ) is deposited and patterned to
serve as an isolation dielectric layer underneath the electrode bonding pads. Fifty to
100s of lm deep trenches with straight sidewalls 90  1 are then dry etched into
 F. Ayazi / Mechatronics 12 (2002) 11851199 1187

Fig. 1. Fabrication process ow for the six-mask HARPSS MEMS technology.

a low-resistivity silicon substrate using the Bosch process [4] in a silicon DRIE
system. The height of these trenches will determine the height of silicon micro-
structure(s). Trenches with smooth and straight sidewalls are needed to eliminate
void formation in the polysilicon beams which will be formed by back-lling these
trenches. Fig. 2 shows the scanning electron microscope (SEM) view of these tren-
ches etched in a STS DRIE machine [5]. Fig. 3 is a close-up of the top part of 5.6 lm
wide trenches showing the scalloping of the sidewall (<0.1 lm) and a mask undercut
of 0.3 lm per side. The scalloping at the top of the trench is formed due to the nature
of the Bosch process, which is based on sequential etching and polymer deposition.
Any sidewall scalloping or striation pattern will directly transfer to the polysilicon
beams upon backlling of these trenches. Table 1 summarizes the conditions used to
1188 F. Ayazi / Mechatronics 12 (2002) 11851199

Fig. 2. SEM view of 5 lm wide, 100 lm deep trenches with straight sidewalls etched in a STS DRIE
system using the ASE process. The etch parameters are given in Table 1; the etch time was 46 min.

Fig. 3. Close-up of the top of 5.6 lm wide, 100 lm deep trenches etched in a STS DRIE system using the
ASE process. Scalloping of the sidewall is less than 0.1 lm and mask undercut is 0.3 lm per side. Four
micrometre thick photoresist (AZ4400) was used as a mask.

Table 1
Conditions used in STS machine for etching 5 lm wide, 100 lm deep trenches shown in Fig. 2
Etch cycle Passivation cycle
Chemistry SF6 130 sccm, O2 13 sccm C4 F8 84 sccm
Cycle duration (s) 12 9
Pressure (mTorr) 22 10
Coil power (W) 800 600
Platen temperature 20 C. Etch rate 2 lm/min.

etch these trenches in a STS DRIE machine using the advance silicon etch (ASE)
process [6]. High aspect-ratio polysilicon mechanical structures are then created by
 F. Ayazi / Mechatronics 12 (2002) 11851199 1189

relling trenches with thin lms of polysilicon (24 lm thick) deposited over a
sacricial oxide layer. The maximum width of trenches is determined by the total
thickness of the sacricial oxide and polysilicon layer and is usually kept less than
7 lm. Trenches are completely relled after deposition of the polysilicon and hence
thicker deposition of poly can result in wider trenches and wider polysilicon beams.
Very high aspect-ratio polysilicon beams (>50:1) can be realized by reducing the
width of trenches to 34 lm.
LPCVD oxide lm is deposited at relatively high temperature (920 C) to obtain
conformal coating inside the trenches. Conformal LPCVD polysilicon layer is de-
posited at 588 C. After relling trenches, poly on the surface is etched back and the
underneath oxide is patterned to provide anchor points for the poly. From this step
on, since all the trenches are completely relled, lithographical steps (spin-casting)
can easily be performed using thick photoresist. After patterning the oxide, more
poly is deposited, doped and patterned. The structural polysilicon layer has to be
doped to lower its electrical resistance. Doping with boron is preferred over phos-
phorous due to the fact that the etch rate of boron-doped poly is much less than the
etch rate of phosphorous-doped poly in the HF:H2 O (1:1) solution, leaving the
poly beams intact after relatively long HF release step. After the doping process; Cr/
Au (200 A /3000 A ) is evaporated and patterned to form the electrode bonding
pads.
The next step in the process is the deep dry release step, which consists of a deep,
directional etch (depth of the trenches 1020 lm) followed by an isotropic SF6
silicon etch. Both of these steps are performed consecutively in a silicon DRIE
system. Thick photoresist (e.g. AZ4400) is used as a mask for this step. Areas of the
silicon substrate that need to be etched away are exposed to the plasma and are
bounded with deep trench-relled beams that have silicon dioxide on their side-
walls. Single-crystal silicon electrodes and microstructures are protected on the sides
from the silicon enchants by the outer oxide coating of trench-relled beams. After
the deep directional etch, the subsequent isotropic SF6 etch will isotropically etch the
silicon at the bottom of silicon electrodes (structures) to release them from the
substrate. After the deep release step, the photoresist mask is stripped o and sac-
ricial oxide layers are etched away in HF:H2 O (1:1) solution to create sub-micron
capacitive gaps between electrodes and the main body structure. Fig. 4 shows the
SEM view of a polysilicon ring microgyroscope fabricated through the HARPSS
process. This device is 2 mm in diameter and 80 lm thick; the width of the poly-
silicon beams is 4 lm and the support post is 400 lm in diameter. Fig. 5 shows the
close-up of a 60 lm thick single-crystal silicon electrode separated from the 80 lm
thick polysilicon ring resonator by 1.2 lm air-gap created through sacricial oxide
etching. The single-crystal silicon electrode is anchored on top to the supporting
polysilicon layer, which is in turn anchored through the isolating nitride layer to the
substrate. Vertical polysilicon stieners (trench-relled) are also incorporated in the
structure of the electrodes to ensure their rigidity.
Size of the air-gaps in this technology is not limited to sub-micron levels. Larger
air-gaps can be realized with polysilicon trench-relled electrodes. Larger air-gaps
are dened by the distance between two adjacent trenches which form parallel plates
1190 F. Ayazi / Mechatronics 12 (2002) 11851199

Fig. 4. SEM view of an 80 lm thick, 2 mm in diameter, four-ring gyroscope with meander-shaped springs
fabricated through the HARPSS process.

Fig. 5. Close-up of a 60 lm tall single crystal silicon sense electrode separated from the 80 lm thick
polysilicon ring resonator by a 1.2 lm air-gap.

of a capacitor. The silicon between these trenches is then directionally etched in the
STS machine during the deep release step. If the spacing is so small that deep release
etch openings cannot be placed directly between the adjacent trenches (<8 lm), then
the silicon between the two trenches is protected with resist on the top but undercut
at the bottom and the sides during the dry release step. This narrow piece of sili-
con which is held by the oxide on the sidewall of trenches will then fall into the
HF:H2 O solution during the sacricial oxide etch. Fig. 6 shows the SEM view
of wide capacitive gaps (10 to 20 lm) with polysilicon electrodes fabricated using this
technology.
It should be mentioned that a modied version of this process can extend the
multilayer polysilicon technology to the third dimension into the silicon substrate,
 F. Ayazi / Mechatronics 12 (2002) 11851199 1191

Fig. 6. Close-up of polysilicon electrodes separated from polysilicon ring resonator by large air-gaps
(1020 lm).

yielding multiple vertical polysilicon layers inside a trench with aspect-ratios in the
range of 100:1 and higher [7]. The polysilicon layers can be separated from each
other by sub-micron gap spacing, as shown in Fig. 7.

Fig. 7. Multiple polysilicon layers inside a 12 lm wide trench etched into the silicon substrate. Submicron
airgaps in between the poly beams are created by removal of sacricial oxide layers.
1192 F. Ayazi / Mechatronics 12 (2002) 11851199

3. Process characterization

Some design rules should be followed when using the HARPSS process. First, in
order to avoid the RIE lag eect, the width of all the trenches that dene the
polysilicon microstructures should be kept constant. Various width trenches can be
used if the dierence in the depth of the trenches due to RIE lag is not critical. The
maximum width of the trenches is determined by the total thickness of the deposited
sacricial oxide tox and the polysilicon layer tpoly and hence a thicker deposition of
poly can result in wider trenches and wider polysilicon beams. However, in order to
completely rell the trenches at their intersection
p points, the maximum width of the
trenches wmax should be kept less than 2tox tpoly (for perpendicular trenches).
Since LPCVD oxide and polysilicon are typically deposited with a thickness of less
than 3 lm, the maximum width of trenches is kept less than 7 lm. With 1.5 lm of
oxide and 3 lm of polysilicon deposition, 6 lm wide trenches used in this study were
completely relled at their intersections. As mentioned earlier, trenches with straight
sidewalls are required, as bowing of the prole will cause void formation in the
trench-relled polysilicon beams. A trench sidewall that is slightly slanted-inward
from top to the bottom will eliminate chances of void formation.
The other critical step in this process is the deep dry release step. Size of the etch
openings used in this step should preferably be equal in order to avoid RIE lag eect.
Electrodes and structures that need to be released from the substrate must be sur-
rounded by trench openings that provide the undercut. Typically, 810 lm wide
trenches are used in this step. Bigger size openings will result in faster release/
undercut of the single-crystal silicon structures.

3.1. Residual stress in polysilicon trench-relled beams

In order to investigate the amount of residual stress in 80 lm thick, trench-relled

polysilicon beams, a bent-beam strain gauge [8] was fabricated using this technology.
An SEM micrograph of a 500 lm long bent-beam strain sensor is shown in Fig. 8.
Small amount of lateral displacement can be measured by a vernier scale located at
the midpoint of the bent beams. The pitch of the tines is 0.2 lm, resulting in a
displacement resolution of 0.1 lm, and the angle between the bent-beam and the
long axis of the device is 0.1 radians.
Fig. 9 shows the close-up of the vernier attached to the 80 lm thick polysilicon
beams. The center tines are aligned to each other indicating that the displacement
and hence, the in-plane stress for thick polysilicon trench-relled beams are negli-
gible and cannot be measured using on-chip strain sensors.

3.2. Quality factor of microresonators and electronic tuning

Clampedclamped beam microresonators have been fabricated to investigate the

resonance behavior and quality factor of simple micromechanical structures in
this technology. These beams are electrostatically resonated in the plane of sub-
strate (lateral vibration mode) using tall electrodes located on their sides, as shown in
 F. Ayazi / Mechatronics 12 (2002) 11851199 1193

Fig. 8. SEM view of a 500 lm long, bent-beam strain gauge and a 300 lm long clampedclamped res-
onant beam fabricated using this technology.

Fig. 9. Close-up of the strain gauge vernier, showing virtually zero stress on 80 lm thick polysilicon
beams.

Fig. 10. Fabricated beams are 80 lm tall, 4 lm wide and have various lengths of 300
lm, 500 lm or 800 lm. The SEM micrograph of a 300 lm long clampedclamped
beam was shown in Fig. 8.
Table 2 shows the calculated and measured resonance frequencies of the fabri-
cated beams, assuming a Youngs modulus of E 150 GPa and a density of q
2:328 g/cm3 for 4 lm wide, 80 lm thick trench-relled polysilicon beams. Mea-
surements are in very good agreement with calculated values. Fig. 11 shows the
resonance peaks for 300 lm long clampedclamped beam, showing a quality factor of
85,000 measured in 1 mTorr vacuum.
1194 F. Ayazi / Mechatronics 12 (2002) 11851199

Fig. 10. Micromechanical clampedclamped beam resonator with electrostatic actuation and capacitive
detection.

Table 2
Measurement results on resonance frequency and quality factor of the various clampedclamped beam
micromechanical resonators fabricated through the HARPSS technology
Length (lm) Calculated res. freq. (kHz) Measured res. freq. (kHz) Measured Q
300 367 388 85,000
500 132 132 30,000
800 51.6 51 10,000

Fig. 11. Frequency response of an 80 lm thick, 300 lm long polysilicon beam showing a Q of 85,000
under 1 mTorr vacuum.
 F. Ayazi / Mechatronics 12 (2002) 11851199 1195

Fig. 12. Change in the resonance frequency versus DC polarization voltage for an 80 lm thick, 4 lm wide
polysilicon beam.

Fig. 12 shows the change in the resonance frequency of a 500 lm long, 80 lm tall
clampedclamped beam resonator with DC polarization voltage. The resonance
frequency can be changed from 147.5 to 144.5 kHz (2%) with only 7 V increase in
polarization voltage (8 to 15 V). This high tuning capability is a result of small ca-
pacitive gaps (1.2 lm) made by sacricial oxide layer.

4. Application to inertial sensors

The HARPSS process provides several important features that are required for
high-performance MEMS microgyroscopes and microaccelerometers. First, it allows
fabrication of 100s of microns thick electrically isolated silicon structures, which in
turn will result in larger mass and larger capacitive area. Second, since the gap
spacing is dened by the thickness of the sacricial oxide layer, it can be reduced to
sub-micron level; these two factors together will signicantly increase the sense ca-
pacitance and hence the device sensitivity. Third, a wide range of gap spacing (from
100s of Angstroms to 10s of microns) can be realized simultaneously in this tech-
nology. Fourth, the structural material is silicon which has a high mechanical quality
factor (Q) suitable for vibratory gyroscopes. Fifth, the all-silicon feature of this
technology improves long-term stability and temperature sensitivity. These features
play an instrumental role in allowing the performance of MEMS capacitive inertial
sensors to be improved by orders of magnitude.

4.1. Precision silicon microgyroscopes

Fig. 13 shows the SEM view of an 80 lm thick, polysilicon ring gyroscope (PRG)
[9] fabricated through the HARPSS process. The ring is 1.1 mm in diameter and the
diameter of the support post is 120 lm. The width of the ring and support springs is
4 lm. Sixteen electrodes are evenly located around the structure; they are approxi-
mately 60 lm tall and 150 lm long and are separated from the ring by a 1.2 lm
capacitive air-gap. The ring is electrostatically vibrated into its primary exural
1196 F. Ayazi / Mechatronics 12 (2002) 11851199

Fig. 13. SEM view of a prototype 1.7 mm  1:7 mm PRG fabricated through the HARPSS technology.
The ring is 1.1 mm in diameter and 80 lm thick.

mode with a xed amplitude. When device is subjected to rotation around its normal
axis, Coriolis force causes energy to be transferred from the primary mode to the
secondary exural mode, which is located 45 apart from the primary mode, causing
amplitude to build up proportionally in the latter mode; this build-up is capacitively
monitored [9].
Fig. 14 is the response of a prototype HARPSS polysilicon ring gyroscope to
input rotation rates in 5 Hz bandwidth. An open-loop sensitivity of 200 lV/deg/s in a
dynamic range of 250 deg/s was measured under low vacuum level for this device
tested in hybrid format, as shown in Fig. 15. The resolution under low vacuum
condition with a quality factor of 1200, drive amplitude of 0.15 lm, and sense node
parasitic capacitances of 2 pF was measured to be better than 1 deg/s [9]. This res-
olution for a Q of 1200 and parasitic capacitances of 2 pF is in agreement with
theory. The resolution of the sensor was limited by the noise from the circuitry.
Elimination of the parasitic capacitances and improvement in the quality factor of
the ring structure will improve the resolution to 0.01 deg/s in 1 Hz bandwidth. By

Fig. 14. Measured rate results obtained from a prototype PRG in 5 Hz BW.
 F. Ayazi / Mechatronics 12 (2002) 11851199 1197

Fig. 15. Hybrid attachment of the ring gyroscope to the interface IC chip in a 24-pin ceramic DIP
package.

increasing the drive amplitude to 1 lm, the resolution can be further improved to
5  103 deg/s (18 deg/h) in a 10 Hz bandwidth [10], yielding a tactical grade mi-
crogyroscope [1].

4.2. Precision silicon microaccelerometers

The HARPSS process can also be employed to realize inertial grade capacitive
microaccelerometers with sub-micro-g resolution (g 9:8 m/s2 ). Fig. 16 shows the

Fig. 16. Structure of a HARPSS precision lateral microaccelerometer.

1198 F. Ayazi / Mechatronics 12 (2002) 11851199

structure of a 200 lm thick lateral HARPSS capacitive accelerometer with lg ac-

celeration sensitivity. The combination of large proof mass and corrugated
p sense
nger design reduces the Brownian noise oor of this device to 0.1 lg/ Hz. The
projected sensitivity of this HARPSS microaccelerometer is 15 pF/g with a shock
resistance of 1000 g.

5. Conclusions

The HARPSS MEMS technology is an all silicon single wafer process capable of
producing 10100s of microns thick, electrically isolated poly- and single-crystal
silicon structures. Various size capacitive air-gaps ranging from sub-micron to tens
of microns can be realized in this technology. High aspect-ratio (>50:1) polysilicon
structures are created by relling 100s of microns deep trenches with polysilicon
deposited over a sacricial oxide layer. HARPSS process provides several important
features required for precision MEMS inertial sensors, consisting of microaccelero-
meters and microgyroscopes. The all-silicon feature of this technology improves long
term stability and temperature sensitivity while fabrication of large area, vertical
electrodes with sub-micron gap spacing will increase the sensitivity by orders of
magnitude.

Acknowledgements

This work was supported partially by the Defense Advanced Research Projects
Agency (DARPA) under contracts # DABT63-C-0111 and F30602-98-2-0231.

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 F. Ayazi / Mechatronics 12 (2002) 11851199 1199

Farrokh Ayazi was born in 1972. He received the B.S. degree in electrical engineering from the University
of Tehran in 1994, and the M.S. and Ph.D. degrees in electrical engineering from the University of
Michigan, Ann Arbor, in 1997 and 2000, respectively.

He joined the Faculty of Georgia Institute of Technology in 2000, where he currently is an Assistant
Professor in the School of Electrical and Computer Engineering. His research interests are in the areas of
MEMS, high aspect-ratio silicon micromachining technologies, analog integrated circuits, MEMS inertial
sensors, RF MEMS, and integrated microsystems. Dr. Ayazi is the Georgia Techs Packaging Research
Center thrust leader for Integral Passives and MEMS. He is a member of Sigma Xi and received a
Rackham Predoctoral Fellowship from the University of Michigan for 1998-99.