Electrical and Computer Engineering

Block RAM Exercise

By Prawat Nagvajara

Synopsis core registers in the Basic Options. The number

Use IP Catalog to create a custom IP RAM with of address bits is 10.
32-bit data and 10-bit address.

Deliverable
Test bench project which has the IP as its
peripheral and verify the correctness in SDK.

Comments

BRAM Design
IP Catalog Block Memory Generator
1. Create a new vivado vhdl project
2. Use Block Memory Generator from IP Catalog
to generate a single port native block RAM
having 32-bit data, 1024 addresses. Figure 1
shows the component parameters.
Fig.2 Core Summary
3. Block RAM Core Wrapper
Create a vhdl source, call it say,
BRAM_1032_wrapper (10-bit address 32-bit
data). Declare blk_mem_gen_0 as a component
and instantiate it using the instantiation
template file blk_mem_gen_0.vho found in the
IP Sources as shown in Fig. 3.

Fig. 3 Instantiation Template - .vho File

Fig. 1 Block RAM Parameters
Figure 2 shows the component blk_mem_gen_0
summary. The read latency is one clock cycle.
This results from not selecting primitive and
Below is the code in the .vho file use for the
component declaration and instantiation. Note
the comment at the end of the template code
on instructions regarding compiling a wrapper
file and reference library.
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT blk_mem_gen_0
PORT (
clka : IN STD_LOGIC; Fig. 4 Simulation Waves
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 5. Create and Package BRAM IP
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0); Note that the file
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0); bram_1032_ip_v1_0_S_AXI_ip.vhd in the test
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) bench is under
); ipshare/bram_1032_ip_v1_0/Xilinx.com/fe838d
END COMPONENT; b4/hdl
ATTRIBUTE SYN_BLACK_BOX : BOOLEAN;
ATTRIBUTE SYN_BLACK_BOX OF blk_mem_gen_0 : COMPONENT IS 6. Create BRAM embedded design test Bench
TRUE; and test application. Figure 5 shows example of
ATTRIBUTE BLACK_BOX_PAD_PIN : STRING; the terminal output.
ATTRIBUTE BLACK_BOX_PAD_PIN OF blk_mem_gen_0 : COMPONENT
IS "clka,ena,wea[0:0],addra[9:0],dina[31:0],douta[31:0]";
-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture

-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : blk_mem_gen_0
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------

-- You must compile the wrapper file blk_mem_gen_0.vhd when

simulating
-- the core, blk_mem_gen_0. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.

After editing BRAM_1032_wrapper.vhd the

design hierarchic has a component which binds
to blk_ram_gen_0.xci. Synthesize the design.

4. Simulation Fig. 5 Terminal Output Test Results

Launch simulation, in this case the modelsim
simulator.