Experiment: 7 VERILOG PROGRAMS FOR BASIC GATESDate: 07.10.

15

Aim:To write a Verilog program for basic gates using: i) Primitive Cells
ii) Continuous Assignment Statements

i)VERILOG Program for basic gates using Primitive Cells:

module basic gates(a,b,andout,orout,notout,norout,nandout,xorout,xnorout );
inputa,b;
output andout,orout,notout,norout,nandout,xorout,xnorout;
and andgate(andout,a,b);
or orgate(orout,a,b);
not notgate(notout,a,b);
nor norgate(norout,a,b);
nand nandgate(nandout,a,b);
xor xorgate(xorout,a,b);
xnor xnorgate(xnorout,a,b);
end module

Output of basic gates using Primitive Cells:

i)VERILOG Program for basic gates using Continuous Assignment Statements:

module basicgates(a,b,andout,orout,notout,norout,nandout,xorout,xnorout );
input a, b;
output andout,orout,notout,norout,nandout,xorout,xnorout;
and andgate(andout, a, b);
assign andout =(a & b)
assign orout =a |b
assign notout=a ~b
assign norout=~(a |b)
assign nandout=~(a &b)
assign xorout=a ^b
assign xnorout=~(a ^b)
end module
Output of basic gates using Continuous Assignment Statements:

Conclusion: The VERILOG program for basic gates using Primitive Cells and Continuous Assignment
Statements was studied and successfully implemented.