COMPUTER ORGANIZATION & ARCHITECTURE (EMT475/3)

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UNIVERSITI MALAYSIA PERLIS

COMPUTER ORGANIZATION & ARCHITECTURE
(EMT475/3)
Semester 1 Session Academic 2016/2017

LAB #1

Combinational Logic: Designing and Simulation of Arithmetic Logic Unit

ALU using VHDL

Student Name(s) Matrix No. Programme

1. Cheah Kuang Lee 141031713 RK-86
2. Chin Wei Seong 131030354 RK-86

Lecturer(s)
1. Dr. Shaiful Nizam Mohyar
2. Dr. Asral Bin Bahari Jambek

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Introduction:

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Objective(s):

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Methodology: (Coding & its explanation)

1. 4-bit ALU

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2. 8-bit ALU

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Result: (Waveform & discussion)

Waveform

1. 4-bit ALU Page | 5

2. 8-bit ALU

When opcode = 00

When opcode = 01

When opcode = 10

When opcode = 11

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RTL Viewer

1. 4-bit ALU

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tmp~3
in_A[3..0]
0
in_B[3..0]
1

tmp~5
Add0
1' h0 --
A[4..0] 0

1' h0 --
B[4..0]
+ 1

tmp~6
ADDER

0 out_Y[3..0]
tmp~2 1

tmp~7

tmp~1 0

tmp~8
tmp~0
0 0
carry
1

opcode tmp~4

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2. 8-bit ALU
tmp~[32..24]
tmp~8
in_A[7..0] SEL
0
in_B[7..0]
1

tmp~0 tmp~23
tmp~[41..33]

DATAA
0 SEL
Equal2 OUT0 DATAA
1 OUT0 carry
DATAB

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A[1..0]
opcode[1..0] tmp~18 out_Y[7..0]
2' h2 --
B[1..0]
= 1' h0 --
MUX21
EQUAL DATAB
tmp~9
0
1
MUX21
tmp~1 tmp~22

tmp~10
0

tmp~2 tmp~21

tmp~11
0
1

tmp~3 tmp~20

tmp~12
0
1

tmp~4 tmp~19

tmp~13

tmp~5

tmp~14
0
1

tmp~6 tmp~17

tmp~15
0
1

tmp~7 tmp~16

1' h0 --
Add1
A[9..0]
1' h1 --
1' h0 --
B[9..0]
+
ADDER
1' h1 --

Equal1
A[1..0]

2' h1 --
B[1..0]
=
EQUAL

Add0
1' h0 --
A[8..0]

1' h0 --
B[8..0]
+
ADDER

Equal0
A[1..0]

2' h0 --
B[1..0]
=
EQUAL

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Discussion
1. 4-bit ALU

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2. 8-bit ALU

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Conclusion:

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