TSB DFT 006 Appnote

TSB_DFT_006 Application Note
cad_dd_01017
Note Id: 3030
Issue 2.2 May 2016
TSB DFT 006 Application Note (PMC-2143953) (Note Id 3030) cad_dd_01017, Issue 2.2
PMC-Sierra, Inc. Proprietary and Confidential Page 1 of 45
Table of Contents
1 Introduction ............................................................................................................................................ 3
2 Context ................................................................................................................................................... 4
3 Reference ................................................................................................................................................ 5
4 TSB DFT Block Level View .................................................................................................................. 6
5 Differences From Previous Release........................................................................................................ 7
5.1 New Features are Supported in this Release ................................................................................... 7
5.2 Features Currently Not Supported in this Release .......................................................................... 8
6 Requirements for TSB DFT v006 Flow ................................................................................................. 9
7 TSB DFT Structure................................................................................................................................11
7.1 Scan Chain Construction ...............................................................................................................11
7.2 TSB Description (pmxxxx)............................................................................................................11
8 High-Level DFT Flow Description .......................................................................................................15
8.1 Stage 1: DFT Setup.......................................................................................................................15
8.2 Stage 2: Fill Out TSB Info File.....................................................................................................16
8.3 Stage 3: DFT Implementation ......................................................................................................16
8.4 Stage 4: Pre-DFT vs. Post-DFT LEC ...........................................................................................17
8.5 Stage 5: LL Verification ...............................................................................................................18
8.6 Stage 6: Run ET ATPG ................................................................................................................18
9 A Bit on TCL .........................................................................................................................................19
9.1 Back-slashes ..............................................................................................................................19
9.2 Comments ......................................................................................................................................19
9.3 Scalar Variable and Lists ...............................................................................................................19
9.4 Array ..............................................................................................................................................19
9.5 Nesting of Lists ..............................................................................................................................20
10 Detailed Flow Description .................................................................................................................21
10.1 Populate .........................................................................................................................................21
10.2 Setup DFT .....................................................................................................................................21
10.3 Fill Data File ..................................................................................................................................22
10.3.1 Design and DFT Set Up Section ............................................................................................22
10.3.2 IEEE 1500 Wrapper Cell Insertion Section ...........................................................................24
10.3.3 Compression Insertion and Scan-stitch Section .....................................................................25
10.3.4 Functional Lockup Latch Insertion Section ...........................................................................28
10.3.5 ATPG and LEC Script Generation Section ...........................................................................29
10.4 Run DFT Implementation ..............................................................................................................29
10.4.1 DFT Implementation .............................................................................................................29
10.4.2 Pre-DFT vs. Post-DFT LEC Verification ..............................................................................32
10.4.3 Lockup Latch Verification .....................................................................................................34
10.5 Run ET ATPG ...............................................................................................................................35
11 Intepreting DFT LINT Message ........................................................................................................38
11.1 Checking PI Registering Warning Messages .................................................................................38
11.2 Checking PO Registering Warning Messages ...............................................................................39
12 Static Timing Analysis (STA) Modes ...............................................................................................40
12.1 Scan Shift Mode ............................................................................................................................40
12.2 Scan Capture Mode .......................................................................................................................41
12.3 Functional Mode ............................................................................................................................43
12.4 JTAG Mode ...................................................................................................................................44
13 Revision History ................................................................................................................................45
1 INTRODUCTION
This application note introduces version 6 of the TSB DFT flow. This flow is designed
to insert DFT logic to a TSB to make it friendly to test. More specifically this involves:
- Design and DFT set up
- WIR (Wrapper Instruction Registers) insertion
- IEEE 1500 wrapper cell insertion
- Compressed scan chain stitching
- Functional lockup latch insertion
- Hierarchical test compression macro insertion
- ATPG and LEC scripts generation
- Verification of the logic inserted
The term TSB has been loosely used in various contexts within PMCs design flow.
Here, this term denotes any block designed within a chip/device that is large enough (area
and gate-count wise) to be a layout region and/or a DFT region. Such a region can be,
but does not have to be, a functional standalone entity. The key point in partitioning a
device into DFT regions is the size of each region and the I/O interface to the neighboring
regions. To avoid insertion of extra DFT logic, it is recommended to ensure that the
primary I/Os of the DFT region (referred to as TSB) are directly connected to flops
inside.
This flow makes use of the following EDA tools: Cadence RTL Compiler (RC),
Cadence Encounter Test (ET), and Cadence Conformal LEC. Here are the versions of
each tool which are required in this flow:
- Cadence RTL Compiler (RC): v14.20-p005_1.lnx86
- Cadence Encounter Test (ET): v14.1.102
- Cadence Conformal LEC: lec.14.20-p100.lnx86
This application note starts by describing the DFT hierarchies and structures to be
inserted into the TSB (section 4). It then provides a high-level description of the flow to
state the general purpose of each DFT step (section 7). Then it provides a detailed
description of the flow to describe exactly how to run each step such as filling in the main
metadata file, invoking scripts etc. (section 9).
2 CONTEXT
This component is created as part of the overall DFT flow maintained within PMC. The
following are links to parent/sibling components to this flow:
cad_dd_00693 - Top-level Design for Testability Methodologies (v004)
cad_dd_00764 - AC Scan Home Page, for different flavors of ATPG flow
3 REFERENCE
The following are the references for this flow:
IEEE 1500 Standard Testability Method for Embedded Core-based Integrated Circuits:
http://bby1dms01/DocMgmt/getfile.cfm?file_id=392187
Design for Test in Encounter RTL Compiler:
/tools/cds/RC/unsupported/v14.20-s008_1.lnx86/doc/rc_dft_ug/rc_dft_ug.pdf
4 TSB DFT BLOCK LEVEL VIEW
scan_out
scan_out
(CTO)
(CTO)
Input wrapper cell Output wrapper cell
Primary from core
input logic
(CFI) (CFI)
1 To core logic Primary
D Q 0 1 Output
D Q 0 (CFO) 0
D Q D Q 0 (CFO)
1 scan_in 1
E (CTI)
E
clk
Select_cfi
fll_clk
scan_in
clk
Select_cfi
(CTI)
Select_cti
fll_clk
Select_cti
WSE DFTSE WSI WPI WPI_feedout
pmxxxx
Decompressor COMP_EN
WIR_SI
WIR
.
WIR Update Registers
WIR Shift Registers
Decoder
RAM wrapper
Logic
...
WSC
(WCK TIM ram_iddq_en
...
WRSTN
WBY
selectWIR scan_en_o
shiftWR
fll_clk
updateWR
captureWR) scan_en_c
ramscanb
RAM sequencer scanb
bist_jtag_sel
rd_udrb
WIR_SO bist_jtag_si
bisttest_jtag_sel
RAM DFT Connector update_dr
Purely wire feedthroughs bisttest_jtag_si
shift_dr
tck
trstb
bisttest_jtag_so
testclk_selb bist_jtag_so
X-Masking MASK_EN
MASK_EN_1
Compressor
WSO MASK_LD so_drvb WPO_feedin WPO

WPO_or
WPO_or_feedin
Figure 1 TSB DFT block level structure
The above diagram is a high-level depiction of the TSB structure. The top level hierarchy
of this DFT region is the design pmxxxx, and all the DFT scan related logic is inserted at
the same level of the design.
5 DIFFERENCES FROM PREVIOUS RELEASE
5.1 New Features are Supported in this Release
Reduced impact of DFT on RTL development

Since the TSB DFT v006 flow only supports reading in the netlist after synthesis and
RAM BIST insertion, and all the DFT related logic is added in the same level of the TSB
design, designers are no longer required to wrap their design with DFT centric RTL.
This eliminates DFT logic insertion at RTL design stage, which
Allows for cleaner RTL simulations without the clutter of DFT hierarchy and
instances (reference CAD Prep 110589)
Decouples RTL parameterization and vaulting with DFT implementation
(reference CAD Prep 118349)
Add/remove in functional port do not imply regeneration of DFT RTL
Synergies with Cadence compression and Cadence ATPG algorithms

Compression logic and ATPG solutions will now both be Cadence-based strategies.
Therefore, PMC will be positioned to take advantage of any synergies between the
Cadence compression logic and ATPG algorithms. The TSB DFT v006 flow now
provides the following new features:
In addition to the Illinois style decompressor structure, users can now choose
XOR style decompressor.
Unlike the simple XOR compressor in TSB DFT v005 flow, the XOR
compressor in this flow is optimized to leverage Cadence ATPG algorithms.
The option to insert X-masking logic. If X sources exist in the design, they could
damage data in compression and therefore, reduce the test coverage. X-masking
logic can be useful in these cases since it eliminates the X before it can corrupt
other scan data in compression logic.
Faster run times for DFT logic insertion

This flow uses the Cadence RC native compiled code to identify and insert the IO
Wrapper Cells, which is more than 2x faster than the TCL scripts used in the TSB DFT
v005 flow.
Test insertion will be consolidated into one RC job

TSB DFT v005 flow involved multiple RC runs. However, only one call to RC will be
required in this flow for all test logic insertion. By consolidating DFT insertions into one
RC job, users will need to make fewer requests for RC licenses to accomplish test
insertion in a netlist, which will reduce license queuing, and enable improvements in
license and CPU utilization.
Moving to IEEE 1500 standard structures

The TSB DFT v006 flow involves in IEEE 1500 standard structures which are widely
used in industry and support more features than in the TSB DFT v005 flow:
Replaced the DFT UDR in TSB DFT v005 flow with the IEEE 1500 standard
defined WIR (Wrapper Instruction Registers).
TIM (Test Interconnect Macro) is inserted at the block level, which provides a
standard test bus interface for each DFT region.
Bypass registers are inserted for bypassing different test modes.
RAM DFT Block is required for interfacing the RAM BIST to the
control logic
Instead of using rbist_concat_in/rbist_concat_out bus to control and connect RAM
BIST inside a design in the TSB DFT v005 flow, a block called the RAM DFT
connector is inserted by the RAM BIST insertion flow, and it will be configured and
reconnected in the TSB DFT v006 flow to communicate to the RAM BIST logic.
In order to insert the RAM DFT connector block, the RAM BIST insertion flow with
tag incremental_113_for_new_dft_test_all is required. The RAM DFT connector
block will be the new interface block between the RAM BIST logic to the outside
control.
Support for Pre-stitched sub blocks

Integration of pre-stitched sub blocks are supported from release tag incremental_4 and
onwards. If a sub block is pre-stitched with scan chains inside, users can specify them in
the DFT info file through the dont_touch_blocks/dont_touch_module variables. It is
very similar as the TSB DFT v005 flow, but the TSB DFT v006 flow requires more
information such as the chain type and the wrapper mux select signal. Please refer to the
DFT info template for the details.
5.2 Features Currently Not Supported in this Release
- FLLs (Functional Lockup Latches) are not inserted based on the clock grouping
specified in the scan_clocks array in the DFT info file. Instead, users have to
explicitly specify the paths in the 'fll_insertion_path' list in the DFT info file if
they want to insert any FLLs.
- IB/OB chain AND gates are not currently inserted in this flow, it will be
considered in future releases.
- To run ATPG, this flow provides a RC generated ET ATPG script. A PMC
featured ATPG flow will be implemented at a future date which will be
compatible to this flow.
- To run LEC between the pre-stitch and post-stitch netlist, this flow provides a RC
generated LEC scripts. But, it requires some manual work to make it work. In
future, a PMC featured LEC flow will be implemented and it will be compatible
to this flow and minimize the manual work.
6 REQUIREMENTS FOR TSB DFT V006 FLOW
Although test related logic is added at gate-level, there are still some requirements at the
RTL level to prep the design for DFT processing:
(1) Creation of test ports (that can remain unconnected at RTL) for connection of test
logic at gate-level (e.g. scanb, scan_en_o, etc.)
Test logic is inserted at gate-level, and it requires test related ports at the design
block to control the scan. Normally, designers could choose to not add any of
those test ports at RTL level, and let the DFT flow to create those ports at gate-
level if needed. However, this is not the case when a design is also a layout
region. Because, if a DFT region is also a layout region, it is very likely that the
netlist generated before DFT insertion will be used for floor planning. So, if RC
adds some test ports later in the post-stitched netlist, it will be different than the
ports in floor planning. Therefore, this flow requires all the test ports creation at
the RTL level. Designers have to create those ports which will be described in the
following section, and leave them unconnected in RTL.
(2) RTL simulations should include a toggle of trstb and WRSTN to ensure the
WIR (which will be inserted at gate level) places the design in functional mode,
by default.
If designers want to reuse the test bench generated from RTL simulation in the
gate-level simulation, then RTL simulation should include a toggle of trstb and
WRSTN. It is because that RTL simulation is under functional mode, and at
that stage, WIR is not inserted yet. Gate-level simulations are based on the
poststitch netlist, which has the WIR logic inserted. In order to put a design in
functional mode, the trstb and WRSTN signals have to be toggled. Otherwise,
Design cannot be set into the correct mode. Therefore, requiring a toggle of
trstb and WRSTN is recommended at the RTL level simulation to allow for
consistency between RTL and gate level functional test benches.
(3) In order to run TSB DFT v006 flow, a new RAM BIST version tag
incremental_113_for_new_dft_test_all is required, which is the compatible
version that accompanies this flow.
In this new RAM BIST tag, it inserts an interface block, RAM DFT connector
block (as shown in Figure 1). The portion of RAM BIST connection logic that
was generated by the TSB DFT v005 flow at the DFTW level is now inserted at
the design core level during RAM BIST insertion. Similarly, the RAM DFT
connector block is inserted during RAM BIST insertion as well, which is an
interface block between the RAM BIST to the outside controls. In TSB DFT v005
flow, the communication to/from the RAM BIST is through the rbist_concat_*
buses, and the bus width could be changed based on the number of RAM BIST
wrappers that exist in the design. However, in the TSB DFT v006 flow,
rbist_concat_* buses no longer exist in the design, and the communication
to/from the RAM BIST is through the RAM DFT connector block. The input or
output bus width of this block is always a fixed number, and it does not change
based on the number of RAM BIST wrappers or controllers. The new RAM BIST
insertion flow will take care of the configuration and connection to the multiple
RAM BIST controllers, if specified by the user. More specifically, there are only
feed-through wires inside the RAM DFT connector block.
If RAM exists in the design, please make sure to run through the RAM BIST
insertion flow using the new tag incremental_113_for_new_dft_test_all before
running the TSB DFT v006 flow.
(4) The TSB DFT v006 flow uses Cadence RTL Compiler (RC) version v14.20-
p005_1.lnx86. In this version, the / at the end of some set_attribute
commands is not accepted. Therefore, in the synth_init.rctcl file, set_attribute
does not need / for the following commands:
Please replace:
if {[info exists ::scan_flops_list]} {
set_attribute -quiet avoid false $::scan_flops_list /
}
foreach dont $dont_use_list {

set_attribute avoid true [find / -libcell $dont] /
}
With:
if {[info exists ::scan_flops_list]} {

set_attribute -quiet avoid false $::scan_flops_list
}
foreach dont $dont_use_list {

set_attribute avoid true [find / -libcell $dont]
}
(5) The TSB DFT v006 flow requires a special ET license for embedded hierarchical
test insertion in both RC runs and ET runs. The license is called
ET_Hierarchical_Option. Currently, it only exists in the QA pool, not in the
peak pool. Please refer to the Knowledge Base #1682 for how to apply for access
to the QA pool.
After users get the access to the QA licenses, please invoke the RC job and ET
job with the -qa switch. Refer to the section 9.4 for the details.
7 TSB DFT STRUCTURE
7.1 Scan Chain Construction
Scan chains are created at the level of the TSB. They are divided into two groups:
(1) those linking all the flops connected from primary inputs/outputs called wrapper
boundary chains (including IB chains and OB chains)
(2) those linking the rest of the flops talking to other flops called core chains
In this flow, it is possible that the input wrapper boundary flops (IB flops) and output
wrapper boundary flops (OB flops) are mixed on the same wrapper boundary chains, but
they are controlled by separate scan shift enables (i.e. DFTWSEI for IB flops, and
DFTWSEO for OB flops) and separate mux selection signals (i.e. INTEST for IB cells,
and EXTEST for OB cells). The shift enables and mux select signals for input/output
wrapper boundary cells are driven by WIR logic as opposed to block level ports. All the
wrapper boundary cells are inserted at the DFT design level, which register the I/Os to
prevent X propagation during ATPG. They are bypassed in functional mode to avoid
addition of unwanted cycle latency on the data-paths.
7.2 TSB Description (pmxxxx)
A key difference between TSB DFT v005 and TSB DFT v005 is that it is no longer
required to first create a TSB core. In TSB DFT v005, users were required to first
create a TSB core upon which scripts would wrap the core to form the overall DFT
region. In contrast, in TSB DFT v006, the TSB itself is level of hierarchy at which test
logic is inserted no core or wrapping with additional hierarchy is required. A TSB is
typically an intuitive functional unit. All functional descriptions pertaining to this module
and modules below are the responsibility of the TSB designer(s). Since this is a manually
created hierarchy, please ensure it follows all the naming rules listed below:
Please ensure that the module name of this level be called <TSB_name>, where
<TSB_name> is the name intended for the TSB. Although <TSB_name> can be any
alphanumeric string, usually each TSB is assigned a PM number, so it is customary to set
TSB_name to the PM number. For example, for a TSB can be named pm1234.
The following is a list of DFT reserved port names. As mentioned in section 5, please
specify them in the RTL when defining the TSB module. Those ports will be connected
to test logic during scan insertion. Define them as an input or an output (as appropriate),
and leave them as unconnected in RTL. Port names are case sensitive to comply with the
IEEE 1500 standard.
DFT reserved port names:

Inputs:
WPI
WPO_feedin
WPO_or_feedin
WSI
WSE
DFTSE
WRCK
WRSTN
SelectWIR
ShiftWR
UpdateWR
CaptureWR
MASK_EN
MASK_EN_1
MASK_LD
COMP_EN
SPREAD_EN
fll_clk
testclk_selb
scanb
scan_en_o
so_drvb
Outputs:
WPI_feedout
WPO
WPO_or
WSO
If RAM exists in the design, please also define the following ports in the RTL module
defination:
Inputs:
trstb
tck
shift_dr
update_dr
rd_udrb
ramscanb
scan_en_c
bisttest_jtag_si
bisttest_jtag_sel
bist_jtag_si
bist_jtag_sel
fll_clk
ramscanb
scanb
scan_en_c
scan_en_o
ram_iddq_en
Outputs:
bist_jtag_so
bisttest_jtag_so
The following is a list of port with DFT significance. When coding the TSB, please
avoid assigning these names to any functional port unless the port is intended for the DFT
operation described by the corresponding bullet below.
Inputs:
WPI: Wrapper Parallel Input bus for parallel scan chains. The width of this bus is the
scan bus width.
WPO_feedin: Input bus to serve as feed-through for WPO. It is ANDed onto the
WPO bus of the TSB. This is used to daisy-chain outputs of TSBs at chip-level.
WPO_or_feedin: Input bus to serve as feed-through for WPO_or. It is ORed onto
the WPO bus of the TSB. This is used to daisy-chain outputs of TSBs at chip-level.
WSI: Wrapper Serial Input port. The scan input port for serial scan test modes.
WSE: Wrapper Shift Enable signal used to generate the shift enables for input
boundary wrapper cell and output boundary wrapper cell. The inputs boundary
wrapper cell shift enable signal: DFTWSEI = WSE | INTEST; the output boundary
wrapper cell shift enable signal: DFTWSEO = WSE | EXTEST.
DFTSE: The shift enable signal for the core chains.
WRCK: The IEEE 1500 clock which is connected to sequential logic in the WIR.
WRSTN: The IEEE 1500 active-low reset which is connected to sequential logic in
the WIR.
SelectWIR: The IEEE 1500 wrapper terminal that determines the selection of a
wrapper register (WR). A value of 1 represents selection of the wrapper instruction
register (WIR), and a value of 0 represents selection of a wrapper data register
(WDR).
ShiftWR: The wrapper terminal used to enable and control a Shift operation in the
selected IEEE 1500 wrapper register (WR).
UpdateWR: The wrapper terminal used to enable and control an Update operation in
the selected IEEE 1500 wrapper register (WR).
CaptureWR: The wrapper terminal used to enable and control a Capture operation in
the selected IEEE 1500 wrapper register (WR).
MASK_EN: Mask enable signal to enable the X-masking logic to block the scan
channel outputs.
MASK_EN_1: Mask enable signal to enable the X-masking logic to block the scan
channel outputs. This port is only used if wide2 type of X-masking logic is inserted.
MASK_LD: Mask load signal to enable loading of mask flops.
COMP_EN: Compression enable signal. Active-high signal to route scan chain
through expansion/compression logic.
SPREAD_EN: Spread enable signal. The test signal that enables the XOR-based
spreader network in the decompression logic. This signal is only required if XOR
decompressor is built in the design.
fll_clk: This port controls the enable of Functional Lockup Latches (FLLs) in the
design. If there are FLLs inserted in the RTL description of the TSB by the designer,
then please drive their enables with fll_clk.
testclk_selb: This port is used to mux in scan-mode clocks for internal clock sources,
i.e. use it as the select signal of the clock mux, and drive the scan-mode test clock into
through the I0 input of the mux.
scanb: This port controls various scan mode gating/muxing within the TSB other
than clock muxing.
scan_en_o: The enable signal controls the SE pin of ICG cell.
so_drvb: Active-low signal to enable values to be output to WPO (and WPO_or).
Default value is 1, which prevents WPO to change by masking all bits on the bus to 1
(and all bits on WPO_or to 0).
Outputs:
WPI_feedout: Output bus to serve as feed-through for WPI. This is used to daisy-
chain outputs of TSBs at chip-level.
WPO: Wrapper Parallel Output bus for parallel scan chains. Width is the scan bus
width.
WPO_or: Another version of the TSB WPO bus. It is used for parallel testing of
identical TSBs at the chip-level. Please refer to the top-level DFT methodology
(cad_dd_00693), scan_out_or bus.
WSO: Wrapper Serial Output port. The scan output port for serial scan test modes.
8 HIGH-LEVEL DFT FLOW DESCRIPTION
Start
1 defaults.tcl Setup DFT using tsb_dft_setup.tcl

- scan/tsb_dft/*
- formalv/tsb_dft/*
2 Fill out TSB info file pm1234_dft_info.tcl
synth_init.rctcl
RAM .lib list file Design and DFT set up
dft_procs.tcl
pm1234_prestitch.v
WIR insertion
IEEE 1500 wrapper cell insertion
pm1234_dft_flop.rpt
Compressed scan chain stitching pm1234_dft_core_wrapper.rpt
pm1234_tsb_dft pm1234_before_itc_scan_chains.rpt
_impl.rctcl 3
FLL insertion pm1234_insert_fll_timing_path.rpt
Hier test compression macro insertion pm1234_gates.v
et_atpg/*
ATPG and LEC scripts generation
pm1234_pre_post.do
pm1234_FULLSCAN*.rpt
Scan chain verification pm1234_SERIAL*.rpt
pm1234_tsb_dft_impl.log
pm1234_pre_
post.do 4 pm1234_pre_post.do Pre-DFT vs. Post-DFT LEC (Conformal) pm1234_pre_post.log
pm1234_verify pm1234_verify_ll.gt.tcl pm1234_verify_ll.rpt

_ll.gt.tcl 5 .synopsys_pt.setup
LL verification (GoldTime)
pm1234_verify_ll.log
et_atpg/tbdata/*
runet.atpg 6 et_atpg/runet.atpg
et_atpg/*
Run ET ATPG
et_atpg/testresults/*
et_atpg/pm1234_DIR/*
et_atpg/runet.log
Done
Figure 2 TSB DFT v006 flow chart
Figure 2 provides a high-level view on TSB DFT 006. It is broken down into 6 stages.
8.1 Stage 1: DFT Setup
This stage is meant to setup the DFT directories for a given TSB. This involves
populating the source codes from the ICDC vault (cad_dd_01017) using get_icdc_comp,
and running tsb_dft_setup.tcl to setup the TSB directory with sub-directories, files,
and scripts used by downstream steps of the flow.
8.2 Stage 2: Fill Out TSB Info File
One of the files generated through the previous stage is a generic DFT info file that needs
to be filled with design-specific information by users. Please refer to section 9.3 for more
details. After properly filling out the info file, all downstream DFT steps become
automated.
8.3 Stage 3: DFT Implementation
This stage takes the pre-DFT netlist generated from synthesis and inserts all needed DFT
logic on it to form the post-DFT netlist. This run includes the following steps:
Design and DFT set up: This step reads in the TSB pre-stitched netlists (RAM BIST
inserted), defines the scan control signals (e.g. scan clocks, resets, pin constraints, test
bus ports for WIR and compression, etc.). It also checks the DFT rules for any violations.
WIR insertion: WIR stands for Wrapper Instruction Register, which is the IEEE 1500
standard and is very similar to the DFT UDR (User-Defined Register) in the TSB DFT
v005 flow. This step inserts the WIR block, and makes the appropriate connections.
During scan testing, the WIR loads the instructions to its shift registers from the chip
level TAP controller, decodes the instructions, and stores them into its update registers,
then controls the TSB into different test modes.
IEEE 1500 wrapper cell insertion: This step checks all the PIs and POs of the TSB
whether they are correctly registered by flops. If a PI/PO is not natively registered by
flops through buffers and inverters, then, it may lose test coverage in block level ATPG.
Therefore, this step checks the status of each PI/PO, inserts dedicated wrapper cells on
PIs/POs which are not natively registered, and defines the flops which are directly
connected to PIs/POs as the shared wrapper cells. Both the dedicated wrapper cells and
shared wrapper cells will be stitched on the wrapper boundary chains during the scan
chain stitching step.
Compressed scan chain stitching: This step calculates the number of each type of scan
chains (i.e. IB/OB/core chains) based on user information (e.g. compression ratio and
WPI bus width) as well as the flop count. The total number of compressed chains created
is the external WPI/WPO bus width multiplied by the compression ratio. Then, it defines
and connects the scan chains with compression on. If prestitched sub-blocks exist in the
design, this step also provides automatic connections between the sub-block scan signals
to the corresponding top module control signals based on the user information in the DFT
info file. And, it stitches the pre-existing sub block scan chains to the corresponding top
module scan chains.
Functional LL insertion: This step inserts Functional Lockup Latches (FLLs) on the
cross-clock paths in the design. For each crossing, an active-high latch is inserted
immediately before the endpoint of the crossing and enabled by fll_clk.
Hierarchical test compression macro insertion: This step inserts test compression logic
to configure the scan chain expansion/compression. The following test modes can be
generated by inserting this macro:
- fullscan_intest
- fullscan_extest
- fullscan_bypass
- serial_intest
- serial_extest
- serial_bypass
- compression_intest (with broadcast decompressor)
- compression_extest (with broadcast decompressor)
- compression_bypass (with broadcast decompressor)
- compression_decompression_intest (with broadcast + XOR decompressor)
- compression_decompression_extest (with broadcast + XOR decompressor)
- compression_decompression_bypass (with broadcast + XOR decompressor)
Optionally, users can insert X-masking logic in the compression to block the X-sources
which may damage the compression data in ATPG.
ATPG and LEC scripts generation: This step runs the RC native commands to
generate the LEC do file and the ET ATPG run scripts.
Scan chain verification: This step generates series of scan chain reports for different test
modes: fullscan, fullscan_intest, fullscan_extest, fullscan_bypass, serial_intest,
serial_extest, and serial_bypass modes. Users should examine those reports for any
broken scan chains. (Please note that because RC does not understand scan chain
compression logic, it is not possible to trace the scan chains while turning compression
on. This checked is done during ATPG.)
8.4 Stage 4: Pre-DFT vs. Post-DFT LEC
This is a Conformal LEC run that checks for logic equivalence between the pre-DFT
netlist and the post-DFT netlist. Its purpose is to ensure that the DFT implementation
steps did not inadvertently change the TSBs functionality. Therefore, one should expect
the result of the run to be that the two netlists are functionally equivalent. Currently, this
RC generated LEC scripts requires some manual modifications (please refer to section
9.4 for details). In future, a PMC featured LEC script generator will be implemented,
which will be compatible with the TSB DFT v006 flow.
8.5 Stage 5: LL Verification
This is a GoldTime run that verifies that all scan path lockup latches and FLLs are
correctly inserted. This is done by hold check techniques in which huge clock
uncertainties are applied at clock crossings, and the presence of an LL at the crossing will
prevent the hold violation from being reported.
8.6 Stage 6: Run ET ATPG
This run is optional for the users. If users want to run ATPG on the DFT implemented
TSB with TSB DFT v006 flow, then, they can run this RC auto generated ATPG scripts.
But in future, a PMC featured ATPG script generator will be implemented, which will be
compatible with the TSB DFT v006 flow.
9 A BIT ON TCL
As will be seen later, one main step in running the TSB DFT flow involves filling out a
DFT info file. This file is in tcl format. Therefore, it may be worthwhile to quickly
explain the tcl construct used within the file. For more details on tcl, please refer to
Tcl/Tk references such as Practical Programming in Tcl and Tk, 3rd edition, Welch.
9.1 Back-slashes \
The basic usage of a \ is serving as an escape character that makes the tcl interpreter
ignore the character after it (escape it). This is generally used to control wrap-around of
long lines to line up columns of text. (There are other uses for \ beyond the scope of
this discussion. Please refer to a tcl manual for more details.) In the example below, the
\s is used to escape carriage-returns so that all three lines actually forms just one line to
the tcl interpreter. Please note that nothing can be added after the \ in this case or the
carriage-return cannot be escaped.
set scalar_data [ list \

trstb 1 \
bist_rstb 1 ]
9.2 Comments
A line that starts with # is a comment and ignored complete by the interpreter. Please
note that \ takes precedence over #. Therefore it is a good idea to keep comments
away from continuations of tcl statements (\).
9.3 Scalar Variable and Lists

A scalar variable can hold any string, number, symbol or list. One can provide a value to
a scalar variable by using the set command. The tcl language centers around lists. A
list is a string delimited by white space. Elements within the list are ordered from 0 to n-
1 where n is the total number of elements in the list. A list can be created by enclosing a
series of elements by {} or or by issuing the list command. In the above example, the
scalar variable scalar_data now holds a list with 4 elements: trstb, 1, bist_rstb, 1.
9.4 Array
An array is a variable that holds key-value pairs. It can be thought of as a hash where the
keys are unique and the value associated with each key can be any string, symbol or list.
The array can be filled with the array set command. For example, the following
command creates an array called scan_resets with two keys, trstb and bist_rstb. The
values for both keys are 1.
array set scan_resets [ list \
trstb 1 \
ejtag_trstb 1 \
global_rstb 1 \
mc_rstb 1 \
]
9.5 Nesting of Lists

Lists can be nested, i.e. each element of a list can also be a list. For example, the
command below stores a 3-element list into a scalar-variable called design_files, and
each element is also a list.
set design_files \
[ list \
[ list ../gates/${top_module}_prestitch.v ] \
]
As another example, the command below creates an array called scan_clocks with five
keys, tck, ejtag_tck, test_pclk, test_sclk and test_bistclk. The value of key tck is its
offstate 0.
array set scan_clocks [ list \

tck 0 \
ejtag_tck 0 \
test_pclk 0 \
test_sclk 0 \
test_bistclk 0 \
]
10 DETAILED FLOW DESCRIPTION
Each sub-section below represents a step in the DFT flow.
10.1 Populate
Command:
cd ()/scripts/
get_icdc_comp cad_dd_01017
Output:
Populated files in ../depend/unmodified/cad_dd_01017_dd/
Description:
The flow assumes that the proper development directory has been set up by running
start_tsb.prl. From the scripts/ directory of the parent TSB directory, invoke
get_icdc_comp to grab a copy of the flow out of the vault. The resulting repository is
mentioned in the output section above.
10.2 Setup DFT
Command:
../depend/unmodified/cad_dd_001017_dd/tsb_dft_006/scripts/tsb_dft_setup.tcl \
pm1234
Output:
Created the following directory and populated the related files:
All files related DFT invocation scripts/chain reports/verification/fll insertion are at
../scan/tsb_dft/
All files related to pre-DFT vs. post-DFT formal verification are at
../formalv/tsb_dft/
This directory will hold the final TSB netlist file after DFT implementation proceeds:
../gates/
Description:
In this step, the TCL script tsb_dft_setup.tcl is invoked to setup all DFT sub-
directories with the necessary files to complete the DFT flow. Invoking the script
without any arguments will display the usage of the script. The first argument of the
script is the name of the TSB, usually the PM number. From this point forward
pm1234 will be used to denote the TSB name.
10.3 Fill Data File
Command:
Modify ../scan/tsb_dft/pm1234_dft_info.tcl
Description:
One of the files populated by step 10.2 is the DFT info file pm1234_dft_info.tcl located
at ../scan/tsb_dft/. User is asked to fill out this data-file with design-specific
information such as clock pins, reset pins, etc. This file is referenced by all downstream
script/tool invocations to perform DFT implementation and verification. The following is
a description of every variable in the data file.
The data file is divided into 4 sections: design and DFT setup, IEEE 1500 wrapper cell
insertion, scan stitching and compression insertion, Functional Lockup Latch insertion,
and ATPG and LEC scripts generation.
10.3.1 Design and DFT Set Up Section
This section contains entries used for setting up the design and DFT. Below are the
descriptions of each variable:
set top_module pm1234
The scalar variable top_module is the name of the TSB. The data file is already created
with the standard naming conventions, so this variable usually does not need to be
changed. However, please ensure that the TSB name in the netlist file corresponds to the
name given to top_module.
set design_files \
[ list \
[ list ../gates/${top_module}_prestitch.v ] \
]
The tcl variable design_files is a two-level nested list containing a comprehensive list of
files that fully resolve the TSB pm1234. The files can be gate-level descriptions,
and/or list files of the TSB gate-level descriptions. Only netlists (not RTL) are
supported here. So, please only specify netlists in the design_files list.
# option 1: individual files

# [ list <netlist file> ]
# option 2: list files
# [ list <.list_file> ]
The above are the two supported options for specifying the netlist files in design_files
list. Users can choose whether to specify all the required netlists separately in
design_files using option 1, or put all the netlists into one .list file, and specify only the
.list file in design_files using option 2.
The order in which the files are declared has significance. Since design files A may
depend on file B to compile properly, it is necessary to declare B in front of A.
set rambist_inserted no
The scalar variable rambist_inserted defines whether RAM BIST is inserted in the
design. If the given DFT region/TSB does not have any RAMs or RAMBISTs, specify
the variable rambist_inserted to no; otherwise, specify it to yes. Default is no.
array set scan_resets [ list \

trstb 1 \
ejtag_trstb 1 \
global_rstb 1 \
mc_rstb 1]
The variable scan_resets is an array containing the scan-mode asynchronous reset ports of
the TSB. The keys of the array are the port names and the value associated with each key
is the reset ports off-state. Active-low resets have offstate of 1. Specify trstb only if
it exists in the design. Please make sure none of the ports mentioned in scan_resets
array drive synchronous resets in the design.
array set scan_clocks [ list \

tck 0 \
ejtag_tck 0 \
test_pclk 0 \
test_sclk 0 \
test_bistclk 0 \
]
The variable scan_clocks is an array containing the scan-mode clock ports of the TSB.
The keys of the array are the port names, and the value associated with each key is the
offstate (rise-edge clock has an offstate of 0). Unlike TSB DFT v005 flow info file, there
is no need to specify the name of the scan-mode driver source to the clock port at chip-
level. Therefore, no Functional Lockup Latches (FLLs) will be automatically inserted by
the flow based on the info in this array. For FLL insertion, please refer to the
fll_insertion_path list.
array set user_pin_constraints [ list \

user_pin 0 \
]
The variable user_pin_constraints is an array containing the user-defined pin constraints
of the TSB. The keys of the array are the port names and the value associated with each
key is the value to be held during test mode (i.e. scan shift and scan capture modes).
10.3.2 IEEE 1500 Wrapper Cell Insertion Section
set ignore_reg_func_pi [list ]

set ignore_reg_func_po [list ]
The ignore_reg_func_pi and ignore_reg_func_po variables contain lists of

functional data input ports (PI) and output ports (PO) respectively that can be ignored
during input/output registering checks of the RTL DFT lint run. If a PI/PI port is defined
in the above two lists, it will be excluded from IEEE 1500 wrapper cell insertion.
Usually, these lists should be left empty to best position the design for optimal test
coverage.
set add_dedicated_regs_on_pi [list ]

set add_dedicated_regs_on_po [list ]
The add_dedicated_regs_on_pi and add_dedicated_regs_on_po variables contain

lists of functional data input ports (PI) and output ports (PO) respectively that users want
to force a dedicated IEEE 1500 wrapper cell on each of them. If a PI is defined in
add_dedicated_regs_on_pi list, then, a dedicated input wrapper cell will be inserted
between this PI and the inside logic it is driving. Similarly, if a PO is defined in
add_dedicated_regs_on_po, an output wrapper cell will be inserted between this PO and
its driven logic. Usually, these lists should be left empty to avoid duplicated wrapper
insertion.
set input_shared_threshold 1
set output_shared_threshold 1
The input_shared_threshold and output_shared_threshold variables specify the

maximum number of scannable flops that can be shared in wrapper cell insertion. When
the number of scannable flops exceeds the specified threshold value, a single dedicated
wrapper cell will be inserted for the input/output port. Default is 1, which is the same as
the TSB DFT v005 flow.
For example, if the threshold in both variables are set as the number of X, then, for each
PI/PO, if RC finds that the number of the related shared wrapper cells is equal to or less
than X, then, those flops will be put onto the wrapper boundary chains, and no
dedicated wrapper cell will be inserted on this port. However, if this number is larger
than X, then RC will insert a dedicated wrapper cell on this PI/PO, and it will be put
onto the wrapper boundary chains. All the other flops will be put onto the core chains.
set insert_dedicated_cells_on_feedthrough_path yes
The variable insert_dedicated_cells_on_feedthrough_path controls whether to

insert the dedicated wrapper cells on any feed-through path. Setting this variable to 'yes',
RC will put two dedicated wrapper cells (one for input, one for output) on a purely feed-
through path (through buffers or inverters). If it is 'no', no dedicated cell will be added.
Default is 'yes'.
In TSB DFT v005 flow, for a purely feed-through path, only one input wrapper cell will
be added. However, Cadence RC currently does not support this feature. RC will insert
either two or none wrapper cells according to this setting. Therefore, leave this variable
for now until the feature of adding only input wrapper cell on feed-through paths is
supported and implemented in RC.
set ib_chain_add_regs [ list ]

set ob_chain_add_regs [ list ]
The ib_chain_add_regs and ob_chain_add_regs variables contain lists of flops to be

stitched as part of the wrapper input boundary (IB) chains and wrapper output boundary
(OB) chains respectively. This is on top of the flops already assigned to the IB and OB
chains by the RC parsing. For example, candidates for OB chains are flops controlling
enable logic of the boundary flops. The pathnames of these flops start from inside the
TSB (ie. <flop_name>_inst).
10.3.3 Compression Insertion and Scan-stitch Section
set wpi_bus_width 8
set compression_ratio 10
The scalar variable wpi_bus_width defines the width of the wrapper parallel scan bus at
the TSB. The number of wpi_bus_width is also the number of scan chains in full scan
test modes. This number multiplied by the value given to compression_ratio is the
number of scan chains in compressed scan test modes.
The value of wpi_bus_width is determined by the top-level scan-pin sharing analysis.

Usually, the larger this number is, the more efficient (shorter test time) scan testing
becomes because the chains become shorter. However, since only digital pins can be
reused for scan purpose and some of these pins may be timing critical, the choices of pin
selection for WPI/WPO may become limited. Please work with the top-level integration
engineer to determine the optimum WPI/WPO bus pin count. This work is in
conjunction with scan clock/reset pin sharing as well.
By default, the value of compression_ratio is 10. Users can decide how many
compressed scan chains they want to create based on the size of the TSB design. Usually,
the recommendation is to choose a compression ratio which can ensure the average
compressed scan chain length is around 200 (flops). This number can be adjusted if the
TSB contains a hardmacro with an unreasonably long chain inside (heavy chain
imbalance).
set overwrite_default_iob_width no
set manual_ib_chain_width 6
set manual_ob_chain_width 5
The TSB DFT v006 flow calculates the widths of internal wrapper input boundary (IB)
chains and wrapper output boundary (OB) chains to achieve the best chain balancing
based on WPI bus width, the number of total flops, the number of IB/OB flops and the
compression ratio. If overwrite_default_iob_width is assigned as no, then the flow
calculated widths will be used for generating the compressed wrapper scan chains and
core chains. If user wishes to assign the widths of ib and ob chains manually, set
overwrite_default_iob_width to yes and enter the desired ib/ob chains widths to
manual_ib_chain_width/manual_ob_chain_width. This is usually not needed.
Default is no.
set decompressor xor
The variable decompressor specifies the type of the decompressor logic. The options
are: broadcast or xor. If broadcast is defined, the Illinois style of decompressor block
will be inserted. The WPI inputs will spread to the compressed inner scan chains through
wires. If xor is specified, the xor decompressor block will be inserted. And, the WPI
inputs will drive the compressed inner scan chains through the inserted XOR logic.
Please note that the XOR decompressor also keeps the functionality of the Illinois
decompressor. Therefore, if xor is specified, the design can be set into using either
Illinois decompressor or the XOR decompressor. Default is xor.
set compressor xor
The variable compressor specifies the type of the compressor logic. Only the xor
compressor block is supported in this release.
set mask wide1
The variable mask specifies whether to insert the X-masking logic, and which type of
masking logic will be used. The options are: wide1, wide2 or no. If it is no, then, no
masking logic will be inserted. wide1 and wide2 controls whether to insert wide1
type of X-masking or wide2 type of X-masking logic. Default is wide1.
Please refer to Design For Test in Encounter RTL Compiler P. 716 for the details of the
channel masking types. The location of this documentation is on the UNIX system at:
/tools/cds/RC/unsupported/v14.20-p005_1.lnx86/doc/rc_dft_ug/rc_dft_ug.pdf
set allow_mix_clock_edge_in_scan_chain yes
This variable determines whether to put different clock edge (i.e. falling edge or rising
edge) flops into one scan chain during scan chain stitching. When it is no, the stitched
scan chains will contain rising edge flops only, or falling edge flops only; when it is
yes, both falling edge flops and rising edge flops can be put into the same chain.
Default is yes because it provides optimal chain balancing.
This variable is added to support CAD Prep 111384 (UltraSoc block insides PCIE
switch). Basically, if a design contains a pre-stitched scan segment, which has a tail latch
inserted on each chain (for example, the pre-stitched UltroSoc block with tail latches
inside), this variable has to be set as no. And, this may lead to slightly less optimal
balancing of scan chains.
Please note that the tail latches can only be inserted if the pre-stitched block (e.g.
UltroSoc) contains all rising edge flops; falling edge flops in pre-stitched block with tail
latch on the scan chain is not supported for now.
set add_scan_chain_tail_latch yes
The variable add_scan_chain_tail_latch controls whether to force a tail lockup latch

at the end of a scan chain when stitching the scan chains with compression on. If it is
no, then no tail lockup latch will be inserted; if it is 'yes', an active-low lockup latch will
be added if the scan chain ends with a positive triggered scan flop, and it is driven by the
same clock of the last scan flop on that chain. No tail latch will be added if a scan chain
ends with a negative triggered flop. Setting this to yes, it can ensure each compressed
scan chain ends with a negative triggered element, which can avoid possible cross timing
violations when serializing/concatenating stubby chains together. Default is yes.
set add_scan_chain_head_flop yes
The variable add_scan_chain_head_flop controls whether to insert a D flip flop (head

flop) at the beginning of a scan chain when stitching the scan chains with compression
on. If it is no, then no head flop will be inserted; if it is 'yes', an-active high D flip flop
(head flop) will be added if the scan chain starts with a negative triggered scan flop, and
it is driven by the same clock of the first scan flop on that chain. No head flop will be
added if a scan chain starts with a positive triggered flop. Setting this to yes, it can
ensure each compressed scan chain starts with a positive triggered element, which can
avoid possible cross timing violations when serializing/concatenating stubby chains
together. Default is yes.
set ignore_flops_for_scan [list ]
The ignore_flops_for_scan variable contains a list of flops that the user purposely
wishes to exclude from being put on scan chains. The norm is to put every flop possible
onto scan chains to achieve good test goals (high test coverage, low pattern count).
However, it may be desirable for some designs to exclude certain flops from the random
shifting that would occur during scan shifting. An example would be JTAG UDR flops
that configure an ABC inside the DFT region. The full instance name of the flop(s) would
be defined in this variable to exclude them from being placed onto scan chains.
set dont_touch_blocks {}
The dont_touch_blocks array contains definitions of hard-macros. Please refer to the

comments in the DFT info file for more details. If the TSB contains no hard macros that
should be left non-scanned, simply declare the array and leave it empty.
As mentioned earlier in this document, pre-stitched sub blocks are supported in the latest
release (i.e. tag incremental_4 and higher). Please specify the pre-stitched sub block scan
chains in this section. Refer to the instructions in the DFT info template for how to
specify the information to include the prestitched sub-block scan chains.
10.3.4 Functional Lockup Latch Insertion Section
set fll_insertion_path [ list \

]
This variable fll_insertion_path manually specifies the paths where to insert the
functional lockup latches (FLL). In TSB DFT v006 flow, this is the only way to specify
the FLL insertion path and insert FLLs. Please explicitly specify all the FLL insertion
paths here. If the variable is defined as empty, then, no FLL will be inserted at all. Please
refer to the comments in the DFT info file for more details.
set final_netlist ../gates/${top_module}_gates.v
The final_netlist variable contains the name of the final post-DFT netlist file name.
This file will run through a suite of DFT-related verifications and can be used for ATPG
(may need to attach RAM shells for ATPG).
10.3.5 ATPG and LEC Script Generation Section
set et_atpg_dir ./et_atpg
The variable et_atpg_dir contains the directory where to put the RC generated ATPG
scripts.
set dft_library
/home/liblib/28n/cells/v1_5/mentor/dft/mentor_28n,../ram/pm1234_sprhdpgw
2048x52/pm1234_sprhdpgw2048x52.et_lib
The variable dft_library contains the libraries which will be used in ATPG run, e.g.
RAM libraries. Multiple ET libraries can be separated by comma (,).
set lec_do_file ${::dft::dev_formalv_dir}/${top_module}_pre_post.do
The variable lec_do_file contains the name of the RC generated Conformal LEC do
file. The golden netlists are the netlists defined in the design_files list; the revised netlist
is the final netlist.
10.4 Run DFT Implementation
10.4.1 DFT Implementation

Input:
../scan/tsb_dft/pm1234_tsb_dft_impl.rctcl, DFT implementation scripts
../scan/tsb_dft/pm1234_dft_info.tcl, filled out DFT info file from section 9.3.
Command:
cd ()/scripts/
less ./synth_init.rctcl (to ensure set_tech_lib and RAM .lib files
are setup correctly)
less ../scan/tsb_dft/pm1234_tsb_dft_impl.rctcl. (to see what is being
run)
rc qa -f synth_init.rctcl -f \
../scan/tsb_dft/pm1234_tsb_dft_impl.rctcl | & tee \
../scan/tsb_dft/pm1234_tsb_dft_impl.log
grep Error ../scan/tsb_dft/ pm1234_tsb_dft_impl.log
Examine ../scan/tsb_dft/pm1234_dft_flop.rpt for flops which have
passed/failed DFT rules.
Examine ../scan/tsb_dft/pm1234_dft_core_wrapper.rpt to check whether
PI/PO is correctly wrapped by shared/dedicated wrapper cells.
Examine ../scan/tsb_dft/pm1234_before_itc_scan_chains.rpt for broken
scan chains before compression insertion.
Examine ../scan/tsb_dft/pm1234_insert_fll_timing_path.rpt for
functional cross timing paths where to add the FLLs.
Examine ../scan/tsb_dft/pm1234_<FULLSCAN|SERIAL>*.rpt for broken scan
chains in different test modes.
Examine et_atpg/* directory to check whether the ATPG files are
correctly generated.
Examine the ../formalv/tsb_dft/pm1234_pre_post.do file to check
whether the LEC do file is correctly generated.
Output:
(from DFT and scan insertion)

../scan/tsb_dft/pm1234_dft_flop.rpt, status report for all the flops
../scan/tsb_dft/pm1234_dft_core_wrapper.rpt, status report for PIs/POs and boundary
cells
../scan/tsb_dft/pm1234_before_itc_scan_chains.rpt, scan chain report before
compression insertion
../scan/tsb_dft/pm1234_insert_fll_timing_path.rpt, timing report for FLL insertion
paths
../scan/tsb_dft/pm1234_FULLSCAN.rpt, scan chain report for fullscan mode
../scan/tsb_dft/pm1234_FULLSCAN_BYPASS.rpt, scan chain report for fullscan
bypass mode
../scan/tsb_dft/pm1234_FULLSCAN_EXTEST.rpt, scan chain report for fullscan
extest mode
../scan/tsb_dft/pm1234_FULLSCAN_INTEST.rpt, scan chain report for fullscan
intest mode
../scan/tsb_dft/pm1234_SERIAL_BYPASS.rpt, scan chain report for serial bypass
mode
../scan/tsb_dft/pm1234_SERIAL_EXTEST.rpt, scan chain report for serial extest
mode
../scan/tsb_dft/pm1234_SERIAL_INTEST.rpt, scan chain report for serial intest
mode
../scan/tsb_dft/ pm1234_tsb_dft_impl.log, log file
(from ATPG scripts generation)

et_atpg/et_checks.sh
et_atpg/pm1234.COMPRESSION_BYPASS.pinassign
et_atpg/pm1234.COMPRESSION_DECOMP_BYPASS.pinassign
et_atpg/pm1234.COMPRESSION_DECOMP_EXTEST.pinassign
et_atpg/pm1234.COMPRESSION_DECOMP_INTEST.pinassign
et_atpg/pm1234.COMPRESSION_EXTEST.pinassign
et_atpg/pm1234.COMPRESSION_INTEST.pinassign
et_atpg/pm1234.FULLSCAN_BYPASS.pinassign
et_atpg/pm1234.FULLSCAN_BYPASS.seqdef
et_atpg/pm1234.FULLSCAN_DEFAULT.seqdef
et_atpg/pm1234.FULLSCAN_EXTEST.pinassign
et_atpg/pm1234.FULLSCAN_EXTEST.seqdef
et_atpg/pm1234.FULLSCAN_INTEST.pinassign
et_atpg/pm1234.FULLSCAN_INTEST.seqdef
et_atpg/pm1234.SERIAL_BYPASS.pinassign
et_atpg/pm1234.SERIAL_BYPASS.seqdef
et_atpg/pm1234.SERIAL_EXTEST.pinassign
et_atpg/pm1234.SERIAL_EXTEST.seqdef
et_atpg/pm1234.SERIAL_INTEST.pinassign
et_atpg/pm1234.SERIAL_INTEST.seqdef
et_atpg/pm1234.et_netlist.v, netlist to read into ET for ATPG
et_atpg/run_compression_decomp_intest_sim
et_atpg/run_compression_intest_sim
et_atpg/run_fullscan_intest_sim
et_atpg/run_serial_intest_sim
et_atpg/runet.atpg, scripts to run ET ATPG.
(from LEC do file generation)

../formalv/tsb_dft/pm1234_pre_post.do, LEC do file
Description:
During this step, the netlist(s) of the TSB is loaded into RC to run DFT implementation.
Search the log file for any error that may have occurred. There should be none. The DFT
core wrapper report and the DFT flop report generated should be looked at in detail. The
former shows the status of each PI/PO, and whether they are registered by
shared/dedicated wrapper cells; the later shows the status of all the flops, whether they
have passed or failed DFT rules. If a PI/PO is not correctly registered, or if it has failed a
DFT rule, it may reduce the test coverage. Therefore, it may require some changes to the
design or DFT info file. Please refer to section 10 on details of interpreting the DFT
LINTing messages in log files and reports.
This step also runs WIR insertion, IEEE 1500 wrapper cell insertion, scan stitching and
compression insertion, FLL insertion, ATPG scripts generation and LEC do file
generation. Please check the generated scan chain reports, the et_atpg folder and LEC do
file for any errors and warnings.
10.4.2 Pre-DFT vs. Post-DFT LEC Verification
Input:
../formalv/tsb_dft/pm1234_pre_post.do
The invocation script to run pre-DFT vs. post-DFT formal verification. This script is
generated during the previous step (Section 10.4.1: DFT Implementation).
Command:
Edit ~/.tool_version and specify the tool version (CURRENT_CONFORMAL).
cd ()/scripts/
Modify ../formalv/tsb_dft/pm1234_pre_post.do before running LEC:
Do not run LEC with multiple CPUs:

Pre-DFT vs. post-DFT verification is a gates-to-gates comparison. This comparison
runs very quickly and using multiple CPU is not necessary. Delete the following line
from the LEC script:
set parallel option -threads 4 -license xl -norelease_license
Add additional LEC constraints:

The constraints in the LEC script generated by RTL Compiler are incomplete. Add
the following constraints in the Setup mode of the LEC script (add these constraints
before set system mode lec).
Make functional lockup latches transparent and disable scan mode:

set flatten model -latch_transparent
add pin constraint 1 fll_clk -both
add pin constraint 1 scanb -both
Disable the scan paths by setting the WIR into functional (BYPASS) mode:
add instance constraint 0 wir_instance/wir_slice_0/UpdateReg_reg \
-revised
-revised
-revised
-revised
Do not compare scan outputs that are added by our DFT implementation flow:
add ignored outputs WPI_feedout\[*\] -both
add ignored outputs WPO_or\[*\] -both
If the wrapper clock (WRCK) is connected to test clock(s) (e.g., tck) at the top level,
clock gating is added to each test clock. Constrain clock gating such that the test
clock(s) is always active. (Refer to PEPS 398588)
add pin constraints 0 COMP_EN -revised
If RAMBIST exists in the design, configure the dft_connector inputs to the same
mode as the pre-DFT design:
add primary input *dft_connector_inst*trstb_dft -pin -revised
add pin constraint 1 *dft_connector_inst*trstb_dft -revised
add primary input *dft_connector_inst*tck_dft -pin -revised

add pin constraint 0 *dft_connector_inst*tck_dft -revised
add primary input *dft_connector_inst*update_dr_dft -pin -revised

add pin constraint 0 *dft_connector_inst*update_dr_dft -revised
add primary input *dft_connector_inst*shift_dr_dft -pin -revised

add pin constraint 0 *dft_connector_inst*shift_dr_dft -revised
add primary input *dft_connector_inst*rd_udrb_dft -pin -revised

add pin constraint 0 *dft_connector_inst*rd_udrb_dft -revised
add pin constraint 1 ramscanb -revised

add pin constraint 0 bist_jtag_si -revised
add pin constraint 0 bist_jtag_sel -revised
add pin constraint 0 bisttest_jtag_si -revised
add pin constraint 0 bisttest_jtag_sel -revised
add pin constraint 0 ram_iddq_en -revised
If RAMBIST exists in the design, do not compare bisttest_jtag_so and

bist_jtag_so outputs.
These outputs are floating ports in the pre-DFT design. Instead, compare the
corresponding outputs from the dft_connector by promoting these outputs to
primary outputs:
add primary output *dft_connector_inst*bisttest_jtag_so_dft -both
add primary output *dft_connector_inst*bist_jtag_so_dft -both
add ignored outputs bisttest_jtag_so -both
add ignored outputs bist_jtag_so -both
lec -lp -nogui -dofile \

../formalv/tsb_dft/pm1234_pre_post.do -logfile \
../formalv/tsb_dft/pm1234_pre_post.log
Examine ../formalv/tsb_dft/pm1234_pre_post.log for errors
Grep ERROR ../formalv/tsb_dft/pm1234_pre_post.log
Output:
(from pre-DFT vs. post-DFT LEC)
../formalv/tsb_dft/pm1234_pre_post.log, log file
This step runs a logic equivalence check (LEC) between the pre-stitch netlist and the
post-stitch netlist. When examining the LEC log file, pay attention to the line with
Compare Results. This line should end with EQ to signify logic equivalence.
Otherwise, this indicates that the DFT insertion step may have changed the original
functionality of the TSB.
If users forget to add the ignored outputs WPI_feedout* or ignored outputs WPO_or*
lines, then, nonequivalent pins will be shown in the LEC report. This is because, the
WPI_feedout/WPO_or outputs are unconnected in the golden netlist, but they are
connected to logic in revised netlist. Therefore, users have to ignore them in LEC to
avoid the nonequivalence. Currently, there are no commands for RC to insert those lines
automatically when generating the LEC scripts. In the future, a more flexible PMC
featured LEC flow will be implemented to reduce this manual work.
10.4.3 Lockup Latch Verification

Input:
../scan/tsb_dft/pm1234_verify_ll.gt.tcl, GoldTime script to verify insertion of all
lockup latches and head/tail latches.
Command:
cd ()/scripts/
less .synopsys_pt.setup ( this file can still be used for library
set-up, in this DFT specific GoldTime run only. The
::CAD::setup::set_tech_lib command in this file will load the
standard cell library.)
less ../scan/tsb_dft/pm1234_verify_ll.gt.tcl (to see what is being
run)
goldtime -f \
../scan/tsb_dft/pm1234_verify_ll.gt.tcl -logfile \
../scan/tsb_dft/pm1234_verify_ll.log
../scan/tsb_dft/pm1234_verify_ll.gt.tcl
Examine ../scan/tsb_dft/pm1234_verify_ll.log for errors and
equivalence
grep Error ../scan/tsb_dft/pm1234_verify_ll.log
Examine ../scan/tsb_dft/pm1234_verify_ll.rpt for any hold-time
violation of 250000000.00
Output:
(from pre-DFT vs. post-DFT LEC)
../scan/tsb_dft/pm1234_verify_ll.rpt, report file containing spots for missed LLs
../scan/tsb_dft/pm1234_verify_ll.log, log file
Description:
This step runs verification on the completeness of lockup latch insertion. When
examining the LL verification report, search for any violation of 250000000. Any
location with this type of violation is usually an indication of missing LL. Ideally, there
should be none.
10.5 Run ET ATPG
Input:
et_atpg/runet.atpg, ATPG run scripts
Command:
cd ()/scripts/
less et_atpg/runet.atpg (to see what is being run)
If the compression ratio in the DFT info file was defined as 1 when
running the run_tsb_dft.rctcl scripts, please modify the generated
et_atpg/runet.atpg file as follows before dispatching to LSF:
Comment out the following commands:
#prepare_core_migration_faults \
# coremigrationdir=./et_atpg/pm1234_DIR \
# testmode=COMPRESSION_INTEST \
#CheckLogs $? "log_prepare_core_migration_faults_COMPRESSION_INTEST"
#prepare_core_migration_faults \
# testmode=COMPRESSION_DECOMP_INTEST \
#CheckLogs $?
#"log_prepare_core_migration_faults_COMPRESSION_DECOMP_INTEST"
#prepare_core_migration_info \
#CheckLogs $? "log_prepare_core_migration_info_COMPRESSION_INTEST"
#prepare_core_migration_info \
#CheckLogs $?
#"log_prepare_core_migration_info_COMPRESSION_DECOMP_INTEST"
#prepare_core_migration_tests \
#CheckLogs $? "log_prepare_core_migration_tests_COMPRESSION_INTEST"
#prepare_core_migration_tests \
#CheckLogs $?
#"log_prepare_core_migration_tests_COMPRESSION_DECOMP_INTEST"
#commit_tests \
# inexperiment=pm1234_atpg \
# testmode=FULLSCAN
#CheckLogs $? "log_commit_tests_FULLSCAN_pm1234_atpg"
Adding the following commands:
Right after the below section:
write_vectors \
inexperiment=pm1234_atpg \
testmode=FULLSCAN_INTEST \
language=verilog \
scanformat=serial \
CheckLogs $? "log_write_vectors_FULLSCAN_INTEST_pm1234_atpg"
Adding:
commit_tests \
testmode=FULLSCAN_INTEST
CheckLogs $? "log_commit_tests_FULLSCAN_INTEST_pm1234_atpg"
Right after the below section:
write_vectors \
testmode=SERIAL_INTEST \
language=verilog \
scanformat=serial \
CheckLogs $? "log_write_vectors_SERIAL_INTEST_pm1234_atpg"
Adding:
commit_tests \
testmode=SERIAL_INTEST
CheckLogs $? "log_commit_tests_SERIAL_INTEST_pm1234_atpg"
et qa -e ./et_atpg/runet.atpg | \
& tee et_atpg/runet.log
Examine et_atpg/runet.log for errors and equivalence
grep Error et_atpg/runet.log
Output:
et_atpg/tbdata/*, ATPG generated binary files
et_atpg/testresults/*, log files for ET commands and the files for simulation
et_atpg/pm1234_DIR/pm1234/*, ATPG generated files for core migration
et_atpg/runet.log, log file
Description:
This step is optional, only for the users who want to run ATPG on the DFT implemented
post stitched netlist using the RC auto generated ET scripts. In the future, a PMC featured
ATPG script generator will be updated which will be compatible with TSB DFT v006
flow.
11 INTEPRETING DFT LINT MESSAGE
The DFT log file pm1234_tsb_dft_impl.log outputs quite a few Info and Warning
messages for DFT LINT and IEEE 1500 wrapper cell insertion. Info messages usually
indicate something that is friendly to DFT and passes certain DFT rule. Warning usually
indicates DFT-related problems with the design or design setup, and may require certain
changes to resolve the issues. The following explains the warnings that may be
observable in the log file.
11.1 Checking PI Registering Warning Messages
This section checks if every functional primary input is correctly registered on the
boundary of the block. If so, the receiving flop will be stitched as part of the IB chain.
Otherwise, a warning is issued. The type of warning in the run_tsb_dft.log file done on
the TSB is parsed by the pm1234_tsb_dft_impl.rctcl script to generate input wrapper
cells. The following are possible warnings in the pm1234_tsb_dft_impl.log file and
some explanations behind them.
Warning: Cannot wrap pin/port. [DFT-567]

: Port <port_name> is associated to {test_mode/clock/shift_enable} signal
<signal_name>.
This warning is self-explanatory.

: Port <port_name> is floating.
Warning: Cannot honor '-shared' option for pin/port. [DFT-568]

: For input/output port <port_name> its fanout/fanin includes instances other
than buffers/inverters and flip-flops (reg).
This warning message means the PI port is driving some combinational logic other than
buffers, inverters and flip-flops. So, it is not natively registered by flops. Therefore, RC
will insert a dedicated input wrapper cell on this port.

: For input port <port_name> its fanout includes a port <output_port_name>
This warning means the path from this input port to the <output_port_name> is a feed-
through path. Either two dedicated wrapper cells (input and output wrapper cells) or none
of them will be inserted on this path depends on the setting of
insert_dedicated_cells_on_feedthrough_path in the DFT info file.
11.2 Checking PO Registering Warning Messages
This section checks if every functional primary output is correctly registered on the
boundary of the block. If so, the launching flop will be stitched as part of the OB chain.
Otherwise, a warning is issued. The type of warning in the run_tsb_dft.log file done on
the TSB is parsed by the pm1234_tsb_dft_impl.rctcl script to generate output
wrapper cells. The following are possible warnings in pm1234_tsb_dft_impl.log file.

: Port <port_name> is driven by a logic constant (1'b0).

: Port <port_name> is floating.
This warning means the PO port is undriven.

: For output port <port_name> its fanin includes instances other than
buffers/inverters and flip-flops (<instance_name>).
This warning message means the PO port is driven by some combinational logic other
than buffers, inverters and flip-flops. So, it is not natively registered by flops. Therefore,
RC will insert a dedicated output wrapper cell on this port.
12 STATIC TIMING ANALYSIS (STA) MODES
This section lists the STA case analysis and false paths to be set for various modes. Note
that pin names are based on 28nm libraries. Other libraries may need adjustments to
these constraints.
12.1 Scan Shift Mode

This mode exercises the paths which propagates data from the scan inputs (WSI/WPI)
through the scan chains to the scan outputs (WSO/WPO).
Enable scan mode clocking and other scan mode logic

Note: scan_en_c is only needed if RAMs exist.
set_case_analysis 0 [get_ports scanb]
set_case_analysis 0 [get_ports testclk_selb]
set_case_analysis 1 [get_ports scan_en_o]
if {[sizeof_collection [get_ports -quiet scan_en_c]] > 0} {
set_case_analysis 1 [get_ports scan_en_c]
}
Select the SI pin of scan chain elements

set_case_analysis 1 [get_ports WSE]
set_case_analysis 1 [get_ports DFTSE]
Disable the functional path between clock domains

set_case_analysis 0 [get_ports fll_clk]
False path from WIR and bypass flops

There are paths in the TIM that exist when it is not set to a specific mode, but these paths
become false when the MUX structure of the TIM is set to a specific mode. (Refer to
CAD_PREP 124421.)
In general, only paths between the WIR/bypass flops to itself are valid; paths from the
WIR/bypass flops to other parts of the design are false. The additional path from
wir_instance/wir_slice_3/ShiftReg_reg/CK to *wir_bypass_inst_WBY_WSO_reg/D is
false because SelectWIR allows data to propagate from wir_slice_3/ShiftReg_reg/Q to
*wir_bypass_inst_WBY_WSO_reg/D, but SelectWIR also chooses the SI input by
controlling *wir_bypass_inst_WBY_WSO_reg/SE.
set wir_ck_pins [get_pins -hier */CK \
-filter "full_name =~ *wir_inst* || full_name =~ *wir_bypass_inst*"]
set non_wir_regs [filter_collection [all_registers] \
"full_name !~ *wir_inst* && full_name !~ *wir_bypass_inst*"]
set_false_path -from $wir_ck_pins -to $non_wir_si_pins
set_false_path \
-from [get_pins wir_instance/wir_slice_3/ShiftReg_reg/CK] \
-to [get_pins *_wir_bypass_inst_WBY_WSO_reg/D]
The WIR update registers are static; false path to everything.
set_false_path -from \
[get_pins wir_instance/wir_slice_0/UpdateReg_reg/CK]
Constrain the delay to scan inputs and scan outputs

Refer to CAD_PREP 116464. The delay values are project specific.
# Scan feedthrough max delay
set_max_delay <delay> -from [get_ports WPI[*]] \
-to [get_ports WPI_feedout[*]]
set_max_delay <delay> -from [get_ports WPO_feedin[*]] \
-to [get_ports WPO[*]]
set_max_delay <delay> -from [get_ports WPO_or_feedin[*]] \
-to [get_ports WPO_or[*]]
# Scan input-to-register max delay

# - When EXTEST is defined, the paths from WSI to mintreg0*/SI and
# to mextreg0*/SI are false. When running without modes, the paths
# are seen.
set_max_delay <delay> -from [get_ports WSI] -to [all_registers]
set_max_delay <delay> -from [get_ports WPI[*]] -to [all_registers]
set_false_path from [get_ports WSI] \
-to [get_pins COMPACTOR/compressor/mintreg0_reg_0_inst/SI]
-to [get_pins COMPACTOR/compressor/mextreg0_reg_0_inst/SI]
# Scan register-to-output max delay

set_max_delay <delay> -from [all_registers] -to [get_ports WSO]
set_max_delay <delay> -from [all_registers] -to [get_ports WPO[*]]
set_max_delay <delay> -from [all_registers] -to [get_ports WPO_or[*]]
12.2 Scan Capture Mode

This mode exercises the paths which captures the scan results onto the scan chain.
Enable scan mode clocking and other scan mode logic

}
Select the D pin of scan chain elements
Define the clock for functional lockup latches

The clock has rising edge at 50% of the clock period and falling edge at 75% of clock
period. This matches the clock pattern defined in ATPG. Refer to CAD_PREP 68307.
create_clock -name FLL_CLK -period <period> \
-waveform [list [expr <period> * 0.50] [expr <period> * 0.75] ] \
[get_ports fll_clk]
Define test clocks and clock relationships

Define the test clock (tck/WRCK) and independently controllable functional clocks.
create_clock -name TCK -period <period> ... [get_ports tck WRCK]
create_clock name <independently_controllable_functional_clock_1> \
-period <period1> ... [get_ports <func_clock_1>]
create_clock name <independently_controllable_functional_clock_2> \
-period <period2> ... [get_ports <func_clock_2>]
...
Define clock groups to prevent timing across clock domains.

set_clock_groups -logically_exclusive -group [get_clocks TCK]
set_clock_groups logically_exclusive -group [get_clocks FLL_CLK]
set_clock_groups logically_exclusive \
-group [get_clocks <independently_controllable_functional_clock_1>] \
-group [get_clocks <independently_controllable_functional_clock_2>] \
-group ...
False path from WIR and bypass flops

The WIR update registers are static; false path to everything.
Constrain the delay to scan inputs and scan outputs

Same as for Scan Shift mode.
# Scan feedthrough max delay
set_max_delay <delay> -from [get_ports WPI[*]] \
-to [get_ports WPI_feedout[*]]
set_max_delay <delay> -from [get_ports WPO_feedin[*]] \
-to [get_ports WPO[*]]
set_max_delay <delay> -from [get_ports WPO_or_feedin[*]] \
-to [get_ports WPO_or[*]]
# Scan input-to-register max delay
# - When EXTEST is defined, the paths from WSI to mintreg0*/SI and
# to mextreg0*/SI are false. When running without modes, the paths
# are seen.
set_max_delay <delay> -from [get_ports WSI] -to [all_registers]
set_max_delay <delay> -from [get_ports WPI[*]] -to [all_registers]
-to [get_pins COMPACTOR/compressor/mintreg0_reg_0_inst/SI]
-to [get_pins COMPACTOR/compressor/mextreg0_reg_0_inst/SI]
# Scan register-to-output max delay

set_max_delay <delay> -from [all_registers] -to [get_ports WSO]
set_max_delay <delay> -from [all_registers] -to [get_ports WPO[*]]
set_max_delay <delay> -from [all_registers] -to [get_ports WPO_or[*]]
12.3 Functional Mode

These constraints set the TSB in non-scan mode.
Disable scan mode clocking and other scan mode logic

}
Select the D pin of the scan chain elements

Enable the functional path between clock domains

Configure the DFT logic into WS_BYPASS mode (as per IEEE 1500)
# INTEST
set_case_analysis 0 [get_pins wir_instance/wir_slice_0/UpdateReg_reg/Q]
# EXTEST
# SERIAL
# BYPASS
12.4 JTAG Mode
This mode exercises the paths for shifting data into the WIR. It may be possible to merge
this mode with one of the other modes. It may also be possible to integrate these checks
with top level STA.
The main motivation for a separate mode is to use a different (usually slower) clock
frequency for WRCK for shifting data into the WIR than in the other modes for shifting
data into scan chains.
Disable scan mode clocking and other scan mode logic

}
Select the D pin of the scan chain elements

Enable the functional path between clock domains

Define test clock

create_clock -name TCK -period <period> ... [get_ports tck WRCK]
Enable paths related to loading the WIR

Other constraints may also be necessary to load the RAMBIST UDR.
set_case_analysis 1 [get_ports SelectWIR]
Constrain the delay to WSI and WSO

The delay values are project specific.
set_max_delay <delay> -from [get_ports WSI]
set_max_delay <delay> -to [get_ports WSO]
13 REVISION HISTORY
Issue DATE NAME DESCRIPTION

1.0 December 2014 Xiaoye Xia Created
Added the support for prestitched sub-blocks,
adjusted the flow order, and added the
2.0 January 19 2015 Xiaoye Xia
add_scan_chain_head_flop variable to the
DFT info file.
2.1 April 14, 2016 Anthony Pun Update LEC constraints.
2.2 May 16, 2016 Anthony Pun Add STA constraints
End Of Document
Please send any comments or suggestions concerning this document to the CAD PREP
system.

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TSB_DFT_006 Application Note

Issue 2.2 May 2016

The following are the references for this flow:

WSO MASK_LD so_drvb WPO_feedin WPO

5.1 New Features are Supported in this Release

Reduced impact of DFT on RTL development

Synergies with Cadence compression and Cadence ATPG algorithms

Faster run times for DFT logic insertion

Test insertion will be consolidated into one RC job

Moving to IEEE 1500 standard structures

Support for Pre-stitched sub blocks

5.2 Features Currently Not Supported in this Release

foreach dont $dont_use_list {

if {[info exists ::scan_flops_list]} {

foreach dont $dont_use_list {

7.1 Scan Chain Construction

7.2 TSB Description (pmxxxx)

DFT reserved port names:

1 defaults.tcl Setup DFT using tsb_dft_setup.tcl

2 Fill out TSB info file pm1234_dft_info.tcl

IEEE 1500 wrapper cell insertion

Hier test compression macro insertion pm1234_gates.v

pm1234_verify pm1234_verify_ll.gt.tcl pm1234_verify_ll.rpt

8.1 Stage 1: DFT Setup

8.2 Stage 2: Fill Out TSB Info File

8.3 Stage 3: DFT Implementation

8.4 Stage 4: Pre-DFT vs. Post-DFT LEC

8.6 Stage 6: Run ET ATPG

set scalar_data [ list \

9.3 Scalar Variable and Lists

9.5 Nesting of Lists

array set scan_clocks [ list \

Each sub-section below represents a step in the DFT flow.

10.2 Setup DFT

10.3.1 Design and DFT Set Up Section

set top_module pm1234

# option 1: individual files

array set scan_resets [ list \

array set scan_clocks [ list \

array set user_pin_constraints [ list \

10.3.2 IEEE 1500 Wrapper Cell Insertion Section

set ignore_reg_func_pi [list ]

The ignore_reg_func_pi and ignore_reg_func_po variables contain lists of

set add_dedicated_regs_on_pi [list ]

The add_dedicated_regs_on_pi and add_dedicated_regs_on_po variables contain

The input_shared_threshold and output_shared_threshold variables specify the

set insert_dedicated_cells_on_feedthrough_path yes

The variable insert_dedicated_cells_on_feedthrough_path controls whether to

set ib_chain_add_regs [ list ]

The ib_chain_add_regs and ob_chain_add_regs variables contain lists of flops to be

10.3.3 Compression Insertion and Scan-stitch Section

The value of wpi_bus_width is determined by the top-level scan-pin sharing analysis.

set decompressor xor

set compressor xor

set mask wide1

set allow_mix_clock_edge_in_scan_chain yes

set add_scan_chain_tail_latch yes

The variable add_scan_chain_tail_latch controls whether to force a tail lockup latch

set add_scan_chain_head_flop yes

The variable add_scan_chain_head_flop controls whether to insert a D flip flop (head

set ignore_flops_for_scan [list ]

The dont_touch_blocks array contains definitions of hard-macros. Please refer to the

10.3.4 Functional Lockup Latch Insertion Section

add primary input dft_connector_insttck_dft -pin -revised

add primary input dft_connector_instupdate_dr_dft -pin -revised

add primary input dft_connector_instshift_dr_dft -pin -revised

add primary input dft_connector_instrd_udrb_dft -pin -revised