3rd ISSE National Conference on Complex Engineering Systems of National
Importance:Current Trends & Future Perspective (INAC-03), October 12-13, 2017
AM-0007 Fabrication of Nanotransistors
Gangadhar Purohit1,2#+, Monica Katiyar1,2, Deepak 1,2
1
Department of Materials Science and Engineering, Indian Institute of Technology Kanpur, India,
2
National Centre for Flexible Electronics, Indian Institute of Technology Kanpur, India
#
Corresponding author: ganga@iitk.ac.in +Presenter
AbstractIn this paper, using a cost-effective and
simple technique for the formation of nano-
separation of metal electrodes over a large
substrate/wafer using conventional optical
lithography and thermal stresses,a thin film transistor
with indium-gallium-zinc oxide (IGZO)
semiconductor is fabricated. Gate electrode is made
by inkjet printing of polyvinylphenol dielectric and
PEDOT:PSS. The threshold voltage is 6.4 V and
estimated linear mobility is 0.1 cm2/Vs. Combination
of the techniques for forming of nano-separation of
metal electrodes and printing is a viable low cost
hybrid process for making TFT arrays.
I. INTRODUCTION
High throughput and low cost processing is of
paramount importance for nanomanufacturing
when miniaturization of electronics devices is
required [1]. But, the scaling down the device
components results in increase of complexity of
nanolithography equipment as well as their process
steps. Hence, the development of low cost and
unconventional routes for nanolithography is
essential. Although the present-day
nanolithography instruments are used for producing
large area nanostructure geometries, still they have
daunting tasks such as long fabrication time and
expensive process cost. Hence unconventional
way/approach of top-down nanofabrication (or
bottom-up approach by chemical self-assembly)
will be a replacement of many expensive,
conventional lithography techniques used in
miniaturization of semiconductor technology. We
have demonstrated here a technique for
nanofabrication by applying thermal stress on
multilayered thin films patterned over a large
substrate/wafer [2]. The strength of this invention
is that scalable fabrication of large number of
nanogaps in electrodes in a single thermal
annealing step. This thermal stress based nanogap
fabrication involves very minimum number steps to
get final geometry, which is unlikely in existing
nanolithography techniques, such as e-beam
lithography [3], focused ion beam (FIB)
lithography [4] and scanning probe lithography [5].
Here Au/Ti thin films were taken as a test structure
because of its use as electrode contacts in may
electronics devices. Furthermore, we have
visualized the nanochannel thin film transistors
(TFTs) by using the thermal stress defined
nanogaps in electrodes as the source and drain
electrodes of the devices. The IGZO based TFT
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Advanced Materials
was realized in bottom contact top gate
architecture, with IGZO as sputtered active channel
layer, and PVPh dielectric and PEDOT:PSS as
inkjet printed layers (Figure 1).
PEDOT:PSS
PVPh dielectric
IGZO channel material
S/D electrodes
Glass
Fig.1.Schematic side-view of TFT device architecture
fabricated on nanogap containing Au electrodes.
II. EXPERIMENTAL DETAILS
(a) Patterned substrate: Thick transparent glass,
basically used in electronics industry for device
fabrications, was taken as substrate material. First
they were cleaned by soap solution, then rinsed
with de-ionized (DI) water, followed by RCA
protocol for removing organic and metal
contaminations. After cleaning, the multilayer thin
films of Ti (10 nm)/ Au (50 nm)/SiOx (300 nm)
were deposited using e-beam evaporator, without
breaking vacuum in between these deposition steps.
Here the SiOx layer was deposited at 200oC. In
addition, an ultrathin layer of Ti was made to
promote adhesion of Au film on glass surface.
Next, the sequential patterning of multilayer thin
films from SiOx, Au and then Ti were made using
conventional optical lithography, as show in Figure
2a. The so-formed substrate was taken for heat
treatment ranging from 300-500oC.
(a (b
) )
Fig. 2. (a) The optical imaging of a notched electrode
bridge consisting of stacking layer of SiO x/Au/Ti on
glass by using optical lithography, (b) Crack assisted
nano-separation notched electrode bridge after thermal
annealing at 350oC for 1 hr.
The crack was formed on SiOx layer due to thermal
stress mismatch between SiOx and metal (Au) thin
films, and also because of brittle nature of SiOx thin
film. In order to localize the crack, a notch was
3rd ISSE National Conference on Complex Engineering Systems of National
Importance:Current Trends & Future Perspective (INAC-03), October 12-13, 2017
included at the mid length of electrode bridge.
When a crack opening generated on SiOx layer, the
Au and Ti films just underneath to SiOx layer were
etched out using their respective chemical etchants.
Finally, the entire SiOx layer was stripped out from
the substrate, leaving the nano-separation Au
nanogap electrodes. Using this technique,
nanogaps in electrodes with around ~ 200-300 nm
length scale were generated (Figure 2b). by using
industrial semiconductor processing, this thermal
stress technique can be a viable process for
commercial nanomanufacturing. The I-V electrical
characterization of the nanogap separated electrode
bridges was taken to check whether the electrodes
were electrically isolated or not. After that, these
nanogaps in electrodes were used as source and
drain electrodes in thin film transistors, its
fabrication process is described in the following
sections (Figure 1).
(b) Fabrication of other device components: The
RF sputtering evaporator was employed for
depositing IGZO semiconductor of 20 nm
thickness, also confirmed by stylus profilometer.
The transparent nature of IGZO thin film was an
advantage while printing of gate dielectric and gate
electrode above it. It was also useful during
electrical probing.
The drop-on-demand inkjet printer [Fujifilm
Dimatix Materials Printer DMP-2831] was used for
depositing polymer dielectrics (PVPh) and gate
electrodes (PEDOT:PSS) at desired location.
Precise dropping of inks was possible using inkjet
printing technology. Inkjet printer does not require
masks for production of different layers.
Furthermore, it is a non-contact technique with
advantage of reduced contamination and risk of
substrate damage.Other than printing techniques,
no easy process was found to make multilayers of
films with exact alignments. Advanced lithography
techniques will require multiple steps to get same
final configuration, for example mask alignment,
multi-steppatterning. Hence, inkjet printer helps to
make drop-on-demand fabrication of layers within
short time.
(c) Ink Formulations:Polymer dielectric
PVPh inks were formulated by mixing additives of
propylene glycol methyl ether acetate (PGMEA)
and cross-linking agent (CLA ). The ink for drop-
on-demand printing is formulated as 96.25 wt %
PGMEA + 2.5 wt% PVPh + 1.25 wt% CLA. After
inkjet printing, the dielectric ink droplets were
dried for 1 hour at 180oC. The thickness of PVPh
dielectric was measured using stylus profilometer,
which was around 10-15 nm of thickness.
The droplets of PVPh were precisely jetted on the
desired location of the S/D electrodes, as shown in
the Figure 4.In order to reduce resistances created
due to overlap of various layers, drop-on-demand
printing was followed to deposit polymer dielectric
and gate contact electrode with best possible way.
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Advanced Materials
As we know, apart from the inherent resistance on
active semiconductor layer, the other resistances
created due to overlap of S/D electrodes with
semiconductor layer, between junction/interface of
semiconductor molecule with Au atoms, and also
due to thin film nature of gate oxide causes current
leakage to gate electrode.
(d) Ink Formulations:Conducting gate electrode
PEDOT:PSS was purchased from Heraeus
(CleviosTM P Jet HC) and mixed with additives of
dimethyl sulfoxide (DMSO), Titron X and de-
ionized (DI) water to make inks for printing. Here
the ink solution was prepared using solvent of
PEDOT:PSS and DI-water as a ratio of (1:1) , then
mixing with 5 wt% of DMSO and 1 wt% of
Triton as a binding agent.After drying printed layer
of PVPh dielectric, the PEDOT:PSS electrode
contact was deposited by using inkjet printing.
Then the films were dried for 30minutes at 120 oC.
Here the film thickness was observed around 25-35
nm, which confirmed using stylus profilometer.
Here the ink-jet printed PEDOT:PSS acts as the top
gate electrode of TFTs.
III. RESULTS AND DISCUSSION
The concept behind the proposed method/technique
for forming nano-separation in electrodes involves
the differential thermal expansion co-efficient
between the ceramic film (SiOx) and Au metal film
beneath it. Tensile stress are induced in SiOx film
during heating from a specific temperature. As the
thermal expansion co-efficient of SiOx film
(deposited by e-beam evaporator) is lower than Au
thin film, then upon heating crack propagation only
takes place on SiOx layer. Here a notch shaped
electrode bridge was patterned and it led to stress
concentration at the notch tip during heating of the
substrate, so the crack at first was initiated at the
notch tip of electrode bridge of SiOx layer. The
crack propagated across the electrode bridge only
in SiOx film. Then a metal etching step was made
to remove Au and Ti film at the location of crack,,
while the ceramic oxide acts as protecting layer (or
hard mask) to other area of metal films. At the end,
stripping out of SiOx layer causes nanogap at the
notched electrode bridge having the dimension in
nanometer range. The nanogaps in electrodes were
measured of dimensions ranging between 150-300
nm by taking number of substrates. The crack
defined nanogaps in electrodes is independent of
substrate used. Here the glass substrate was
replaced by, silicon substrate with thermally grown
SiO2 (Figure 3).
(a) (b)
Fig. 3. (a) FE-SEM image of nanogap separated Au
electrodes on SiO2/Si-substrate, (b) Its enlarged nanogap
~300nm was achieved in one of electrode bridges.
3rd ISSE National Conference on Complex Engineering Systems of National
Importance:Current Trends & Future Perspective (INAC-03), October 12-13, 2017 Advanced Materials

Due to thermal annealing, the cracks were only made at

VD = 10 V
the notched electrode bridge of patterned multilayer thin -8
1.0x10
films. The advantage of the process is that no observation
of any crack formation on as-purchased SiO2/Si -9
8.0x10

Drain current (A)

substrate.
-9
To localize the crack defined nanogap at the 6.0x10
electrode bridge, we have used rf-sputtering and
-9
ink-jet printer for depositing other TFT 4.0x10
components. All ink-jet printing layers of TFTs can
be made on the thermal stress defined nanogap -9
2.0x10
electrodes, but we have made only two top layers,
such as polymer dielectric and gate contact by ink- 0.0
jet printing process. In Figure 4, a droplet of PVPh -10 -5 0 5 10
was ink-jet printed over IGZO film deposited on Gate voltage (V)
nanogap separated Au/Ti source and drain contacts.
Fig. 5.(a) Output characteristics of an IGZO based TFT
having channel length of 700 nm. (b) Transfer
characteristics of the TFT at 10 V. Channel width is 4
m, capacitance of PVPh is 20 x 10-9 F/cm2.

V. CONCLUSIONS
In our lab, we obtained nanogap features with
thermal annealing, without steppers, on entire
substrate simultaneously. The so-obtained nanogap
in electrodes is around ~ 200 nm, which is difficult
to achieve only using traditional photolithography.
Hence, it is a cost-efficient and simplistic technique
for formation of nano-separation in between metal
electrodes. Its eminent use is in semiconductor
Fig.4. Droplet of PVPh on nanogap containing Au device manufacturing. Control of notch, with
electrode. sharper features (industrial processing conditions)
can further reduce the gap dimension much below
IV. DEVICE CHARACTERIZATION optical lithography limits.
The current vs voltage measurement of the device IGZO based TFT was also realized in bottom
was measured using Kiethley 2640 source-meter contact top gate device architecture on nanogap of
unit. Figure 5(a) and (b) show output and transfer Au electrodes, with IGZO as the sputtered active
characteristics of the device. The threshold voltage channel layer, and PVPh dielectric and PEDOT:
is 6.4 V and estimated linear mobility is 0.1 PSS as printer layers. Further optimization of
cm2/V.s. processes is required to improve performance.
-8 VG=0.0 V
8.0x10
VG=2.5 V REFERENCES
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-8
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VG=10 V vol. 10, pp. 2995-3014, 2016/03/22 2016.

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