A REPORT

ON

Three stage amplifier

BY

Omkar Lad 2011A3PS214P

Anand Karwa 2011A8PS334P
Vatsal Malavia 2011A8PS350P
AT

BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, PILANI

(November, 2013)

1
 Summary Of Results

For TT:

Sl. Quantity Value Required Specifications

No.
1 DC Gain 100.7 dB 100 dB
2 Phase Margin 58.3o
Output Swing 1.95V
4 Output DC Offset 0.12V
5 Input DC Offset 960nV
6 Slew Rate 16.6 V/s <20V/s
7 Settling Time 35 ns <20ns
8 Unity Gain Bandwidth 230Mhz >200Mhz
9 CMRR 112dB
10 PSRR 108 dB
11 ICMR 1.4V-2.3V
12 Power Dissipation 1.39 mW 3 mW
13 Closed loop gain 97.5 dB
14 Closed loop phase margin 45.5 o

For FF:

Sl. Quantity Value Required Specifications

No.
1 DC Gain 91 dB 100 dB
2 Phase Margin 66.9o
Output Swing 2.13V
4 Output DC Offset 0.08V
5 Input DC Offset 2.35V
6 Slew Rate 18.5 V/s <20V/s
7 Settling Time 40 ns <20ns
8 Unity Gain Bandwidth 186Mhz >200Mhz
9 CMRR 97 dB
10 PSRR 95 dB
11 ICMR 1.35V-2.3V

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12 Power Dissipation 1.213 mW 3 mW
13 Closed loop gain 83 dB
14 Closed loop phase margin 58 o

For SS:

Sl. Quantity Value Required Specifications

No.
1 DC Gain 74 dB 100 dB
2 Phase Margin 83o
Output Swing 1.87V
4 Output DC Offset 0.05V
5 Input DC Offset 14.2V
6 Slew Rate 20 V/s <20V/s
7 Settling Time 33 ns <20ns
8 Unity Gain Bandwidth 33 Mhz >200Mhz
9 CMRR 90 dB
10 PSRR 85 dB
11 ICMR 1.65V-2.3V
12 Power Dissipation 1 mW 3 mW
13 Closed loop gain 91 dB
14 Closed loop phase margin 68 o

3
INTRODUCTION

Ques 41. Design a CMOS OPAMP.

a) Analog schematic for the above model
b) Analysis of all equations of your design, with a systematic derivative of all transistors
W/L ratios and spectre simulation of circuit for the following specifications.

i) Gain 100 dB
ii) Settling time 20ns
iii) UGB 200 MHz
iv) Slew rate 20 V/s
c) Measure the closed loop gain and phase margin for your OPAMP using STB analysis?
d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC
gain and phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, output voltage
swing (dc + Transient), power consumption, and input and output offset voltage.
e) Check whether your OPAMP can function as a unity-gain buffer.

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Design and operation of current reference
Unbuffered, Two-Stage CMOS Op Amp

For best performance, keep all transistors in saturation. M4 is the only transistor that cannot
be forced into saturation by internal connections or external voltages. Therefore, we
develop conditions to force M4 to be in saturation. 1.) First assume that VSG4 = VSG6. This
will cause proper mirroring in the M3-M4 mirror. Also, the gate and drain of M4 are at

5
the same potential so that M4 is guaranteed to be in saturation.

Unbuffered Op Amp Design Procedure

This design procedure assumes that the gain at dc (Av), unity gain bandwidth (GB), input
common mode range (Vin(min) and Vin(max)), load capacitance (CL), slew rate (SR),
settling time (Ts), output voltage swing (Vout(max) and Vout(min)), and power dissipation
(Pdiss) are given. Choose the smallest device length which will keep the channel
modulation parameter constant and give good matching for current mirrors.
1. From the desired phase margin, choose the minimum value for Cc, i.e. for a 60 phase
margin we use the following relationship. This assumes that z 10GB.
Cc > 0.22CL
2. Determine the minimum value for the tail current (I5) from the largest of the two
values. VDD + |VSS|

I5 = SR .Cc or I5 10 2 .Ts
3. Design for S3 from the maximum input voltage specification.
I5

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 =
3 K'3[VDD Vin(max) |VT03|(max) + VT1(min)]2
4. Verify that the pole of M3 due to Cgs3 and Cgs4 (= 0.67W3L3Cox) will not be dominant
by assuming it to be greater than 10 GB
gm3
Cgs3 > 10GB.

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8
 Plots (The analysis is done in next section)

For tt

CMRR CMRR

icicc

9
ICMR

10
Output voltage swing

11
PSRR

12
STB

For ff

13
CMRR

14
ICMR

15
Output Voltage Swing

16
PSRR

17
Slew Rate and Settling time

18
STB

vdee

19
For SS

Bode plot and phase margin

20
ICMR

21
Slew rate and settling time

22
STB

23
Output voltage swing

2.2 RESULTS

The first two stages of op amp have been designed to give a total gain of around 102 dB,
UGB>300 MHz, while the buffer is implemented using a CD configuration of MOS. The buffer
is designed to give a high output impedance and minimal drop in the gain (ideally unity gain ,and
infinite output resistance). The slew rate parameter is dominant in the differential stage. The
settling time is specified to be less than 20 ns while slew rate is required to be less than 20 V/uS.
These parameters cannot be simultaneously satisfied since if the slope of step input response is
small, the settling time will be higher. So both cannot be satisfied at the same time. The current

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source used is of 6.5 uA which is low enough to give high gain , and high enough to maintain the
required phase margin and UGB. The designed circuit was observed to be performing
satisfactorily below 50 degrees Celsius. The compensating resistance and capacitance are tuned
to give a zero as far as possible from the UGB as possible, to give a good phase margin. This will
result in the op amp performing well even in high frequency input signals.

CONCLUSION

We therefore conclude that the design we have implemented has met most of the required
specifications while giving minimal power consumption. The circuit has been successfully
verified at the process corners FF, +10%Vdd, 0oC, and SS,-10%Vdd, 100oC. The design also gives
high PSRR, CMRR, ICMR and slew rate with a short settling time.

3 REFERENCES

1. http://webpages.eng.wayne.edu/cadence/ECE7570/doc/wsota_w03.pdf

2.Design of Analog CMOS Integrated Circuits: Behzad Razavi

3.NordianaMukahar, ShamianZainal, Design and Analysis of Operational Amplifier using VLSI

software, International Journal of Undergraduate Studies, 2012

4.Wan Irfaan Wan Fuad and Abdul Halim Ali, Analysis of CMOS Differential Input toIncrease
ICMR of Folded Cascode OperationalAmplifier, 2010 IEEE Symposium on Industrial
Electronics and Applications (ISIEA 2010), 2010

5.Satoshi Sakurai, Seyed R. Zarabadi, Mohammed Ismad, CMOS

OperationalAmplifier with Slew Rate Enhancement Circuit, The Ohio State University

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