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Synopsys

Interconnect Technology Format


Specification
Version 2015.06
Copyright and Proprietary Information Notice
Copyright 2015 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary
information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and
may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may
be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without
prior written permission of Synopsys, Inc., or as expressly provided by the license agreement.
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America.
Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader's responsibility to
determine the applicable regulations and to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH
REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Trademarks
Synopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at
http://www.synopsys.com/Company/Pages/Trademarks.aspx.
All other product or company names may be trademarks of their respective owners.

Synopsys, Inc.
700 E. Middlefield Road
Mountain View, CA 94043
www.synopsys.com

Interconnect Technology Format Specification, version 2015.06 ii


Contents

1. Backus-Naur Form of the Standardized ITF


BNF Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
BNF Notation Description of the ITF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Conventional ITF Keywords. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Electromigration ITF Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

2. Conventional ITF Syntax Specification


AIR_GAP_VS_SPACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
ASSOCIATED_CONDUCTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
BACKGROUND_ER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
BOTTOM_DIELECTRIC_ER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
BOTTOM_DIELECTRIC_THICKNESS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
BOTTOM_THICKNESS_VS_SI_WIDTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
BW_T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
CAPACITIVE_ONLY_ETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
CONDUCTOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
CRT_VS_AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
CRT_VS_SI_WIDTH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
CRT1, CRT2, and T0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

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Interconnect Technology
Technology Format
Format Specification
Specification 2015.06
Version 2015.06

DAMAGE_ER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
DAMAGE_THICKNESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
DENSITY_BOX_WEIGHTING_FACTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
DEVICE_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
DIELECTRIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
DIELECTRIC_FILL_VS_SI_SPACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
DROP_FACTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
DROP_FACTOR_LATERAL_SPACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
ER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
ER_VS_SI_SPACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
ETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
ETCH_VS_CONTACT_AND_GATE_SPACINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
ETCH_VS_WIDTH_AND_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43
ETCH_VS_WIDTH_AND_SPACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45
FILL_RATIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52
FILL_SPACING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
FILL_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54
FILL_WIDTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55
FLOATING_GATE_TO_DIFFUSION_CONTACT_CAP . . . . . . . . . . . . . . . . . . . . . . 2-56
FROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58
GATE_TO_CONTACT_SMIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59
GATE_TO_DIFFUSION_CAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60
GLOBAL_TEMPERATURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62
HALF_NODE_SCALE_FACTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63
ILD_VS_WIDTH_AND_SPACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64
IS_CONFORMAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66
IS_PLANAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67
LAYER_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-68

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Interconnect Technology Format Specification Version 2015.06

MEASURED_FROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70
MULTIGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-72
POLYNOMIAL_BASED_THICKNESS_VARIATION . . . . . . . . . . . . . . . . . . . . . . . . . 2-77
RAISED_DIFFUSION_ETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84
RAISED_DIFFUSION_GATE_SIDE_CONFORMAL_ER . . . . . . . . . . . . . . . . . . . . 2-87
RAISED_DIFFUSION_THICKNESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89
RAISED_DIFFUSION_TO_GATE_SMIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-91
REFERENCE_DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92
RESISTIVE_ONLY_ETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-93
RHO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-94
RHO_VS_SI_WIDTH_AND_THICKNESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-95
RHO_VS_WIDTH_AND_SPACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-97
RPSQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-98
RPSQ_VS_SI_WIDTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-99
RPSQ_VS_WIDTH_AND_SPACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-100
RPV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-102
RPV_VS_AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-103
RPV_VS_COVERAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-104
RPV_VS_SI_WIDTH_AND_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-108
RPV_VS_WIDTH_AND_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-111
SIDE_TANGENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-113
SMIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-115
SPACER_ER_VS_WIDTH_AND_SPACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-116
SW_T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-118
TECHNOLOGY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-119
THICKNESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-120
THICKNESS_VS_DENSITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-121
THICKNESS_VS_WIDTH_AND_SPACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-123

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Interconnect
Interconnect Technology
Technology Format
Format Specification
Specification 2015.06
Version 2015.06

TO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-125
TSV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-126
TVF_ADJUSTMENT_TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-129
TW_T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-131
USE_SI_DENSITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-132
VARIATION_PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-133
VIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-134
WMIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-137

3. Electromigration ITF Syntax Specification


Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Including Electromigration Information in the ITF File . . . . . . . . . . . . . . . . . . . . . . . 3-3
Example of EM and Process Information in One ITF File . . . . . . . . . . . . . . . . . 3-4
Example of EM and Process Information in Separate ITF Files . . . . . . . . . . . . 3-5
ITF-EM Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
ITF-EM Keywords and Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
AVERAGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
COMMON_INFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
CONDITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
CONTACT_AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
CURRENT_DEFAULT_AVERAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
CURRENT_DEFAULT_PEAK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
CURRENT_DEFAULT_RMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
CURRENT_DENSITY_DEFAULT_AVERAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
CURRENT_DENSITY_DEFAULT_PEAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
CURRENT_DENSITY_DEFAULT_RMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
CURRENT_DENSITY_VALUES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
CURRENT_DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
CURRENT_FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

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CURRENT_VALUES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
DELTA_TEMPERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
EM_INFORMATION, END_OF_EM_INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . 3-26
EXPRESSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
FF, FQ, FS, FP, QF, QQ, QS, QP, SF, SQ, SS, SP, PF, PQ, PS, PP . . . . . . . . . . . . 3-29
INCLUDE_EM_INFORMATION_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
ITF_EM_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
LAYER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
LAYER_CURRENT_DENSITY_TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
LAYER_CURRENT_TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37
METAL_LENGTH_VALUES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
METAL_WIDTH_CUTOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
METAL_WIDTH_RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
METAL_WIDTH_VALUES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
PEAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
RATING_TEMPERATURE, RATING_FACTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
REFERENCE_TEMPERATURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45
RMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46
RMS_SPACING_FACTOR_TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
SINGLE, ARRAY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48
STACKED_VIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49
TEMPERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
TTF_TEMPERATURE, TTF_FACTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51
VIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52
VIA_ARRAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54
VIA_ARRAY_MULTIPLIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55
VIA_COVER_LANDING_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-56

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Contents vii
1-vii
Interconnect
Interconnect Technology
Technology Format
Format Specification
Specification 2015.06
Version 2015.06

VIA_CURRENT_TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57
VIA_SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58
VIA_SIZE_LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59
VIA_TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60
WIDTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61

Appendix A. ITF Examples


Fully Planar Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
Conformal Dielectric Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
Gate Poly Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4
Local Interconnect Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
Dielectric Air Gaps Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
Layer Etch Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7
Metal Fill Process (Emulated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8
Transistor-Level Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9
Through-Silicon Via Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10
Trench Contact Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12

Contents viii
1
Backus-Naur Form of the Standardized ITF 1
This chapter describes the Backus-Naur form (BNF) of the standardized Interconnect
Technology Format (ITF) in the following sections:
BNF Syntax Conventions
BNF Notation Description of the ITF File

1-1
Interconnect
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Technology Format
Format Specification
Specification 2015.06
Version 2015.06

BNF Syntax Conventions


The BNF description defines ITF syntax and indicates how the ITF keywords work together.
For information about the meaning and usage of keywords and their arguments, see the
keyword reference pages.
Table 1-1 lists the BNF syntax conventions that are used in the ITF.
Table 1-1 Syntax Conventions for the ITF

Convention Description

<> Denotes an object in the BNF notation that can be expanded (i.e. replaced with
equivalent, more detailed objects). Not part of the syntax.

[ ] Denotes an optional item; not part of the syntax.

| An operator that separates mutually exclusive alternatives; not part of the


syntax.

{ } A grouping operator; part of the syntax. Use exactly as shown.

( ) A grouping operator; part of the syntax. Use exactly as shown.

<ABC> ::= Indicates that the object named within angle brackets (< >) can be replaced by
(expanded into) the object or objects on the right side of the expression.

XYZ = Indicates that the object on the left side of the expression is an ITF keyword
and that it can be set equal to the value on the right side of the expression.

<string> Represents a technology name, layer name, table name or parameter name,
depending on the syntax. Upper and lower case letters are considered to be
different. No white space is permitted in a string. Tabs, spaces, and new line
characters are considered to be white space. There are no quotes for a string.
Examples: Metal1, fpoly, SUBSTRATE

<value> Represents a real number, which can be positive or negative.


Examples: -0.5, 220, 3e-6

<n> Represents a positive integer.

<vector(n)> Indicates a vector of real numbers of size n.


Examples: <vector(2)> is a vector of real numbers with two elements.
<vector(m)> is a vector of real numbers with m elements.

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Table 1-1 Syntax Conventions for the ITF (continued)

Convention Description

<matrix(m,n)> Indicates a matrix of real numbers with m rows and n columns.


For example,
<matrix(3,2)> is a matrix of real numbers with 3 rows and 2 columns.
<matrix(s,t)> is a matrix of real numbers with s rows and t columns.

<expr> Indicates a functional expression.


For example: 4 * 1.104 * ( w - 0.010 )
A constant value can also be a functional expression.

... Indicates that you can repeat the previous arguments multiple times.

... n Indicates that the previous arguments are repeated n times.


For example,
<string> ... 3 specifies that the string is repeated 3 times.

Recursion
BNF notation uses recursion to indicate that elements can be repeated. For example,
consider the following description:
<STACK_LAYERS> ::=
<DIELECTRIC_LAYER>
| <CONDUCTING_LAYER>
| <DIELECTRIC_LAYER> <STACK_LAYERS>
| <CONDUCTING_LAYER> <STACK_LAYERS>

This means that a legal collection of stack layers can consist of any of the following
combinations:
One dielectric layer
One conducting layer
One dielectric layer followed by any legal collection of stack layers
One conducting layer followed by any legal collection of stack layers

This might result in combinations such as one dielectric layer plus one dielectric layer, one
dielectric layer plus one conducting layer, one dielectric layer plus one conducting layer plus
another conducting layer, and so on. In fact, the notation above means that any number and
any order of dielectric and conducting layers is a legal combination of layers in the stack.
The only requirement is that there be at least one dielectric or conducting layer.

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Operators and Grouping


Curly braces, parentheses, and equal signs are part of the ITF syntax. Angle brackets and
square brackets are not part of the syntax. Commas and spaces can be used
interchangeably as delimeters between values in a list or matrix.
For example, consider the following statements;
<ER_VS_SI_SPACING_TABLE> ::=
ER_VS_SI_SPACING {
<ervsss_value_pair> [<ervsss_value_pair>] ...
}
<ervsss_value_pair> ::= ( <er_value> , <si_spacing_value> )
<er_value> ::= <value>
<si_spacing_value> ::= <value>

Object ER_VS_SI_SPACING_TABLE can be replaced by (expanded to) the ITF keyword


ER_VS_SI_SPACING followed by some arguments. These arguments must be enclosed
within curly braces. Spaces, line feeds, and indentation are allowed for readability but are
not required. The keyword appears in blue text to indicate that it is a link to a reference page
that provides more information about the keyword.
The argument list for the ER_VS_SI_SPACING keyword consists of at least one of the objects
named ervsss_value_pair. Including more than one of these objects is optional, as
indicated by the square brackets. You can include any number of these objects, as indicated
by the ellipsis (...). The square brackets and the ellipsis are not part of the final syntax.
The object named ervsss_value_pair consists of two values enclosed within
parentheses. The parentheses are not optional; they are part of the syntax. The objects are
named er_value and si_spacing_value to provide some indication of what the objects
represent. The names are not meaningful for the syntax, but are created only to link the
objects to the subsequent lines, which show that these values must be real numbers. The
reference page provides more detailed information about the arguments of the keyword.
An example of the resulting syntax is as follows:
ER_VS_SI_SPACING {
( 0.020, 7.2 )
( 0.050, 4.2 )
}

The BNF description describes ITF syntax and indicates how the ITF keywords work
together. Information about the meaning and usage of keywords and their options and
arguments appears in the keyword reference pages.

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BNF Notation Description of the ITF File


The following syntax shows the BNF notation for the standardized ITF statements. Links
shown in blue are ITF keywords.

Conventional ITF Keywords


In this section, object definitions appear after their first reference, in order of their
appearance. If an object definition includes other object definitions, those definitions appear
immediately, grouped with their parent object. Objects can be referenced multiple times, but
object definitions appear only once.
<ITF> ::=
<TECHNOLOGY_STATEMENT>
[<GLOBAL_PARAMETERS>]
<FRONTSIDE_ITF_STATEMENTS>
[<TSV_STATEMENT>]
[<BACKSIDE_ITF_STATEMENTS>]
[<VARIATION_PARAMETERS>]
[<EM_INFORMATION>]

<TECHNOLOGY_STATEMENT> ::= TECHNOLOGY = <string>

<GLOBAL_PARAMETERS> ::=
[<GLOBAL_TEMPERATURE>]
[<BACKGROUND_ER>]
[<HALF_NODE_SCALE_FACTOR>]
[<USE_SI_DENSITY>]
[<DROP_FACTOR_LATERAL_SPACING>]
[<REFERENCE_DIRECTION>]

<GLOBAL_TEMPERATURE> ::= GLOBAL_TEMPERATURE = <value>

<BACKGROUND_ER> ::= BACKGROUND_ER = <value>

<HALF_NODE_SCALE_FACTOR> ::= HALF_NODE_SCALE_FACTOR = <value>

<USE_SI_DENSITY> ::= USE_SI_DENSITY = <bool_value>


<bool_value> ::= YES | NO

<DROP_FACTOR_LATERAL_SPACING> ::= DROP_FACTOR_LATERAL_SPACING = <value>

<REFERENCE_DIRECTION> ::= REFERENCE_DIRECTION = VERTICAL | HORIZONTAL

<FRONTSIDE_ITF_STATEMENTS> ::=
<STACK_LAYERS> <VIA_LAYERS>
[<STACK_LAYERS> [<VIA_LAYERS>]]
[<MULTIGATE_DEVICES>]

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<STACK_LAYERS> ::=
<DIELECTRIC_LAYER>
| <CONDUCTING_LAYER>
| <DIELECTRIC_LAYER> <STACK_LAYERS>
| <CONDUCTING_LAYER> <STACK_LAYERS>

<DIELECTRIC_LAYER> ::=
DIELECTRIC <dielectric_name> {
ER = <value>
[<ER_VS_SI_SPACING_TABLE>]
<THICKNESS_STATEMENT> | <THICKNESS_STATEMENT_CONF>
}
<dielectric_name> ::= <string>
<ER_VS_SI_SPACING_TABLE> ::=
ER_VS_SI_SPACING {
<ervsss_value_pair> [<ervsss_value_pair>] ...
}
<ervsss_value_pair> ::= ( <er_value> , <si_spacing_value> )
<er_value> ::= <value>
<si_spacing_value> ::= <value>

<THICKNESS_STATEMENT> ::=
THICKNESS = <value>
| MEASURED_FROM = <measured_from_name>
<WALL_THICKNESS> [THICKNESS = <value>]
[DAMAGE_THICKNESS = <value> DAMAGE_ER = <value>]
<measured_from_name> ::= <dielectric_name> | TOP_OF_CHIP
<WALL_THICKNESS> ::=
SW_T = <value>
| TW_T = <value>]
| SW_T = <value> TW_T = <value>

<THICKNESS_STATEMENT_CONF> ::=
THICKNESS = <value>
| IS_CONFORMAL <WALL_THICKNESS_CONF >
[ASSOCIATED_CONDUCTOR = <conductor_name> [
<SPACER_ER_VS_WIDTH_AND_SPACING_TABLE> ]]
<WALL_THICKNESS_CONF> ::=
BW_T= <value>
| SW_T = <value>
| TW_T = <value>
| SW_T = <value> TW_T = <value>

<conductor_name> ::= <string>

<SPACER_ER_VS_WIDTH_AND_SPACING_TABLE> ::=
SPACER_ER_VS_WIDTH_AND_SPACING {
SPACINGS { <vector(m)> }
WIDTHS { <vector(n)> }
VALUES { <matrix(m,n)> }
}

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<CONDUCTING_LAYER> ::= CONDUCTOR <conductor_name> {


WMIN = <value> SMIN = <value> THICKNESS = <value>
[<AIR_GAP_VS_SPACING_TABLE>]
[<DIEL_FILL_VS_SI_SPACING_TABLE>]
[BOTTOM_DIELECTRIC_THICKNESS = <value>
BOTTOM_DIELECTRIC_ER = <value>]
[MEASURED_FROM = <dielectric_name>
| <BOTTOM_THICKNESS_VS_SI_WIDTH_TABLE>]
[T0 = <value>]
[CRT1 = <value>
| CRT2 = <value>
| CRT1 = <value> CRT2 = <value>
| <CRT_VS_SI_WIDTH_TABLE>]
[<DENSITY_BOX_WEIGHTING_FACTOR_TABLE>]
[<DEVICE_TYPE_LIST>]
[DROP_FACTOR = <value>]
[ETCH = <value>
| CAPACITIVE_ONLY_ETCH = <value>
| RESISTIVE_ONLY_ETCH = <value>]
[<ETCH_VS_WIDTH_AND_SPACING_TABLE>]
[FILL_RATIO = <value> FILL_WIDTH = <value>
FILL_SPACING = <value> FILL_TYPE = GROUNDED | FLOATING]
[GATE_TO_CONTACT_SMIN = <value>]
[<GATE_TO_DIFFUSION_CAP_TABLE>]
[<ILD_VS_WIDTH_AND_SPACING_TABLE>]
[IS_PLANAR]
[LAYER_TYPE = GATE | FIELD_POLY | DIFFUSION | TRENCH_CONTACT | BUMP
| FLOATING_GATE ]
[<POLYNOMIAL_BASED_THICKNESS_VARIATION_TABLE>]
[RAISED_DIFFUSION_ETCH = <value>
RAISED_DIFFUSION_THICKNESS = <value>
RAISED_DIFFUSION_TO_GATE_SMIN = <value>
RAISED_DIFFUSION_GATE_SIDE_CONFORMAL_ER= <value>]
[RPSQ = <value>
| RHO = <value>
| <RPSQ_VS_SI_WIDTH_TABLE>
| <RPSQ_VS_WIDTH_AND_SPACING_TABLE>
| <RHO_VS_SI_WIDTH_AND_THICKNESS_TABLE>
| <RHO_VS_WIDTH_AND_SPACING_TABLE>]
[SIDE_TANGENT = <value>]
[<THICKNESS_VS_DENSITY_TABLE>[<DENSITY_BOX_WEIGHTING_FACTOR_TABLE>]]
[<THICKNESS_VS_WIDTH_AND_SPACING_TABLE>]
[<TVF_FILE> <TVF_ADJUSTMENT_TABLES>]
[<FLOATING_GATE_TO_DIFFUSION_CONTACT_CAP_TABLE>]
}

<AIR_GAP_VS_SPACING_TABLE> ::=
AIR_GAP_VS_SPACING {
SPACINGS { <vector(n)> }
AIR_GAP_WIDTHS { <vector(n)> }
AIR_GAP_THICKNESSES { <vector(n)> }
AIR_GAP_BOTTOM_HEIGHTS { <vector(n)> }
}

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Description of the ITF FileITF 1-7
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<DIEL_FILL_VS_SI_SPACING_TABLE> ::=
DIELECTRIC_FILL_VS_SI_SPACING {
SPACINGS { <vector(n)> }
WIDTHS { <vector(n)> }
THICKNESSES { <vector(n)> }
BOTTOM_HEIGHTS { <vector(n)> }
SIDE_TANGENTS { <vector(n)> }
ERS { <vector(n)> }
}

<BOTTOM_THICKNESS_VS_SI_WIDTH_TABLE> ::=
BOTTOM_THICKNESS_VS_SI_WIDTH
[RESISTIVE_ONLY_ETCH | CAPACITIVE_ONLY_ETCH] {
<btvsiw_value_pair> [<btvsiw_value_pair>] ...
}
<btvsiw_value_pair> ::= ( <si_width_value> , <bottom_thickness_value> )
<si_width_value> ::= <value>
<bottom_thickness_value> ::= <value>

<CRT_VS_SI_WIDTH_TABLE> ::=
CRT_VS_SI_WIDTH {
<crtvsiw_value_triple> [<crtvsiw_value_triple>]
}
<crtvsiw_value_triple> ::=
( <si_width_value> , <crt1_value> , <crt2_value> )
<crt1_value> ::= <value>
<crt2_value> ::= <value>

<DEVICE_TYPE_LIST> ::=
DEVICE_TYPE { <device_type_name_list> | ALL | NONE }
<device_type_name_list> ::= <string>

<ETCH_VS_WIDTH_AND_SPACING_TABLE> ::=
ETCH_VS_WIDTH_AND_SPACING {
[ETCH_FROM_TOP | RESISTIVE_ONLY | CAPACITIVE_ONLY]
[PARALLEL_TO_REFERENCE | PERPENDICULAR_TO_REFERENCE
| PARALLEL_TO_GATE]
[NUMBER_OF_MASKS = <n>]
[MASKS(<mask1>,<mask2>)]
SPACINGS { <vector(n)> }
WIDTHS { <vector(m)> }
VALUES { <matrix(m,n)> }
}
<mask1> ::= <n>
<mask2> ::= <n>

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<GATE_TO_DIFFUSION_CAP_TABLE> ::= GATE_TO_DIFFUSION_CAP {


<one_gtdcap_table> | <multiple_gtd_tables>
}
<one_gtdcap_table> ::= {
CONTACT_TO_CONTACT_SPACINGS { <vector(n)> }
GATE_TO_CONTACT_SPACINGS { <vector(m)> }
CAPS_PER_MICRON { <matrix(m,n)> }
[GATE_WIDTHS { <vector(n)> }
GATE_TO_CONTACT_SPACINGS { <vector(m)> }
CAPS_PER_MICRON { <matrix(m,n)> } ]
}
<multiple_gtd_tables> ::=
NUMBER_OF_TABLES = <n>
<named_gtd_table> n
}
<named_gtd_table> ::= <table_name> {
CONTACT_TO_CONTACT_SPACINGS { <vector(n)> }
GATE_TO_CONTACT_SPACINGS { <vector(m)> }
CAPS_PER_MICRON { <matrix(m,n)> }
[GATE_WIDTHS { <vector(n)> }
GATE_TO_CONTACT_SPACINGS { <vector(m)> }
CAPS_PER_MICRON { <matrix(m,n)> } ]
}
<table_name> ::= <string>

<ILD_VS_WIDTH_AND_SPACING_TABLE> ::= ILD_VS_WIDTH_AND_SPACING {


DIELECTRIC = <dielectric_name>
SPACINGS { <vector(n)> }
WIDTHS { <vector(m)> }
VALUES { <matrix(m,n)> }
}

<POLYNOMIAL_BASED_THICKNESS_VARIATION_TABLE> ::=
POLYNOMIAL_BASED_THICKNESS_VARIATION {
[SI_]DENSITY_POLYNOMIAL_ORDERS = { <vector(n)> }
[SI_]WIDTH_POLYNOMIAL_ORDERS = { <vector(m)> }
WIDTH_RANGES = { <vector(r)> }
POLYNOMIAL_COEFFICIENTS = { <matrix(m,n)> } r+1
[DENSITY_BOUNDS_VS_WIDTH {
(<dbvw_value_triple>) [(<dbvw_value_triple>] }
[THICKNESS_BOUNDS { <min_thick_value> <max_thick_value> } ]
}
<dbvw_value_triple> ::=
( <width_value> , <min_density_value> , <max_density_value> )
<width_value> ::= <value>
<min_density_value> ::= <value>
<max_density_value> ::= <value>
<min_thick_value> ::= <value>
<max_thick_value> ::= <value>

Chapter 1: Backus-Naur Form of the Standardized ITF


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Description of the ITF FileITF 1-9
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<RPSQ_VS_SI_WIDTH_TABLE> ::= RPSQ_VS_SI_WIDTH {


<rpsqvsiw_value_pair> [<rpsqvsiw_value_pair>] ...
}
<rpsqvsiw_value_pair> ::= ( <si_width_value> , <rpsq_value> )
<rpsq_value> ::= <value>

<RPSQ_VS_WIDTH_AND_SPACING_TABLE> ::=
RPSQ_VS_WIDTH_AND_SPACING {
SPACINGS { <vector(n)> }
WIDTHS { <vector(m)> }
VALUES { <matrix(m,n)> }
}

<RHO_VS_SI_WIDTH_AND_THICKNESS_TABLE> ::=
RHO_VS_SI_WIDTH_AND_THICKNESS {
WIDTH { <vector(n)> }
THICKNESS { <vector(m)> }
VALUES { <matrix(m,n)> }
}

<RHO_VS_WIDTH_AND_SPACING_TABLE> ::=
RHO_VS_WIDTH_AND_SPACING {
SPACINGS { <vector(n)> }
WIDTHS { <vector(m)> }
VALUES { <matrix(m,n)> }
}
<THICKNESS_VS_DENSITY_TABLE> ::=
THICKNESS_VS_DENSITY [ RESISTIVE_ONLY | CAPACITIVE_ONLY ]{
<tvd_value_pair> [<tvd_value_pair>]
}
<tvd_value_pair> ::= ( <density_value> , <thickness_change_value> )
<density_value> ::= <value>
<thickness_change_value> ::= <value>
<DENSITY_BOX_WEIGHTING_FACTOR_TABLE> ::=
DENSITY_BOX_WEIGHTING_FACTOR {
<dbwf_value_pair> [<dbwf_value_pair>]
}
<dbwf_value_pair> ::= ( <box_size> , <weight_factor> )
<box_size> ::= <value>
<weight_factor> ::= <value>

<THICKNESS_VS_WIDTH_AND_SPACING_TABLE> ::=
THICKNESS_VS_WIDTH_AND_SPACING
[ RESISTIVE_ONLY | CAPACITIVE_ONLY ]{
SPACINGS { <vector(n)> }
WIDTHS { <vector(m)> }
VALUES { <matrix(m,n)> }
}
<TVF_FILE> ::= <string>

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<TVF_ADJUSTMENT_TABLES> ::= TVF_ADJUSTMENT_TABLES {


<TVF_BOTTOM_THICKNESS_VS_WIDTH_AND_SPACING_TABLE>
| <TVF_BOTTOM_THICKNESS_VS_WIDTH_AND_DELTAPD_TABLE>
| <TVF_BOTTOM_THICKNESS_VS_WIDTH_AND_SPACING_TABLE>
<TVF_BOTTOM_THICKNESS_VS_WIDTH_AND_DELTAPD_TABLE>
}
<TVF_BOTTOM_THICKNESS_VS_WIDTH_AND_SPACING_TABLE> ::=
BOTTOM_THICKNESS_VS_WIDTH_AND_SPACING {
SPACINGS { <vector(n)> }
WIDTHS { <vector(m)> }
VALUES { <matrix(m,n)> }
}
<TVF_BOTTOM_THICKNESS_VS_WIDTH_AND_DELTAPD_TABLE> ::=
BOTTOM_THICKNESS_VS_WIDTH_AND_DELTAPD {
SPACINGS { <vector(n)> }
WIDTHS { <vector(m)> }
VALUES { <matrix(m,n)> }
}
<FLOATING_GATE_TO_DIFFUSION_CONTACT_CAP_TABLE> ::=
FLOATING_GATE_TO_DIFFUSION_CONTACT_CAP {
GATE_POLYGON_LENGTH { <vector(n)> }
GATE_TO_CONTACT_SPACING { <vector(n)> }
CAPACITANCE_VALUES { <vector(n)> }
}
<VIA_LAYERS> ::= <VIA_LAYER> | <VIA_LAYER> <VIA_LAYERS>
<VIA_LAYER> ::= <STD_VIA> | <TC_VIA> | <TC_VIA_SI>

<STD_VIA> ::= VIA <via_name> {


FROM = <conductor_name> TO = <conductor_name>
[T0 = <value>]
[CRT1 = <value>
| CRT2 = <value>
| CRT1 = <value> CRT2 = <value>
| <CRT_VS_AREA_TABLE>]
RHO = <value>
| RPV = <value> AREA = <value>
| <RPV_VS_AREA_TABLE>
[<ETCH_VS_CONTACT_AND_GATE_SPACINGS_TABLE>
| <ETCH_VS_WIDTH_AND_LENGTH_TABLE>]
[<RPV_VS_COVERAGE_TABLES>]
<via_name> ::= <string>

<CRT_VS_AREA_TABLE> ::=
CRT_VS_AREA {
<crtva_value_triple> [<crtva_value_triple>] ... }
<crtva_value_triple> ::=
( <via_area_value> , <crt1_value> , <crt2_value> )
<via_area_value> ::= <value>

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<RPV_VS_AREA_TABLE> ::=
RPV_VS_AREA { <rpvva_pair> [<rpvva_pair>] ... }
<rpvva_pair> ::= ( <area_value> , <rpv_value> )
<area_value> ::= <value>
<rpv_value> ::= <value>

<ETCH_VS_CONTACT_AND_GATE_SPACINGS_TABLE> ::=
ETCH_VS_CONTACT_AND_GATE_SPACINGS CAPACITIVE_ONLY {
CONTACT_SPACING { <vector(n)> }
GATE_SPACING { <vector(m)> }
VALUES { <matrix(m,n)> }
}

<ETCH_VS_WIDTH_AND_LENGTH_TABLE> ::=
ETCH_VS_WIDTH_AND_LENGTH CAPACITIVE_ONLY {
LENGTHS { <vector(n)> }
WIDTHS { <vector(m)> }
VALUES { <matrix(m,n)> }
}

<RPV_VS_COVERAGE_TABLES> ::=
RPV_VS_COVERAGE { <via_size_table> [<via_size_table] }
<via_size_table> ::=
VIA_SIZE { <x_size> <y_size> }
COV_X { <vector(m)> }
COV_Y { <vector(n)> }
VALUES { <matrix(m,n)> }
<x_size> ::= <value>
<y_size> ::= <value>

<TC_VIA> ::= VIA <via_name> {


FROM = <conductor_name> TO = <conductor_name>
<RPV_VS_WIDTH_AND_LENGTH_TABLE>
}

<RPV_VS_WIDTH_AND_LENGTH_TABLE> ::=
RPV_VS_WIDTH_AND_LENGTH {
LENGTHS { <vector(m)> }
WIDTHS { <vector(n)> }
VALUES { <matrix(m,n)> }
}
<TC_VIA_SI> ::= VIA <via_name> {
FROM = <conductor_name> TO = <conductor_name>
ETCH_ASSOCIATED_LAYER ::= <string>
<RPV_VS_SI_WIDTH_AND_LENGTH_TABLE>
}

<RPV_VS_SI_WIDTH_AND_LENGTH_TABLE> ::=
RPV_VS_SI_WIDTH_AND_LENGTH {
LENGTHS { <vector(m)> }
WIDTHS { <vector(n)> }
VALUES { <matrix(m,n)> }
}

Backus-Naur Form of the Standardized ITF 1-12


Interconnect Technology Format Specification Version 2015.06

<MULTIGATE_DEVICES> ::= MULTIGATE <multi_dev_name> {


FIN_SPACING = <value>
FIN_WIDTH = <value>
FIN_LENGTH = <value>
[FIN_THICKNESS = <value>]
[RAISED_DIFFUSION_GROWTH = <value>]
[GATE_POLY_EXTENSION_LENGTH = <value>]
[TRENCH_CONTACT_EXTENSION_LENGTH = <value>]
GATE_OXIDE_TOP_T = <value>
GATE_OXIDE_SIDE_T = <value>
GATE_OXIDE_ER = <value>
GATE_POLY_TOP_T = <value>
GATE_POLY_SIDE_T = <value>
CHANNEL_ER = <value>
GATE_DIFFUSION_LAYER_PAIR { (<gd_pair> [<gd_pair>] }
<multi_dev_name> ::= <string>
<gd_pair> ::= (<gate_layer> <diff_layer>)
<gate_layer> ::= <string>
<diff_layer> ::= <string>

<TSV_STATEMENT> ::= TSV <tsv_name> {


FROM = <conductor_name>
TO = <conductor_name>
RHO = <value>
AREA = <value>
THICKNESS = <value>
INSULATION_THICKNESS = <value>
INSULATION_ER = <value>
[T0 = <value>]
[CRT1 = <value>
| CRT2 = <value>
| CRT1 = <value> CRT2 = <value>]
CSUB_VS_SPACING { <csub_value_pair> [csub_value_pair> }
RSUB_BS_SPACING { <rsub_value_pair> [csub_value_pair> }
}
<tsv_name> ::= <string>
<csub_value_pair> ::= ( <tsv_cap> , <tsv_spacing> )
<rsub_value_pair> ::= ( <tsv_res> , <tsv_spacing> )
<tsv_cap> ::= <value>
<tsv_spacing> ::= <value>
<tsv_res> ::= <value>

<BACKSIDE_ITF_STATEMENTS> ::=
<STACK_LAYERS> <VIA_LAYERS>
[<STACK_LAYERS> [<VIA_LAYERS>]]

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<VARIATION_PARAMETERS> ::= VARIATION_PARAMETERS { <VAR_TABLE> }


<VAR_TABLE> ::= <var_name> = { <var_triple> [<var_triple>] }
<var_name> ::= <string>
<var_triple> ::=
( <var_layer> , <var_parameter_type> , <var_coefficient> )
<var_layer> ::= <conductor_name> | <dielectric_name>
<var_parameter_type> ::= THICKNESS | WIDTH | ER | RHO
<var_coefficient> ::= <value>

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Electromigration ITF Keywords


In this section, object definitions appear in approximate hierarchical order. Higher-level
objects appear before lower-level objects; the definitions of objects within those high-level
objects might not appear until much later in the section. Exceptions are usually simple
definitions, which might appear immediately after their first reference. Objects can be
referenced multiple times, but object definitions appear only once.
<EM_INFORMATION> ::=
EM_INFORMATION
<EM_INFORMATION_FILE> | <EM_INFORMATION_SECTION>
END_OF_EM_INFORMATION

<EM_INFORMATION_FILE> ::=
INCLUDE_EM_INFORMATION_FILE = <em_info_filename>
<em_info_filename> ::= <string>

<EM_INFORMATION_SECTION> ::=
[<COMMON_INFO_BLOCK>]
[<LAYERS_EM_INFO_BLOCK> ]
[<VIAS_EM_INFO_BLOCK> ]
[<VIA_ARRAY_EM_INFO_BLOCK> ]

<COMMON_INFO_BLOCK> ::=
COMMON_INFO {
ITF_EM_VERSION = <version_name>
REFERENCE_TEMPERATURE = <value>
[<COMMON_INFO_AVERAGE_MODULE>]
[<COMMON_INFO_RMS_MODULE>]
[<COMMON_INFO_PEAK_MODULE>]
}
<version_name> ::= <string>

<LAYERS_EM_INFO_BLOCK> ::=
LAYER <layer_name> {
[<LAYERS_EM_INFO_AVERAGE_MODULE>]
[<LAYERS_EM_INFO_RMS_MODULE>]
[<LAYERS_EM_INFO_PEAK_MODULE>]
}
<layer_name>::=<string>

<VIAS_EM_INFO_BLOCK> ::=
VIA <via_name_em> {
[<VIAS_EM_INFO_AVERAGE_MODULE>]
[<VIAS_EM_INFO_RMS_MODULE>]
[<VIAS_EM_INFO_PEAK_MODULE>]
}
<via_name_em>::=<string>

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<VIA_ARRAY_EM_INFO_BLOCK> ::=
VIA_ARRAY {
<VIA_ARRAY_NAME_VALUE_PAIR>
}
<VIA_ARRAY_NAME_VALUE_PAIR> ::= <via_name_em> <value>

<COMMON_INFO_AVERAGE_MODULE> ::=
AVERAGE {
[TTF_TEMPERATURE { <vector(n)> } TTF_FACTOR { <vector(n)> }]
[VIA_COVER_LANDING_TYPE {
FF FQ FS FP QF QQ QS QP SF SQ SS SP PF PQ PS PP } ]
[<LAYERS_EM_INFO_AVERAGE_MODULE>]
[<VIAS_EM_INFO_AVERAGE_MODULE>]
}

<COMMON_INFO_RMS_MODULE> ::=
RMS {
[<LAYERS_EM_INFO_RMS_MODULE>]
[<VIAS_EM_INFO_RMS_MODULE>]
}

<COMMON_INFO_PEAK_MODULE> ::=
PEAK {
[<LAYERS_EM_INFO_PEAK_MODULE>]
[<VIAS_EM_INFO_PEAK_MODULE>]
}

<LAYERS_EM_INFO_AVERAGE_MODULE> ::=
AVERAGE {
[CURRENT_DEFAULT_AVERAGE = <value>]
[CURRENT_DENSITY_DEFAULT_AVERAGE = <value>]
METAL_WIDTH_CUTOFF = <value>
<RATING_FACTOR>
<FUNCTION_DESCRIPTION> | <LAYER_TABLE_DESCRIPTION_AVERAGE>
}

<LAYERS_EM_INFO_RMS_MODULE> ::=
RMS {
[CURRENT_DEFAULT_RMS = <value>]
[CURRENT_DENSITY_DEFAULT_RMS= <value>]
METAL_WIDTH_CUTOFF = <value>
<RMS_SPACING_FACTORS>
<RATING_FACTOR>
<FUNCTION_DESCRIPTION> | <LAYER_TABLE_DESCRIPTION_RMS>
}

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<LAYERS_EM_INFO_PEAK_MODULE> ::=
PEAK {
[CURRENT_DEFAULT_PEAK = <value>]
[CURRENT_DENSITY_DEFAULT_PEAK= <value>]
METAL_WIDTH_CUTOFF = <value>
<RATING_FACTOR>
<FUNCTION_DESCRIPTION> | <LAYER_TABLE_DESCRIPTION_PEAK>
}

<VIAS_EM_INFO_AVERAGE_MODULE> ::=
AVERAGE {
[CURRENT_DEFAULT_AVERAGE = <value>]
[CURRENT_DENSITY_DEFAULT_AVERAGE = <value>]
CURRENT_DIRECTION DOWNSTREAM | UPSTREAM
<RATING_FACTOR>
<FUNCTION_DESCRIPTION> | <VIA_TABLE_DESCRIPTION_AVERAGE>
}

<VIAS_EM_INFO_RMS_MODULE> ::=
RMS {
[CURRENT_DEFAULT_RMS = <value>]
[CURRENT_DENSITY_DEFAULT_RMS= <value>]
<RATING_FACTOR>
<FUNCTION_DESCRIPTION> | <VIA_TABLE_DESCRIPTION>
}

<VIAS_EM_INFO_PEAK_MODULE> ::=
PEAK {
[CURRENT_DEFAULT_PEAK = <value>]
[CURRENT_DENSITY_DEFAULT_PEAK= <value>]
<RATING_FACTOR>
<FUNCTION_DESCRIPTION> | <VIA_TABLE_DESCRIPTION>
}

<RMS_SPACING_FACTORS> ::=
RMS_SPACING_FACTOR_TABLE {
VIA_VIA_SPACING { <vector(n)> }
FACTOR_VALUES { <vector(n)> }
}

<RATING_FACTOR> ::=
RATING_TEMPERATURE { <vector(n)> }
RATING_FACTOR { <vector(n)> }

<FUNCTION_DESCRIPTION> ::=
CURRENT_FUNCTION {
[<var_type> ]
<CONDITION_CASE> | <FUNCTION_EXPRESSION>
}
<var_type> ::= WIDTH | DELTA_TEMPERATURE | LENGTH

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<CONDITION_CASE> ::= CONDITION {


<ONE_CONDITION_VARIABLE>
<FUNCTION_EXPRESSION> n
}

<ONE_CONDITION_VARIABLE> ::=
<CONDITION_VAR_VALUES> | <CONDITION_VAR_RANGES>
<CONDITION_VAR_VALUES> ::= <var_name> == { <vector(n)> }
<CONDITION_VAR_RANGES> ::= <var_name> { <vector(n-1)> }

<FUNCTION_EXPRESSION> ::= EXPRESSION = <expr>

<LAYER_TABLE_DESCRIPTION_AVERAGE> ::=
<LAYER_CURRENT_TABLE_AVERAGE> | <LAYER_CURRENT_DENSITY_TABLE>

<LAYER_TABLE_DESCRIPTION_RMS> ::=
<LAYER_CURRENT_TABLE_RMS> | <LAYER_CURRENT_DENSITY_TABLE>

<LAYER_TABLE_DESCRIPTION_PEAK> ::=
<LAYER_CURRENT_TABLE_PEAK> | <LAYER_CURRENT_DENSITY_TABLE>

<LAYER_CURRENT_TABLE_AVERAGE> ::=
LAYER_CURRENT_TABLE {
VIA_SIZE_LIST { <via_size_name> n }
VIA_TYPES { [SINGLE | ARRAY] m }
TEMPERATURE { <vector(t)> }
METAL_LENGTH_VALUES { <vector(s)> }
METAL_WIDTH_VALUES { <vector(p)> }
CURRENT_VALUES { <vector(n*m*p*t*s)> }
}

<LAYER_CURRENT_TABLE_RMS> ::=
LAYER_CURRENT_TABLE {
VIA_SIZE_LIST { <via_size_name> n }
VIA_TYPES { [SINGLE | ARRAY] m }
DELTA_TEMPERATURE { <vector(t)> }
METAL_WIDTH_VALUES { <vector(p)> }
CURRENT_VALUES { <vector(n*m*p*t)> }
}

<LAYER_CURRENT_TABLE_PEAK> ::=
LAYER_CURRENT_TABLE {
VIA_SIZE_LIST { <via_size_name> n }
VIA_TYPES { [SINGLE | ARRAY] m }
METAL_WIDTH_VALUES { <vector(p)> }
CURRENT_VALUES { <vector(n*m*p)> }
}

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<LAYER_CURRENT_DENSITY_TABLE> ::=
LAYER_CURRENT_DENSITY_TABLE {
VIA_SIZE_LIST { <via_size_name> n }
VIA_TYPES { [SINGLE | ARRAY] m }
METAL_WIDTH_RANGES{ <vector(p-1)> }
CURRENT_DENSITY_VALUES { <vector(n*m*p)> }
}

<VIA_TABLE_DESCRIPTION_AVERAGE> ::=
VIA_ARRAY_MULTIPLIER { <vector(n)> }
<VIA_SIZE>
<VIA_CURRENT_TABLES_AVERAGE>

<VIA_SIZE> ::= VIA_SIZE { <VIA_SIZE_TABLE> }

<VIA_SIZE_TABLE> ::= <via_size_name> { <width_value>, <length_value> }


<via_size_name> ::= <string>
<width_value> ::= <value>
<length_value> ::= <value>

<VIA_CURRENT_TABLES_AVERAGE> ::=
VIA_CURRENT_TABLE {
VIA_COVER_LANDING_TYPE {
FF FQ FS FP QF QQ QS QP SF SQ SS SP PF PQ PS PP }
METAL_LENGTH_VALUES { <vector(n)> }
CONTACT_AREA { <vector(p)> }
TEMPERATURE { <vector(r)> }
VIA_SIZE_LIST { <via_size_name> n }
CURRENT_VALUES { <vector(16*2*n)> }
}
<VIA_TABLE_DESCRIPTION> ::=
VIA_ARRAY_MULTIPLIER { <vector(n)> }
<VIA_SIZE>
<VIA_CURRENT_TABLES>

<VIA_CURRENT_TABLES> ::=
VIA_CURRENT_TABLE {
VIA_COVER_LANDING_TYPE {
FF FQ FS FP QF QQ QS QP SF SQ SS SP PF PQ PS PP }
VIA_SIZE_LIST { <via_size_name> n }
CURRENT_VALUES { <vector(16*2*n)> }
}

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Backus-Naur
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Backus-Naur Form of the Standardized ITF 1-20


2
Conventional ITF Syntax Specification 2
This chapter describes the conventional ITF statements and their options.

Nomenclature
The terms statement, command, option, and keyword are synonymous. The term block
refers to a group of related statements.

Comments in an ITF File


In an ITF file, a dollar sign ($) at the beginning of a line indicates a comment that is not
interpreted by the extraction tool.

Restrictions for Layer Names


In the CONDUCTOR, DIELECTRIC, and VIA statements, the case-sensitive layer names
Must contain only alphanumeric characters and underscores (_)
Must begin with an alphabetic character
Must not begin with a number or an underscore (_)
Must not contain periods

2-1
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AIR_GAP_VS_SPACING
Defines air gap parameters. Valid within a CONDUCTOR block.

Syntax
AIR_GAP_VS_SPACING {
SPACINGS { s1 s2 .. sn }
AIR_GAP_WIDTHS { w(s1) w(s2) w(sn) }
AIR_GAP_THICKNESSES { t(s1) t(s2) t(sn) }
AIR_GAP_BOTTOM_HEIGHTS { h(s1) h(s2) h(sn) }
}

Arguments

Argument Description

s1 s2 sn Spacing between the two conductors.


Units: microns

w(s1) w(s2) w(sn) Width of the air gap formed at the corresponding spacing value.
Units: microns

t(s1) t(s2) t(sn) Thickness of the air gap formed at the corresponding spacing
value.
Units: microns

h(s1) h(s2) h(sn) Height of the bottom of the air gap from the bottom of the
conductor at the corresponding spacing value.
Units: microns

Description
Use an AIR_GAP_VS_SPACING table to define the parameters of an air gap. The number of
arguments in each row of the table must be equal. The smallest spacing value s1 must be
equal to the value of the SMIN keyword used in the CONDUCTOR statement.
If the spacing between the polygons is greater than sn, an air gap does not form.
Lists of values are interpreted on a sequential basis, independent of any carriage returns or
other hidden characters.

Conventional ITF Syntax Specification 2-2


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Example
AIR_GAP_VS_SPACING {
SPACINGS { 0.3 0.5 0.7 1.0 3.0 }
AIR_GAP_WIDTHS { 0.1 0.09 0.09 0.15 0.20 }
AIR_GAP_THICKNESSES { 0.2 0.23 0.25 0.26 0.28 }
AIR_GAP_BOTTOM_HEIGHTS { 0.1 0.14 0.18 0.20 0.22 }
}

See Also
CONDUCTOR

Chapter 2: Conventional ITF Syntax Specification


Conventional ITF Syntax Specification
AIR_GAP_VS_SPACING 2-3
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AREA
Specifies the default area of a via. Valid within a VIA or TSV block.

Syntax
AREA = via_area

Arguments

Argument Description

via_area Area of default via.


Units: square microns
Default: 1.0e -6

Description
Within a VIA block, the resistive properties of a via layer must be specified with one of three
mutually exclusive methods:
Using the RHO keyword.
Using the RPV and AREA keywords (these keywords cannot be used alone in a VIA block).
Using an RPV_VS_AREA table to specify resistance values for different via areas.

Within a TSV block, the AREA keyword is a required keyword.

Example
VIA via1 { FROM=m1 TO=m2 AREA=4 RPV=0.25 }

See Also
RHO

RPV

RPV_VS_AREA

VIA

TSV

Conventional ITF Syntax Specification 2-4


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ASSOCIATED_CONDUCTOR
Names a conductor layer associated with a conformal dielectric layer. Valid within a
DIELECTRIC block.

Syntax
ASSOCIATED_CONDUCTOR = layer_name

Arguments

Argument Description

layer_name Associated conductor layer name

Description
Used within a DIELECTRIC block, the ASSOCIATED_CONDUCTOR keyword names a specific
conductor layer to which a dielectric layer conforms. The following usage notes apply:
Only one ASSOCIATED_CONDUCTOR keyword is allowed within a DIELECTRIC block.
The ASSOCIATED_CONDUCTOR keyword can only be used with the IS_CONFORMAL
keyword. However, the IS_CONFORMAL keyword can be used without the
ASSOCIATED_CONDUCTOR keyword. When no ASSOCIATED_CONDUCTOR keyword is
specified for an IS_CONFORMAL layer, the default is to measure from the top layer.
Using the IS_CONFORMAL and ASSOCIATED_CONDUCTOR keywords is mutually exclusive
with using the MEASURED_FROM keyword within the same DIELECTRIC block.
When an ASSOCIATED_CONDUCTOR layer drops because of a DROP_FACTOR defined for a
layer below it, the related IS_CONFORMAL dielectric layers also drop.
If a conductor above a conformal dielectric layer overlaps with the dielectric layer top wall
thickness, the conductor cuts into the dielectric layer.

Example
DIELECTRIC D1 {
IS_CONFORMAL
ASSOCIATED_CONDUCTOR=met1
SW_T=0.1 TW_T=0.1 ER=2.5
}

See Also
IS_CONFORMAL

DIELECTRIC

Chapter 2: Conventional ITF Syntax Specification


Conventional ITF Syntax Specification
ASSOCIATED_CONDUCTOR 2-5
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BACKGROUND_ER
Specifies the relative permittivity (dielectric constant) of the background dielectric.

Syntax
BACKGROUND_ER = relative_permittivity

Arguments

Argument Description

relative_permittivity Relative permittivity


Default: 1.0

Description
The BACKGROUND_ER statement is an optional statement that can be included in the global
parameters section of the ITF file. If the BACKGROUND_ER statement is not specified, the
relative permittivity of the background dielectric defaults to 1.0, the relative permittivity of air.
The background dielectric globally fills the cross section to an infinite height, effectively
replacing air as the operating medium for the chip.
Relative permittivity settings within individual DIELECTRIC blocks override the global
background value.

Example
TECHNOLOGY = example_tech
GLOBAL_TEMPERATURE = 31.0
BACKGROUND_ER = 4.1

Conventional ITF Syntax Specification 2-6


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BOTTOM_DIELECTRIC_ER
Specifies the relative permittivity of the dielectric region below a conductor. Valid within a
CONDUCTOR block.

Syntax
BOTTOM_DIELECTRIC_ER = permittivity

Arguments

Argument Description

permittivity Relative permittivity of the dielectric

Description
The BOTTOM_DIELECTRIC_ER keyword must be specified along with the
BOTTOM_DIELECTRIC_THICKNESS keyword within a CONDUCTOR block. If the specified
conductor layer does not appear in a certain model, the bottom dielectric layer does not
appear in the model either.

Example
BOTTOM_DIELECTRIC_ER = 4.0

See Also
BOTTOM_DIELECTRIC_THICKNESS

CONDUCTOR

Chapter 2: Conventional ITF Syntax Specification


Conventional ITF Syntax Specification
BOTTOM_DIELECTRIC_ER 2-7
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BOTTOM_DIELECTRIC_THICKNESS
Specifies the thickness of the dielectric region below a conductor. Valid within a CONDUCTOR
block.

Syntax
BOTTOM_DIELECTRIC_THICKNESS = thickness

Arguments

Argument Description

thickness Thickness of the dielectric


Units: microns

Description
The BOTTOM_DIELECTRIC_THICKNESS keyword must be specified along with the
BOTTOM_DIELECTRIC_ER option within a CONDUCTOR statement. If the specified conductor
layer does not appear in a certain model, the bottom dielectric layer does not appear in the
model either.
If a conductor with a bottom dielectric also has conformal dielectrics on the sides of the
conductor, the side conformal dielectric layers extend to the lowest surface of the bottom
conformal dielectric, as shown in Figure 2-1. When placing a conductor with bottom
dielectric in the dielectric stack, the lowest surface of the bottom dielectric layer sits on the
top surface of the planar dielectric layer defined below the conductor.
To specify the thickness of the conductor with the bottom dielectric layer, use the THICKNESS
option in the CONDUCTOR statement. The top of a conductor that includes a bottom dielectric
is placed above the planar dielectric at a height equal to the sum of the conductor thickness
and the bottom dielectric thickness.

Conventional ITF Syntax Specification 2-8


Interconnect Technology Format Specification Version 2015.06

Examples

High-Permittivity Gate Oxide


The high-permittivity dielectric under the gate shown in Figure 2-1 can be modeled with the
following statements:
CONDUCTOR gpoly {
THICKNESS = 0.06
WMIN = 0.03
SMIN = 0.03
BOTTOM_DIELECTRIC_THICKNESS = 0.002
BOTTOM_DIELECTRIC_ER = 10.0
}

Figure 2-1 Modeling High-Permittivity Dielectric Under the Gate

contacts
dielectric

gate poly

diffusion

substrate

gate oxide

Independent Bottom Dielectric Regions in Covertical Conducting Layers


You can define independent bottom dielectric regions in covertical conducting layers. For
example, pgpoly and ngpoly conductors with different bottom dielectric regions, as shown in
Figure 2-2, can be specified with the following statements:
CONDUCTOR pgpoly {
THICKNESS = 0.06 WMIN = 0.03 SMIN = 0.03
BOTTOM_DIELECTRIC_THICKNESS = 0.002
BOTTOM_DIELECTRIC_ER = 10.0
}
CONDUCTOR ngpoly {
THICKNESS = 0.06 WMIN = 0.03 SMIN = 0.03
BOTTOM_DIELECTRIC_THICKNESS = 0.004
BOTTOM_DIELECTRIC_ER = 12.0
}

Chapter 2: Conventional ITF Syntax Specification


Conventional ITF Syntax Specification
BOTTOM_DIELECTRIC_THICKNESS 2-9
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Figure 2-2 Bottom Dielectric Layer With Covertical Layers

pgpoly ngpoly

See Also
BOTTOM_DIELECTRIC_ER

CONDUCTOR

Conventional ITF Syntax Specification 2-10


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BOTTOM_THICKNESS_VS_SI_WIDTH
Specifies the bottom thickness of a conductor layer at different widths. Valid within a
CONDUCTOR block.

Syntax
BOTTOM_THICKNESS_VS_SI_WIDTH [RESISTIVE_ONLY | CAPACITIVE_ONLY]
{ (s1, r1) (s2, r2) (sn, rn) }

Arguments

Argument Description

RESISTIVE_ONLY Applies thickness adjustment to resistance only.

CAPACITIVE_ONLY Applies thickness adjustment to capacitance only.

s1 sn Silicon widths in ascending order. The first entry should be the


smallest possible silicon width of the layer coming from the drawn
WMIN value.

r1 rn Relative changes in bottom thickness. This is the absolute thickness


change from the bottom divided by the nominal thickness of the layer.
A bottom thickness or BTi is positive if the thickness becomes larger in
the nominal value. A bottom thickness BTi is negative if the thickness
becomes smaller than the nominal value.

Description
The BOTTOM_THICKNESS_VS_SI_WIDTH option models the bottom thickness of a conductor.
In a damascene process, deposited metal fills previously etched trenches. The variation in
the trench etch depth affects the thickness of the interconnect as well as the vertical
distance between metal interconnects. Both parasitic resistance and capacitance can be
affected by these variations.
The following limitations apply:
You can specify the BOTTOM_THICKNESS_VS_SI_WIDTH option along with the thickness
variation from the top of the conductor by using the following options:
THICKNESS_VS_DENSITY, THICKNESS_VS_WIDTH_AND_SPACING,
POLYNOMIAL_BASED_THICKNESS_VARIATION.

The BOTTOM_THICKNESS_VS_SI_WIDTH option cannot be specified in the same


CONDUCTOR statement as the MEASURED_FROM option.

Chapter 2: Conventional ITF Syntax Specification


Conventional ITF Syntax Specification
BOTTOM_THICKNESS_VS_SI_WIDTH 2-11
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Effective Thickness Calculation


The effective thickness is calculated with the following equation:
T = Tnom ( 1 + RTf(Deff) + RTf(W, S) + RTf(SiW) )
where
Tnom is the nominal thickness specified in the ITF.
RTf(Deff) is the relative thickness change due to density.
RTf(W,S) is the relative change in thickness due to width and spacing.
RTf(SiW) is the relative change in thickness due to silicon width.

The resistance and capacitance are computed after the effective thickness is computed.

See Also
CONDUCTOR

THICKNESS_VS_DENSITY

THICKNESS_VS_WIDTH_AND_SPACING

POLYNOMIAL_BASED_THICKNESS_VARIATION

MEASURED_FROM

Conventional ITF Syntax Specification 2-12


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BW_T
Specifies the extension distance (bottom wall thickness) of the conformal dielectric below
the conductor. Valid within a DIELECTRIC block.

Syntax
BW_T = bw_thick

Arguments

Argument Description

bw_thick Specifies the bottom conformal thickness.


Units: microns
Default: thickness value of the dielectric

Description
The BW_T option works with the RAISED_DIFFUSION_GATE_SIDE_CONFORMAL_ER option,
which specifies the dielectric constant of the associated silicon dielectric area between the
raised diffusion and the gate processes. The BW_T value specifies the extension distance
of the conformal dielectric below the conductor.
You can associate multiple conformal dielectric layers with BW_T values specified for the
same conductor to produce multiple bottom conformal dielectrics. The BW_T thicknesses of
multiple conformal dielectrics are additive. The BW_T dielectric listed first in the ITF file is
the topmost BW_T dielectric associated with a particular conductor, that is, the closest
bottom conformal dielectric to the conductor.
Use the following guidelines for the BW_T option:
The BW_T keyword can only be used in dielectric statements that also contain
IS_CONFORMAL and ASSOCIATED_CONDUCTOR keywords.

The DAMAGE_THICKNESS and DAMAGE_ER keywords cannot be simultaneously specified


with the BW_T keyword.
The BOTTOM_DIELECTRIC_THICKNESS and BOTTOM_DIELECTRIC_ER keywords cannot
be specified in a conductor that is associated with a conformal layer that has a BW_T
keyword.
For conformal layers without a BW_T specification, set the BW_T value to zero to ensure
backward compatibility with existing ITF files.
If you define a BW_T value for a dielectric layer, you must set the SW_T and TW_T
values to zero.

Chapter 2: Conventional ITF Syntax Specification


Conventional
BW_T ITF Syntax Specification 2-13
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Example
The following example uses the BW_T keyword to define the bottom dielectrics shown in
Figure 2-3.
$ Gate oxide bottom conformal dielectric (closest to poly) DIELECTRIC POLY_BOT2 {
THICKNESS=0.0 IS_CONFORMAL ASSOCIATED_CONDUCTOR=POLY SW_T=0 TW_T=0 BW_T=0.005 }
$ Silicon dielectric under gate oxide (farthest from poly) DIELECTRIC POLY_BOT1 {
THICKNESS=0.0 IS_CONFORMAL ASSOCIATED_CONDUCTOR=POLY SW_T=0 TW_T=0 BW_T=0.3 }

Figure 2-3 Example of BW_T Option Usage

POLY

POLY_BOT2

POLY_BOT1

See Also
DIELECTRIC

MEASURED_FROM

SW_T

TW_T

RAISED_DIFFUSION_GATE_SIDE_CONFORMAL_ER

THICKNESS

Conventional ITF Syntax Specification 2-14


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CAPACITIVE_ONLY_ETCH
Identical to the ETCH option, except that only capacitance is affected. Valid within a
CONDUCTOR block.

Syntax
CAPACITIVE_ONLY_ETCH = etch_value

Arguments

Argument Description

etch_value Absolute width adjustment for one sidewall. A positive value


shrinks the conductor; a negative value expands it.
Units: microns
Default: 0.0

Description
The CAPACITIVE_ONLY_ETCH option applies an etch value to the sidewalls of a conductor. A
positive value denotes conductor shrink; a negative value denotes conductor expansion.
The adjusted conductor width is equal to the drawn width minus twice the etch value.
Use this option instead of the ETCH option to specify that an etch operation is to be used only
for capacitance calculations.
If you use one of the ETCH options in addition to one or more ETCH_VS_WIDTH_AND_SPACING
tables, the ETCH_VS_WIDTH_AND_SPACING operations are applied first, followed by the ETCH
operation.
This option is not the same as ETCH_VS_WIDTH_AND_SPACING CAPACITIVE_ONLY.

Example
CONDUCTOR metal1 {
CAPACITIVE_ONLY_ETCH = 0.05
THICKNESS=0.66 WMIN=0.15 SMIN=0.15 RPSQ=0.078
}

See Also
ETCH

RESISTIVE_ONLY_ETCH

ETCH_VS_WIDTH_AND_SPACING

Chapter 2: Conventional ITF Syntax Specification


Conventional ITF Syntax Specification
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CONDUCTOR
Describes the properties of a conductor layer.

Syntax
CONDUCTOR conductor_name {
SMIN = min_spacing
WMIN = min_width
THICKNESS = cond_thk
[LAYER_TYPE = GATE | FIELD_POLY | DIFFUSION |TRENCH_CONTACT
BUMP | FLOATING_GATE ]
[AIR_GAP_VS_SPACING { }]
[DIELECTRIC_FILL_VS_SI_SPACING { } ]
[BOTTOM_DIELECTRIC_THICKNESS = b_diel_thk
BOTTOM_DIELECTRIC_ER = b_diel_er]
[BOTTOM_THICKNESS_VS_SI_WIDTH { }]
[T0 = nominal_temp]
[CRT1 = lin_coeff | CRT2 = quad_coeff
| CRT1 = lin_coeff CRT2 = quad_coeff | CRT_VS_SI_WIDTH { }]
[DENSITY_BOX_WEIGHTING_FACTOR { }]
[THICKNESS_VS_DENSITY { }]
[DEVICE_TYPE { }]
[DROP_FACTOR = value]
[ETCH = value
| CAPACITIVE_ONLY_ETCH = value | RESISTIVE_ONLY_ETCH = value]
[ETCH_VS_WIDTH_AND_SPACING { }]
[FILL_RATIO = fill_ratio_value
FILL_WIDTH = fill_width_value
FILL_SPACING = fill_spacing_value
FILL_TYPE = GROUNDED | FLOATING ]
[GATE_TO_CONTACT_SMIN = value]
[GATE_TO_DIFFUSION_CAP { }]
[ILD_VS_WIDTH_AND_SPACING { }]
[IS_PLANAR]
[MEASURED_FROM = dielectric_name | TOP_OF_CHIP]
[POLYNOMIAL_BASED_THICKNESS_VARIATION { }]
[RAISED_DIFFUSION_ETCH = rd_distance
RAISED_DIFFUSION_THICKNESS = rd_thickness
RAISED_DIFFUSION_TO_GATE_SMIN = rd_spacing
[RAISED_DIFFUSION_GATE_SIDE_CONFORMAL_ER = rd_er]]
[RPSQ = rpsq_value
| RHO = rho_value
| RPSQ_VS_SI_WIDTH { }
| RPSQ_VS_WIDTH_AND_SPACING { }
| RHO_VS_SI_WIDTH_AND_THICKNESS { }
| RHO_VS_WIDTH_AND_SPACING { }]
[SIDE_TANGENT = value]
[THICKNESS_VS_WIDTH_AND_SPACING { }]
[TVF_ADJUSTMENT_TABLES { }]
[FLOATING_GATE_TO_DIFFUSION_CONTACT_CAP { }]
}

Conventional ITF Syntax Specification 2-16


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Arguments

Argument Description

conductor_name Name of the conductor layer

dielectric_name Name of a dielectric layer whose top surface is a reference height

SMIN = min_spacing Minimum spacing between two geometries on this layer


Units: microns

WMIN = min_width Minimum width of a geometry on this layer


Units: microns

THICKNESS = cond_thk Thickness of the layer (minimum value is 0.001 micron)


Units: microns

BOTTOM_DIELECTRIC_THICKN Thickness of the bottom dielectric layer


ESS = b_diel_thk Units: microns

BOTTOM_DIELECTRIC_ER = Relative permittivity of the bottom dielectric layer


b_diel_er

T0 = nominal_temp Nominal temperature


Units: degrees Celsius
Default: temperature specified by GLOBAL_TEMPERATURE

CRT1 = lin_coeff Layer-specific linear temperature coefficient


Default: 0

CRT2 = quad_coeff Layer-specific quadratic temperature coefficient


Default: 0

FILL_RATIO = Ratio of metal fill coverage


fill_ratio_value

FILL_WIDTH = Average width of metal fill objects


fill_width_value Units: microns

FILL_SPACING = Average lateral spacing between signal nets and metal fill objects
fill_spacing_value Units: microns

Chapter 2: Conventional ITF Syntax Specification


Conventional
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Argument Description

RPSQ = rpsq_value Resistance per square of the conducting layer


Units: ohms/square
Default: 0

RHO = rho_value Bulk resistivity of the conductor layer


Units: ohms-micron

Description
The CONDUCTOR statement describes the properties of a conductor layer such as minimum
width, minimum spacing, thickness, resistivity, and process variation.

Example
The following example shows a simple CONDUCTOR statement for a metal layer.
CONDUCTOR M1 { THICKNESS=0.8 WMIN=0.5 SMIN=0.45 RPSQ=0.041 }

Conventional ITF Syntax Specification 2-18


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CRT_VS_AREA
Specifies the temperature coefficients of resistance as a function of via area. Valid within a
VIA block.

Syntax
CRT_VS_AREA {
(area_1, crt1_1, crt2_1)
(area_2, crt1_2, crt2_2)

(area_n, crt1_n, crt2_n)
}

Arguments

Argument Description

area_1 area_n Via areas specified in increasing order


Units: square microns

crt1_1 crt1_n Linear temperature coefficients for corresponding via sizes

crt2_1 crt2_n Quadratic temperature coefficients for corresponding via sizes

Description
Use the CRT_VS_AREA option within a VIA block to specify the temperature coefficients of
resistance as a function of via area. There is no limit to the number of entries you can
specify. You cannot specify the CRT_VS_AREA option with either the CRT1 or CRT2 options in
the same VIA block.
When the actual via area does not exactly equal any of the area entries in the CRT_VS_AREA
table, CRT1 and CRT2 are determined by the following methods:
If the actual via size is less than the smallest area entry in the CRT_VS_AREA table, the
CRT values are set to the corresponding CRT1 and CRT2 entries of the smallest area
entry; no extrapolation is performed.
If the actual via size falls between two area entries in the CRT_VS_AREA table, CRT1 and
CRT2 are calculated by linear interpolation.
If the actual area is greater than the largest area entry in the CRT_VS_AREA table, the CRT
values are set to the corresponding CRT1 and CRT2 entries of the largest area entry; no
extrapolation is performed.

Chapter 2: Conventional ITF Syntax Specification


Conventional
CRT_VS_AREA ITF Syntax Specification 2-19
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Example
CRT_VS_AREA {
(0.002025, 9.04E-04, 4.74E-07)
(0.005265, 1.18E-03, 8.02E-07)
}

See Also
CRT1, CRT2, and T0

VIA

Conventional ITF Syntax Specification 2-20


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CRT_VS_SI_WIDTH
Specifies CRT-based temperature derating for different conductor widths. Valid within a
CONDUCTOR block.

Syntax
CRT_VS_SI_WIDTH {
(siw_1, crt1_1, crt2_1)
(siw_2, crt1_2, crt2_2)

(siw_n, crt1_n, crt2_n)
}

Arguments

Argument Description

siw_1 siw_n Post-etch conductor widths


Units: microns

crt1_1 crt1_n Linear temperature coefficients for corresponding conductor


widths

crt2_1 crt2_n Quadratic temperature coefficients for corresponding conductor


widths

Description
You can use a CRT_VS_SI_WIDTH table within a CONDUCTOR block to specify the CRT-based
temperature derating for different conductor widths.
When the actual conductor width does not exactly equal any of the siw entries in the
CRT_VS_SI_WIDTH table, then CRT1 and CRT2 are determined by the following methods:

If the actual conductor width is less than the smallest siw entry in the CRT_VS_SI_WIDTH
table, the CRT values are set to the corresponding crt1 and crt2 entries of the smallest
siw entry; no extrapolation is performed.

If the actual conductor width falls between two siw entries in the CRT_VS_SI_WIDTH
table, CRT1 and CRT2 are calculated by linear interpolation.
If the actual conductor width is greater than the largest siw entry in the
CRT_VS_SI_WIDTH table, the CRT values are set to the corresponding crt1 and crt2
entries of the largest siw entry; no extrapolation is performed.

Chapter 2: Conventional ITF Syntax Specification


Conventional ITF Syntax Specification
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If the CRT_VS_SI_WIDTH statement is used with the RPSQ_VS_SI_WIDTH statement, the width
index should be the same for both statements.

Example
CONDUCTOR MET1 {
THICKNESS=0.6 WMIN=0.34 SMIN=0.40
CRT_VS_SI_WIDTH {
(0.34, 0.001, 0.000)
(0.40, 0.001, 0.001)
(0.823, 0.002, 0.001)
(2.0, 0.003, 0.001)
}
}

See Also
CONDUCTOR

CRT1, CRT2, and T0

RPSQ_VS_SI_WIDTH

Conventional ITF Syntax Specification 2-22


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CRT1, CRT2, and T0


Defines parameters for temperature-dependent resistance models. Valid in CONDUCTOR, VIA,
and TSV blocks.

Syntax
CRT1 = lin_coeff
CRT2 = quad_coeff
T0 = nominal_temp

Arguments

Argument Description

CRT1 = lin_coeff Linear temperature coefficient for the layer. Specified on a per-
layer basis.
Default: 0

CRT2 = quad_coeff Quadratic temperature coefficient for the layer. Specified on a


per-layer basis.
Default: 0

T0 = nominal_temp Nominal temperature for the layer


Units: degrees Celsius
Default: Temperature specified by the GLOBAL_TEMPERATURE
keyword.

Description
The CRT1, CRT2, and T0 options define temperature-dependent resistance models for
conducting layers and vias. The resistances are modeled similar to the way they are
modeled in SPICE, by using the following equation:

2
R = R0 [ CRT1 ( T T0 ) + CRT2 ( T T0 ) + 1 ]

In this equation,
R is the modeled resistance at the operating temperature T
R0 is the resistance value at the nominal temperature T0
CRT1 and CRT2 are the linear and quadratic temperature coefficients

Chapter 2: Conventional ITF Syntax Specification


Conventional
CRT1, CRT2, ITF
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T0 Specification 2-23
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The modeled resistance R exactly equals the nominal resistance (R0) if T=T0 or if CRT1 and
CRT2 both equal 0.
If either CRT1 or CTR1 is nonzero for a layer, a nominal temperature specification is
required for that layer. Set a global value for nominal temperature with the
GLOBAL_TEMPERATURE option at the beginning of the ITF file. If you set a nominal
temperature both globally and for an individual layer, the layer nominal temperature
overrides the global setting.

Example
TECHNOLOGY = example_tech
GLOBAL_TEMPERATURE = 31.0
DIELECTRIC IMD2 { THICKNESS=2.0 ER=3.9 }
CONDUCTOR metal2 {
CRT1=3.00e-3 CRT2=2.0e-7
THICKNESS = 0.6 SMIN=0.5 WMIN=0.5 RPSQ = 0.06
}
DIELECTRIC IMD1 { THICKNESS=1.9 ER=4.9 }
CONDUCTOR metal1 {
CRT1=3.50e-3 CRT2=2.5e-7
THICKNESS = 0.5 SMIN = 0.4 WMIN=0.4 RPSQ = 0.08
}
DIELECTRIC FOX { THICKNESS=1.0 ER=3.9 }
VIA via1 {
FROM=metal1 TO=metal2 AREA=1 RPV=1
CRT1=2.5e-3 CRT2=1e-6 T0=29
}

See Also
GLOBAL_TEMPERATURE

Conventional ITF Syntax Specification 2-24


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DAMAGE_ER
Defines the relative permittivity of a dielectric damage layer. Valid within a DIELECTRIC
block.

Syntax
DAMAGE_ER = relative_permittivity

Arguments

Argument Description

relative_permittivity Relative permittivity

Description
Use the DAMAGE_ER and DAMAGE_THICKNESS options together to specify the relative
permittivity of a damage layer. These options cannot be used for conformal dielectric layers.

See Also
DAMAGE_THICKNESS

DIELECTRIC

Chapter 2: Conventional ITF Syntax Specification


Conventional
DAMAGE_ERITF Syntax Specification 2-25
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DAMAGE_THICKNESS
Defines the thickness of a dielectric damage layer. Valid within a DIELECTRIC block.

Syntax
DAMAGE_THICKNESS = thickness

Arguments

Argument Description

thickness Thickness of the damage layer on the surface of the dielectric


Units: microns

Description
Use the DAMAGE_ER and DAMAGE_THICKNESS options together to specify the relative
permittivity of a damage layer. These options cannot be used for conformal dielectric layers.

See Also
DAMAGE_ER

DIELECTRIC

Conventional ITF Syntax Specification 2-26


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DENSITY_BOX_WEIGHTING_FACTOR
Specifies a density box weighting factor. Valid within a CONDUCTOR block.

Syntax
DENSITY_BOX_WEIGHTING_FACTOR {(S1 W1) (S2 W2) (S3 W3) (S4 W4) (S5 W5)}

Arguments

Argument Description

Sn The size of the density box. Up to five entries are allowed.


S1, S2, S3, S4 and S5 are integers between 0 and 500, ordered
from smallest to largest. The density box size is SxS.
Units: microns

Wn The weighting factor specified as a floating-point number. Must


be within the range -10 < W < 10. If W is set to 0, that pair (Sn Wn)
is ignored.

Description
This option is to be used with the THICKNESS_VS_DENSITY option when specifying a single
or multiple box method for effective density calculation.
If you do not specify a DENSITY_BOX_WEIGHTING_FACTOR option, the default density box
size of 50 m is used with the weighting factor of unity. In other words, not specifying this
option has the same effect as the following statement:
DENSITY_BOX_WEIGHTING_FACTOR {(50 1)}

Examples
CONDUCTOR metal3 {
SMIN= 0.35 WMIN=0.42 THICKNESS=0.53 RPSQ=0.061
THICKNESS_VS_DENSITY {(0.1 -0.1)(0.2 0.1)(0.3 0.15)(0.5 0.3)}
DENSITY_BOX_WEIGHTING_FACTOR
{ (10 1)(20 0.23)(30 0.29)(40 0.08)(50 0.12) }
}

See Also

THICKNESS_VS_DENSITY

Chapter 2: Conventional ITF Syntax Specification


Conventional ITF Syntax Specification
DENSITY_BOX_WEIGHTING_FACTOR 2-27
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DEVICE_TYPE
Identifies conductor layers that compose a specified device. Valid within a CONDUCTOR block.

Syntax
DEVICE_TYPE { [device_type_name_1] [device_type_name_2] | ALL | NONE }

Arguments

Argument Description

device_type_name Applies the conductor layer to the specified device type

ALL Applies the conductor layer to all device types

NONE Does not apply the conductor layer any device types

Description
The DEVICE_TYPE keyword identifies conductor layers that compose a specified device.
The device_type_name arguments are user-defined names. To include the conductor in all
device types, specify the ALL keyword. Conversely, if the conductor does not exist in or near
any device in the process, specify the NONE keyword; this is useful for a conductor
corresponding to a capacitor or resistor that is never in or near a device.
The DEVICE_TYPE option has the following constraints:
The DEVICE_TYPE designation can only be included in conductors with GATE,
FIELD_POLY, TRENCH_CONTACT, or DIFFUSION layer types.

Only one DEVICE_TYPE option is allowed for each conductor.


A device type name must adhere to the same syntax rules as a conductor name, via
name, or dielectric name in the ITF file.
Exactly one conductor with a LAYER_TYPE=GATE statement and one conductor with a
LAYER_TYPE=DIFFUSION statement must be specified for each defined device type
name.
Conductors that have no specified device type but have a LAYER_TYPE=GATE statement
are applied to all device types, therefore no other conductors with a LAYER_TYPE=GATE
statement are allowed to exist in the process if a DEVICE_TYPE statement appears
anywhere in the ITF file. An equivalent rule is applied to conductors that have no device
type but do have a LAYER_TYPE=DIFFUSION statement.

Conventional ITF Syntax Specification 2-28


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Any number of conductors that have a LAYER_TYPE=FIELD_POLY or


LAYER_TYPE=TRENCH_CONTACT statement can be associated with a single device type
name.
DEVICE_TYPE { NONE } can only be applied to conductors with
LAYER_TYPE=FIELD_POLY or LAYER_TYPE=TRENCH_CONTACT statements.

Example
The following example shows part of an ITF file that uses the DEVICE_TYPE option.
CONDUCTOR TC_RSD { DEVICE_TYPE { N_RSD P_RSD } }
CONDUCTOR TC { DEVICE_TYPE { N_NO_RSD P_NO_RSD } }

CONDUCTOR FPOLY_N { DEVICE_TYPE { N_RSD N_NO_RSD } }
CONDUCTOR FPOLY_P { DEVICE_TYPE { P_RSD P_NO_RSD } }
CONDUCTOR GPOLY_N { DEVICE_TYPE { N_RSD N_NO_RSD } }
CONDUCTOR GPOLY_P { DEVICE_TYPE { P_RSD P_NO_RSD } }

CONDUCTOR DIFF_NO_RSD { DEVICE_TYPE { N_NO_RSD P_NO_RSD } }
CONDUCTOR DIFF_N_RSD { DEVICE_TYPE { N_RSD } }
CONDUCTOR DIFF_P_RSD { DEVICE_TYPE { P_RSD } }

See Also
CONDUCTOR

LAYER_TYPE

Chapter 2: Conventional ITF Syntax Specification


Conventional
DEVICE_TYPE ITF Syntax Specification 2-29
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DIELECTRIC
Describes the properties of a dielectric layer.

Syntax
DIELECTRIC dielectric_name {
ER = er_value
[ER_VS_SI_SPACING {
( SI_SPACING1, ER1 )
( SI_SPACING2, ER2 )

( SI_SPACINGn, ERn ) } ]
THICKNESS = diel_thickness
[MEASURED_FROM = meas_layer | TOP_OF_CHIP
[SW_T = sw_thick] [TW_T = tw_thick]][BW_T = bw_thick]
[IS_CONFORMAL [ASSOCIATED_CONDUCTOR = conductor_name
[SPACER_ER_VS_WIDTH_AND_SPACING {...} ]]]
[DAMAGE_THICKNESS = damg_thick DAMAGE_ER = damg_er]
}

Arguments

Argument Description

dielectric_name Name of the dielectric layer

er_value Relative permittivity of the layer

diel_thickness Thickness of the layer


Units: microns

meas_layer Name of the reference dielectric layer

sw_thick Sidewall thickness


Units: microns

tw_thick Top wall thickness


Units: microns

bw_thick Bottom wall thickness


Units: microns

conductor_name Name of the associated conductor

Conventional ITF Syntax Specification 2-30


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Argument Description

damg_thick Damage layer thickness


Units: microns

damg_er Relative permittivity of the damage layer

Description
The DIELECTRIC statement describes a dielectric layer above or below a conductor layer.

Example
The following example describes a dielectric layer named FOX with a thickness of 0.3 m
and a relative permittivity of 3.9.
DIELECTRIC FOX { THICKNESS=0.3 ER=3.9 }

Chapter 2: Conventional ITF Syntax Specification


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DIELECTRIC ITF Syntax Specification 2-31
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DIELECTRIC_FILL_VS_SI_SPACING
Defines parameters of dielectric fill features. Valid within a CONDUCTOR block.

Syntax
DIELECTRIC_FILL_VS_SI_SPACING {
SPACINGS { s1 s2 .. sn }
WIDTHS { w(s1) w(s2) w(sn) }
THICKNESSES { t(s1) t(s2) t(sn) }
BOTTOM_HEIGHTS { h(s1) h(s2) h(sn) }
SIDE_TANGENTS { a(s1) a(s2) a(sn) }
ERS { e(s1) e(s2) e(sn) }
}

Arguments

Argument Description

s1 s2 sn Spacing values between the two conductors, in ascending order


Units: microns

w(s1) w(s2) w(sn) Width of the dielectric fill region


Units: microns

t(s1) t(s2) t(sn) Thickness of the dielectric fill region


Units: microns

h(s1) h(s2) h(sn) Bottm height: offset of the bottom of the dielectric fill region with
respect to the drawn bottom height of the conductor. A negative
value indicates that the dielectric fill region is lower than the
conductor bottom height
Units: microns

a(s1) a(s2) a(sn) Side tangent of the dielectric fill region (representing the sidewall
angle)
Units: none

e(s1) e(s2) e(sn) Relative dielectric constant of the dielectric fill region
Units: none

Description
The DIELECTRIC_FILL_VS_SI_SPACING command defines the parameters of dielectric fill.
Dielectric fill features typically have very low dielectric constants and are inserted to reduce

Conventional ITF Syntax Specification 2-32


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the coupling capacitance between upper-layer conductors. Figure 2-4 shows the geometry
of a dielectric fill region.
The side tangent value represents the angular shift from vertical of the side of the dielectric
fill feature. The use of side tangent values is similar to the SIDE_TANGENT option used at the
top level of the CONDUCTOR definition. A positive side tangent results in a top width that is
larger than the center width, while a negative value results in a top width that is smaller than
the center width. The feature in Figure 2-4 results from a negative side tangent value.
Figure 2-4 Dielectric Fill Geometry and Parameters

Dielectric fill region

Conductor
Width

Thickness

Bottom height

Spacing

Dielectric fill is inserted whenever the spacing between conductor features falls within the
range specified in the SPACINGS list. The minimum allowed spacing value is the SMIN value
of the conducting layer and the maximum value is 5 times the SMIN value.
The geometry of a specific dielectric fill feature is determined as follows:
If the actual conductor spacing is smaller than the smallest value in the SPACINGS list, no
dielectric fill is inserted.
If the actual conductor spacing is larger than the largest value in the SPACINGS list,
dielectric fill is inserted using the parameters for the largest spacing value in the
SPACINGS list.

If the actual conductor spacing falls between two spacing values in the SPACINGS list,
linear interpolation is applied to calculate the width, thickness, and bottom height.

Chapter 2: Conventional ITF Syntax Specification


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If the actual conductor spacing falls between two spacing values in the SPACINGS list, the
dielectric constant is not interpolated, but instead is set equal to the ERS value that
corresponds to the smaller of the two spacing values.

For each conductor spacing value in the SPACINGS list, you must provide one value of each
of the other parameters. In other words, the number of entries in each of the parameter lists
must be equal. Lists of values are interpreted on a sequential basis, independent of any
carriage returns or other hidden characters.

Example
In the following example, dielectric fill is inserted between features in conductor layer M1
whenever the spacing between conductor features is greater than 0.035 microns.
CONDUCTOR M1 {
THICKNESS=0.08
CRT1=1E-03 CRT2=2E-07
SIDE_TANGENT=0.09
POYNOMIAL_BASED_THICKNESS_VARIATION { }
ETCH_VS_WIDTH_AND_SPACING { }
DIELECTRIC_FILL_VS_SI_SPACING {
SPACINGS { 0.035 .07 .24 }
WIDTHS { 0.03 0.06 0.12 }
THICKNESSES { 0.22 0.44 0.88 }
BOTTOM_HEIGHTS { 0.008 0.016 0.032 }
SIDE_TANGENTS { 0.09 0.095 0.15 }
ERS { 2.6 2.7 2.8 }
}

See Also
CONDUCTOR

SIDE_TANGENT

SMIN

Conventional ITF Syntax Specification 2-34


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DROP_FACTOR
Specifies the decrease in base height of all upper conductors when the bottom conductor is
not present in the given layout area. Valid within a CONDUCTOR block.

Syntax
DROP_FACTOR = drop_value

Arguments

Argument Description

drop_value Conductor base height decrease


Units: microns

Description
The DROP_FACTOR option specifies the decrease in base height of upper-level conductors
when a lower-level conductor is not present. Use the DROP_FACTOR option in the CONDUCTOR
block for the lower-level conductor. You can specify a drop factor for no more than four
conductors.
Figure 2-5 shows the effect of setting the drop factor to 0.2 microns for lower-level conductor
M1. The base height of upper-level conductor M2 drops by 0.2 microns when M1 is not
present. A lateral gap is maintained between the dropped part of the upper-level conductor
and the lower-level conductor. This lateral gap is 0.5 um by default, but can be modified by
using the DROP_FACTOR_LATERAL_SPACING statement.
Figure 2-5 Drop Factor Example

M2

0.2 m 0.5 m
M1

SUBSTRATE

See Also
DROP_FACTOR_LATERAL_SPACING

Chapter 2: Conventional ITF Syntax Specification


Conventional
DROP_FACTOR ITF Syntax Specification 2-35
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DROP_FACTOR_LATERAL_SPACING
Specifies a constant lateral spacing value to use in conjunction with conductor drop factors.

Syntax
DROP_FACTOR_LATERAL_SPACING = value

Arguments

Argument Description

value Constant value between 0.5 and 4.0


Units: microns
Default: 0.5

Description
The DROP_FACTOR_LATERAL_SPACING statement specifies a constant lateral spacing value
used between a lower-level conductor that has a DROP_FACTOR statement and the dropped
part of an upper-level conductor.
Specify the DROP_FACTOR_LATERAL_SPACING statement in the global parameters section
after the TECHNOLOGY statement.

Examples
This example specifies a lateral spacing of 0.6 m for all conductors when dropped.
TECHNOLOGY = example_tech
DROP_FACTOR_LATERAL_SPACING = 0.6

See Also
DROP_FACTOR

Conventional ITF Syntax Specification 2-36


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ER
Specifies the relative permittivity of a dielectric. Valid within a DIELECTRIC block.

Syntax
ER = permittivity

Arguments

Argument Description

permittivity Relative permittivity of a dielectric layer

Description
The ER parameter specifies the relative permittivity, or dielectric constant, of a dielectric
layer.

Examples
DIELECTRIC D2 {THICKNESS = 1.2 ER = 3.9}

See Also
DIELECTRIC

Chapter 2: Conventional ITF Syntax Specification


Conventional
ER ITF Syntax Specification 2-37
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ER_VS_SI_SPACING
Specifies double-pattern modeling. Valid within a DIELECTRIC block.

Syntax
ER_VS_SI_SPACING {
( SI_SPACING1, ER1 )
( SI_SPACING2, ER2 )

( SI_SPACINGn, ERn )
}

Arguments

Argument Description

SI_SPACING Silicon spacing value

ER Relative permittivity of the dielectric

Description
The ER_VS_SI_SPACING option models variable dielectric constants in the ITF file. One
application is for modeling of capacitance variation due to double patterning processes. If
two conductors move closer together or farther apart, the change in capacitance can be
modeled by varying the dielectric constant.

Example
A dielectric layer might have the following relative permittivity definition:
ER = 5.3
ER_VS_SI_SPACING {
( 0.020, 7.2 )
( 0.050, 6.4 )
( 0.070, 5.3 )
}

The resulting permittivity values are shown in Table 2-2.


Table 2-2 Relative Permittivity for Different Spacing Values

Post-Etch Spacing Relative Permittivity

0 to 0.02 7.2

0.02 to 0.05 interpolated between 7.2 and 6.4

Conventional ITF Syntax Specification 2-38


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Table 2-2 Relative Permittivity for Different Spacing Values (continued)

Post-Etch Spacing Relative Permittivity

0.05 to 0.07 interpolated between 6.4 and 5.3

greater than 0.07 5.3

Chapter 2: Conventional ITF Syntax Specification


Conventional ITF Syntax Specification
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ETCH
Specifies a width adjustment to model layer etch effects. Valid within a CONDUCTOR block.

Syntax
ETCH = etch_value

Arguments

Argument Description

etch_value Absolute width adjustment for one sidewall. A positive value


shrinks the conductor; a negative value expands it.
Units: microns

Description
The ETCH option applies an etch value to each of the sidewalls of a conductor. A positive
argument denotes conductor shrink; a negative value denotes conductor expansion. The
adjusted conductor width is equal to the drawn width minus twice the etch value. The new
conductor width is determined before resistance is calculated (for example by applying the
RPSQ keyword).

You can specify that an etch operation is to be used for only capacitance calculations by
using the CAPACITIVE_ONLY_ETCH option instead of the ETCH option. Similarly, you can
specify that an etch operation is to be used for only resistance calculations by using the
RESISTIVE_ONLY_ETCH option instead of the ETCH option.

If you use one of the ETCH options in addition to one or more ETCH_VS_WIDTH_AND_SPACING
tables, the ETCH_VS_WIDTH_AND_SPACING operations are applied first, followed by the ETCH
operation.

Example
CONDUCTOR M1 {
THICKNESS=0.6 WMIN=0.3 SMIN=0.3 RPSQ=0.05 ETCH=0.05
}

See Also
CAPACITIVE_ONLY_ETCH

RESISTIVE_ONLY_ETCH

ETCH_VS_WIDTH_AND_SPACING

Conventional ITF Syntax Specification 2-40


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ETCH_VS_CONTACT_AND_GATE_SPACINGS
Specifies etch values as a function of contact width and spacing between the gate and
contact. Valid within a VIA block.

Syntax
ETCH_VS_CONTACT_AND_GATE_SPACINGS CAPACITIVE_ONLY {
CONTACT_TO_CONTACT_SPACING { c1 c2 c3 }
GATE_TO_CONTACT_SPACING { s1 s2 s3 }
VALUES { v(c1,s1) v(c2,s1)
v(c1,s2) v(c2,s2)

}
}

Arguments

Argument Description

CAPACITIVE_ONLY Applies etch effect to capacitance only

c1 c2 c3 Contact to contact spacing values specified in ascending order


Units: microns

s1 s2 s3 Gate to contact spacing values specified in ascending order


Units: microns

v(c1,s1) v(c2,s2) Etch values of corresponding contact and gate spacing pairs
Units: microns

Description
The actual size of contacts in silicon might be different than the sizes drawn in layout. To
account for this difference during parasitic extraction, the VIA statement allows a contact
bias to be specified as a function of contact width and gate-to-contact spacing.
A positive etch value models a shrinking contact, and a negative etch value indicates that
the contact size is growing.
The resistance is defined as a post-etch value in the RPV option for a via definition.
Therefore, the contact etch only affects the estimated capacitance.

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Conventional ITF Syntax Specification
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Examples
The following VIA definition does not have a contact bias:
VIA DiffCont {
FROM=diff TO=metal1 AREA=0.003 RPV=15
CRT1=6.56e-04 CRT2=-5.643e-0
}

The VIA definition can be extended to include a contact bias 2-D table, or etch table, as a
function of contact-to-contact and gate-to-contact spacings. For example,
VIA DiffCont {
FROM=diff TO=metal1 AREA=0.003 RPV=15
CRT1=6.56e-04 CRT2=-5.643e-0
ETCH_VS_CONTACT_AND_GATE_SPACINGS CAPACITIVE_ONLY {
CONTACT_TO_CONTACT_SPACINGS {0.1 0.2 0.3}
GATE_TO_CONTACT_SPACINGS {0.05 0.1 0.15}
VALUES {0.005 0.006 0.007
0.004 0.005 0.006
0.003 0.004 0.005}
}
}

Conventional ITF Syntax Specification 2-42


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ETCH_VS_WIDTH_AND_LENGTH
Specifies different via etch values for the length and width sides of nonsquare vias. Valid
within a VIA block.

Syntax
ETCH_VS_WIDTH_AND_LENGTH CAPACITIVE_ONLY {
LENGTHS { l1 l2 lm }
WIDTHS { w1 w2 wn }
VALUES { (v_l1,v_w1) (v_l2,v_w1) (v_lm,v_w1)
(v_l1,v_w2) (v_l2,v_w2) (v_lm,v_w2)

(v_l1,v_wn) (v_l2,v_wn) (v_lm,v_wn)
}
}

Arguments

Argument Description

CAPACITIVE_ONLY Applies etch effect to capacitance only

l1 l2 lm Via lengths specified in ascending order


Units: microns

w1 w2 wn Via widths specified in ascending order


Units: microns

(v_l1,v_wn) Etch values of corresponding via lengths and widths


(v_lm, v_wn) Units: microns

Description
Specify the ETCH_VS_WIDTH_AND_LENGTH option within a VIA statement to apply different via
etch values to the length and width sides of nonsquare vias.
The specified length and width values are used as indexes for the two-dimensional table of
etch values. Each combination of length lm and width wn has a corresponding pair of etch
values (v_lm, v_wn), where v_lm represents the etch value for the length, and v_wn
represents the etch value for the width.
Note the following restrictions when using an ETCH_VS_WIDTH_AND_LENGTH table:
When the width is greater than the length, the corresponding etch values are n.

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Do not use the ETCH_VS_WIDTH_AND_LENGTH option to describe nonsquare diffusion


contacts.
Do not specify the ETCH_VS_WIDTH_AND_LENGTH option together with the
ETCH_VS_CONTACT_AND_GATE_SPACINGS option in the same VIA statement.

You can use ETCH_VS_WIDTH_AND_LENGTH together with the constant etch


CAPACITIVE_ONLY_ETCH option.

Examples
In the following example, the etch entry for length=0.045 and width=0.115 is set to
(VL,VW)=(0.000, 0.000) because the parameter combination is invalid when the length is
less than the width.
VIA via1{ FROM=M8 TO=M9 AREA=0.005 RPV=5
ETCH_VS_WIDTH_AND_LENGTH CAPACITIVE_ONLY {
LENGTHS { 0.045 0.115 0.200 }
WIDTHS { 0.045 0.115 }
VALUES { (0.015, 0.015) (0.002, 0.002) (0.003 0.001)
(0.000, 0.000) (0.015, 0.015) (0.005 0.002)
}
}
}

See Also
ETCH_VS_CONTACT_AND_GATE_SPACINGS

VIA

Conventional ITF Syntax Specification 2-44


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ETCH_VS_WIDTH_AND_SPACING
Specifies conductor etch values with respect to conductor width and spacing. Valid within a
CONDUCTOR block.

Syntax
ETCH_VS_WIDTH_AND_SPACING {
[RESISTIVE_ONLY | CAPACITIVE_ONLY | ETCH_FROM_TOP]
[PARALLEL_TO_REFERENCE | PERPENDICULAR_TO_REFERENCE | PARALLEL_TO_GATE]
[NUMBER_OF_MASKS = num_masks]
[MASKS(i,j)] {
SPACINGS { s1 s2 sm }
WIDTHS { w1 w1 wn }
VALUES { v(s1,w1) v(s2,w1) v(sm,w1)
v(s1,w2) v(s2,w2) v(sm,w2)

v(s1,wn) v(s2,wn) v(sm,wn)
}
}

Arguments

Argument Description

RESISTIVE_ONLY Applies etch effect to resistance only

CAPACITIVE_ONLY Applies etch effect to capacitance only

ETCH_FROM_TOP Specifies a trapezoidal cross section (allows the etch to affect


sidewall angle)

PARALLEL_TO_REFERENCE Applies etch effect to wires that are parallel to the reference
direction

PERPENDICULAR_TO_REFERENCE Applies etch effect to wires that are perpendicular to the


reference direction

PARALLEL_TO_GATE Applies etch on border edges that are parallel to the device
gate. Use this option only for conductor layers where the
LAYER_TYPE option is set to DIFFUSION.

NUMBER_OF_MASKS = In a multiple mask patterning flow, the number of different mask


num_masks colors.

MASKS In a multiple mask patterning flow, the two mask numbers to


which the VALUES table applies for modeling misalignment
between the masks

Chapter 2: Conventional ITF Syntax Specification


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Argument Description

SPACINGS {} Spacing values specified in ascending order


Units: microns

WIDTHS {} Width values


Units: microns

VALUES {} Etch values


Units: microns

Description
The ETCH_VS_WIDTH_AND_SPACING keyword models fabricated pattern shapes. Etch and
lithography processing effects can cause the amount of etch to vary with the width of the
conductor and its spacing to neighboring features. The etch effect might be different on two
edges of the same conductor if the spacing to the nearest neighbor is different on the two
sides. This option must be used within a CONDUCTOR section.
To model processes with multiple etch steps, use multiple ETCH_VS_WIDTH_AND_SPACING
options. Specify them in the same order as the corresponding etch processes. Note that
each occurrence of the ETCH_VS_WIDTH_AND_SPACING option might include more than one
table if a multicolor mask flow is involved.
For each ETCH_VS_WIDTH_AND_SPACING table, you must specify the SPACINGS and WIDTHS
index vectors and the VALUES matrix; these three items can appear in any order. Positive
etch values cause structure widths to decrease, while negative etch values cause structure
widths to increase.
You can apply the ETCH_VS_WIDTH_AND_SPACING option to both capacitance and
resistance.

Examples

Single and Multiple Tables


The following example uses a single table:
CONDUCTOR metal2 {
THICKNESS=0.65 WMIN=0.65 SMIN=0.50 RPSQ=0.62 ETCH=0.05
ETCH_VS_WIDTH_AND_SPACING RESISTIVE_ONLY {
SPACINGS { 0.5 0.67 0.8 }
WIDTHS { 0.65 0.9 }
VALUES { 0.1 0.05 -0.05
0.15 0.10 -0.10 }
}
}

Conventional ITF Syntax Specification 2-46


Interconnect Technology Format Specification Version 2015.06

The following example uses multiple tables:


CONDUCTOR M2 {
THICKNESS=0.132 WMIN=0.050 SMIN=0.050 SIDE_TANGENT=0.06992
ETCH_VS_WIDTH_AND_SPACING {
*First etch_vs_width_and_spacing table (pre ADI table)
SPACINGS { 0.050 0.100 }
WIDTHS { 0.050 1.0 }
VALUES {-0.0027 0.0034
0.0003 0.0052 }
}
ETCH_VS_WIDTH_AND_SPACING {
*Second etch_vs_width_and_spacing table (post ADI table)
SPACINGS { 0.045 0.150 }
WIDTHS { 0.045 2.0 }
VALUES {-0.002 0.0014
0.004 -0.003 }
}
}

Etch From Top


The ETCH_FROM_TOP keyword affects how the etch is applied to the structure sidewalls.
Using this keyword results in a trapezoidal cross section. Figure 2-6 shows the effects of
using negative and positive etch values along with the ETCH_FROM_TOP keyword.
Because the amount of etch specified by the ETCH_VS_WIDTH_AND_SPACING option is based
on the spacing to a neighboring structure, different sides of a conductor can be exposed to
different spacings and therefore can end up with different sidewall angles after the etch.
However, the center width remains constant.
The ETCH_FROM_TOP keyword takes precedence over any SIDE_TANGENT keywords used in
a conductor definition.
The resistance of a conductor is not changed by application of the ETCH_FROM_TOP keyword,
because the cross-sectional area of the conductor does not change. Therefore, the
ETCH_FROM_TOP keyword affects only capacitance by default. You cannot use the
RESISTIVE_ONLY or CAPACITIVE_ONLY keywords with the ETCH_FROM_TOP keyword.

Chapter 2: Conventional ITF Syntax Specification


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ETCH_VS_WIDTH_AND_SPACING 2-47
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Figure 2-6 Effect of the ETCH_FROM_TOP Keyword

Negative etch value Positive etch value

W_center W_center

In the following example, a conductor of width 1 um spaced 0.5 um away from its neighbor
on the left receives an etch of +0.05 um on the left edge. If that conductor is spaced 3 um
away from another structure on the right side, the right edge receives an etch of -0.2 um.
CONDUCTOR Metal5 {
THICKNESS=1.2 WMIN=0.3 SMIN=0.3 RPSQ = 0.62
ETCH_VS_WIDTH_AND_SPACING ETCH_FROM_TOP {
SPACINGS { 0.5 3 }
WIDTHS { 1 2 }
VALUES { 0.05 -0.2
0.1 -0.17 }
}
}

Orientation-Dependent Width
Some etch processes affect lines differently depending on the orientation of the wire.
One or more pairs of ETCH_VS_WIDTH_AND_SPACING tables can be included in each metal
conductor layer. In each pair, one table must contain the PARALLEL_TO_REFERENCE keyword
and specify the etch values for wires that are parallel to the reference direction; the other
table must contain the PERPENDICULAR_TO_REFERENCE keyword and specify the etch values
for wires that are perpendicular to the reference direction.
Note:
You cannot use the ETCH_FROM_TOP keyword with the PARALLEL_TO_REFERENCE or
PERPENDICULAR_TO_REFERENCE keyword.

Figure 2-7 shows an example of orientation-dependent width variation in which the


reference direction is vertical. The etch orientation is either parallel or perpendicular to the
reference direction.

Conventional ITF Syntax Specification 2-48


Interconnect Technology Format Specification Version 2015.06

Figure 2-7 Example of Orientation-Dependent Width Variation

The following example shows the corresponding settings in the ITF file.
REFERENCE_DIRECTION = VERTICAL

CONDUCTOR M2 {
THICKNESS =
ETCH_VS_WIDTH_AND_SPACING
PARALLEL_TO_REFERENCE {
WIDTHS {0.03} SPACINGS {0.03} VALUES {-0.015}
}
ETCH_VS_WIDTH_AND_SPACING
PERPENDICULAR_TO_REFERENCE {
WIDTHS {0.03} SPACINGS {0.03} VALUES {-0.005}
}
}
CONDUCTOR M3 {
THICKNESS =
ETCH_VS_WIDTH_AND_SPACING
PARALLEL_TO_REFERENCE {
WIDTHS {0.03} SPACINGS {0.03} VALUES {-0.015}
}
ETCH_VS_WIDTH_AND_SPACING
PERPENDICULAR_TO_REFERENCE {
WIDTHS {0.03} SPACINGS {0.03} VALUES {-0.010} }
}

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Multiple Masks
A double patterning process splits features from a single layer into two separate masks.
Printing the masks separately can achieve smaller features and spaces than a single mask.
This practice affects extraction results if one of the masks shifts with respect to the other
mask, because some features on the same layer move closer together and others move
farther apart. If more than two masks are used for a single layer, the relationships are even
further complicated.
You can use ETCH_VS_WIDTH_AND_SPACING tables to modify etch behavior based on mask
shifts. The NUMBER_OF_MASKS keyword specifies the number of masks used to pattern the
layer. The MASKS keyword names one or more mask pairs to which an etch table applies. A
mask pair format is (self mask, neighbor mask); more than one pair can be specified for the
same table. A mask ID of 0 indicates a colorless mask.
For a multiple mask process, all combinations of mask relationships must be specified. For
a two-mask process, the table for mask pair (1,1) is used when adjacent features are both
patterned by mask 1. Similarly, the table for mask pair (2,2) is used when adjacent features
are both patterned by mask 2. The table for mask pair (1,2) is used for a feature on mask 1
when its neighbor is patterned by mask 2.
For two mask pairs with the same masks in different orders, such as mask pairs (1,2) and
(2,1), the width and spacing indexes must be the same but the values can be different. If the
values are also the same, you can specify one table for both pairs.
The following example uses a two-mask process. In this example, the same etch values are
used for mask pair (1,2) and mask pair (2,1).
ETCH_VS_WIDTH_AND_SPACING
NUMBER_OF_MASKS = 2
MASKS (1,1) {
SPACINGS { 0.5 0.67 0.8 }
WIDTHS { 0.65 0.9 }
VALUES { 0.1 0.05 -0.05
0.15 0.10 -0.10 }
}
MASKS (1,2) (2,1) {
SPACINGS { 0.05 0.10 }
WIDTHS { 0.05 0.10 }
VALUES { -0.002 0.0014
0.004 -0.003 }
}
MASKS (2,2) {
SPACINGS { 0.045 0.15 }
WIDTHS { 0.045 2.0 }
VALUES { -0.002 0.0014
0.004 -0.003}
}

Conventional ITF Syntax Specification 2-50


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The following example is a table for mask ID 0 that can be optionally added to the two-mask
ETCH_VS_WIDTH_AND_SPACING block to define the behavior of noncolored geometry in the
layout:
MASKS (0,0)(0,1)(0,2)(1,0)(2,0) {
SPACINGS { 0.05 0.10 }
WIDTHS { 0.005 1.0 }
VALUES { -0.001 0.002
0.004 0.003}
}

If multiple ETCH_VS_WIDTH_AND_SPACING statements are used for the same layer, the
number of masks must be the same for each ETCH_VS_WIDTH_AND_SPACING command of
the same type (RESISTIVE_ONLY or CAPACITIVE_ONLY). For example, you could have two
CAPACITIVE_ONLY tables, each specifying two masks, and one RESISTIVE_ONLY table that
doesnt specify any masks.

See Also
CONDUCTOR

REFERENCE_DIRECTION

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FILL_RATIO
Specifies the ratio of metal fill coverage for a specified conductor. Valid within a CONDUCTOR
block.

Syntax
FILL_RATIO = ratio

Arguments

Argument Description

ratio Ratio of metal fill for a given layer

Description
The FILL_RATIO option specifies the ratio of metal fill coverage for a specified conductor.
For example, if the density of the fill is 50 percent, specify FILL_RATIO = 0.5.
You must specify FILL_RATIO when you specify the FILL_SPACING and FILL_WIDTH
options.

Examples
CONDUCTOR m1 {
THICKNESS=0.6 WMIN=0.3 SMIN=0.3
FILL_RATIO = 0.4 FILL_SPACING = 1.0 FILL_WIDTH = 2.0
}

See Also
FILL_SPACING

FILL_TYPE

FILL_WIDTH

Conventional ITF Syntax Specification 2-52


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FILL_SPACING
Specifies the average lateral space separating signal nets and metal fill objects. Valid within
a CONDUCTOR block.

Syntax
FILL_SPACING = spacing

Arguments

Argument Description

spacing The average lateral spacing


Units: microns

Description
The FILL_SPACING option specifies the average lateral space separating signal nets and
metal fill objects in microns. It is required if FILL_RATIO is specified.

Examples
CONDUCTOR m1 {
THICKNESS=0.6 WMIN=0.3 SMIN=0.3
FILL_RATIO = 0.4 FILL_SPACING = 1.0 FILL_WIDTH = 2.0
}

See Also
FILL_RATIO

FILL_TYPE

FILL_WIDTH

Chapter 2: Conventional ITF Syntax Specification


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FILL_TYPE
Specifies grounded or floating processing of lateral metal fill emulation. Valid within a
CONDUCTOR block.

Syntax
FILL_TYPE = GROUNDED | FLOATING

Arguments

Argument Description

GROUNDED (default) Treats lateral metal fill patterns defined by FILL_WIDTH and
FILL_SPACING as if they are tied to ground net.

FLOATING Treats lateral metal fill patterns defined by FILL_WIDTH and


FILL_SPACING as if they are floating.

Description
FILL_TYPE provides for floating as well as grounded processing of lateral metal fill emulation
as defined by FILL_WIDTH and FILL_SPACING.

Examples
CONDUCTOR m1 {
THICKNESS=0.6 WMIN=0.3 SMIN=0.3 FILL_RATIO = 0.4
FILL_SPACING = 1.0 FILL_WIDTH = 2.0 FILL_TYPE=FLOATING
}

See Also
FILL_RATIO

FILL_SPACING

FILL_WIDTH

Conventional ITF Syntax Specification 2-54


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FILL_WIDTH
Specifies the average size of metal fill objects. Valid within a CONDUCTOR block.

Syntax
FILL_WIDTH = value

Arguments

Argument Description

value Average width of metal fill objects


Units: microns

Description
The FILL_WIDTH option specifies the average size of metal fill objects, in microns.
FILL_WIDTH is required if FILL_SPACING or FILL_RATIO is specified.

Examples
CONDUCTOR m1 {
THICKNESS=0.6 WMIN=0.3 SMIN=0.3
FILL_RATIO = 0.4 FILL_SPACING = 1.0 FILL_WIDTH = 2.0
}

See Also
FILL_RATIO

FILL_SPACING

FILL_TYPE

Chapter 2: Conventional ITF Syntax Specification


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FLOATING_GATE_TO_DIFFUSION_CONTACT_CAP
Specifies a capacitance table to model floating polycide on the diffusion edge. Valid within a
CONDUCTOR block.

Syntax
FLOATING_GATE_TO_DIFFUSION_CONTACT_CAP {
GATE_POLYGON_LENGTH { l1 l2 ln }
GATE_TO_CONTACT_SPACING { s1 s2 sn }
CAPACITANCE_VALUES { c(l1,s1) c(l2,s2) c(ln,sn) }
}

Arguments

Argument Description

l1 l2 ln Gate polygon lengths specified in ascending order


Units: microns

s1 s2 sn Gate to contact spacings specified in ascending order


Units: microns

c(ln,sn) Capacitance values for corresponding length and spacing values


Units: fF

Description
Specify the FLOATING_GATE_TO_DIFFUSION_CONTACT_CAP option within a CONDUCTOR
block to assist with accurate modeling of floating polycide layers on the diffusion edge. This
keyword is allowed only when the conductor also has a LAYER_TYPE specification of
FLOATING_GATE.

The specified length and spacing values form triplets with the capacitance values. For
example, the first capacitance value corresponds to the first gate polygon length and the first
gate-to-contact spacing value. The second capacitance value corresponds to the second
length value and second spacing value, and so on.

Conventional ITF Syntax Specification 2-56


Interconnect Technology Format Specification Version 2015.06

Figure 2-8 FinFET Layout With Floating Gate

floating polycide layer

diffusion layer

bulk diffusion

device fins

gate-to-contact spacing gate polygon length

Example
The following example includes two capacitance values that correspond to the two sets of
gate polygon length and gate-to-contact spacing values. For example, when the gate
polygon length is 0.2 and the spacing is 0.5, the capacitance is 1.5. When the gate polygon
length is 0.3 and the spacing is 0.6, the capacitance is 2.5.
FLOATING_GATE_T0_DIFFUSION_CONTACT_CAP {
GATE_POLYGON_LENGTH { 0.2 0.3 }
GATE_TO_CONTACT_SPACING { 0.5 0.6 }
CAPACITANCE_VALUES { 1.5 2.5 }
}

See Also
CONDUCTOR

Chapter 2: Conventional ITF Syntax Specification


Conventional ITF Syntax Specification
FLOATING_GATE_TO_DIFFUSION_CONTACT_CAP 2-57
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FROM
Specifies a conductor layer connected to a via. Valid within a VIA block.

Syntax
FROM = layer

Arguments

Argument Description

layer Conductor layer connected by the via

Description
The FROM option specifies the upper or lower layer (which must be a defined CONDUCTOR
layer) connected by a via.

Examples
VIA sub_tie {
FROM = SUBSTRATE
TO = M1
AREA = 0.25
RPV = 5
}

See Also
TO

VIA

Conventional ITF Syntax Specification 2-58


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GATE_TO_CONTACT_SMIN
Specifies the minimum spacing value between the polysilicon gate and the METAL1-
diffusion contact layer. Valid within a CONDUCTOR block.

Syntax
GATE_TO_CONTACT_SMIN = spacing

Arguments

Argument Description

spacing Minimum spacing value between the polysilicon gate layer and
the METAL1 diffusion contact layer. The default is specified by
the SMIN option.

Description
The GATE_TO_CONTACT_SMIN option specifies the minimum spacing value between the
polysilicon gate and the METAL1-diffusion contact layer as shown in Figure 2-9.
Figure 2-9 Derivation of SMIN and GATE_TO_CONTACT_SMIN

GATE_TO_CONTACT_SMIN

M1 M1

SMIN

GATE POLY

NSD NSD

Examples
CONDUCTOR poly {
THICKNESS=1.00 WMIN=0.13 SMIN=0.15
RPSQ=0.015 GATE_TO_CONTACT_SMIN=0.08
}

Chapter 2: Conventional ITF Syntax Specification


Conventional ITF Syntax Specification
GATE_TO_CONTACT_SMIN 2-59
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GATE_TO_DIFFUSION_CAP
Models the gate-to-diffusion capacitance within a CONDUCTOR statement.

Syntax
GATE_TO_DIFFUSION_CAP {
NUMBER_OF_TABLES = num_of_tables
model_name1 {
CONTACT_TO_CONTACT_SPACINGS {c1 c2 c3 cm}
GATE_TO_CONTACT_SPACINGS {s1 s2 s3 sn}
CAPS_PER_MICRON {
v(c1,s1) v(c2,s1) v(cm,s1)
v(c1,s2) v(c2,s2) v(cm,s2)

v(c1,sn) v(c2,sn) ... v(cm,sn)
}
GATE_WIDTHS { g1 g2 g3 ... gx }
GATE_TO_CONTACT_SPACINGS { s1 s2 s3 ... sn }
CAPS_PER_MICRON {
v(g1,s1) v(g2,s1) v(gx,s1)
v(g1,s2) v(g2,s2) v(gx,s2)

v(g1,sn) v(g2,sn) v(gx,sn)
}
}
...
model_name2 {

}
}

Arguments

Argument Description

num_of_tables Number of tables

model_name Model name

c1 c2 c3 Nearest contact-to-contact spacing (units: microns)

s1 s2 s3 Gate-to-contact spacings (units: microns)

v(c1,s1) v(c2,s1) Capacitance per micron (units: femtofarads per micron)

g1 g2 g3 Gate widths (units: microns)

Conventional ITF Syntax Specification 2-60


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Description
The capacitance table is included as part of the gate polysilicon definition in the ITF file. The
three layout-dependent parameters used for the capacitance value in the table are:
CONTACT_TO_CONTACT_SPACINGS

GATE_TO_CONTACT_SPACINGS

GATE_WIDTHS

A contact etch table and gate-diffusion cap table cannot be individually selected for a gate
layer or for a device. They are always selected as a set. If you need another combination of
two tables for a specific type of device, they can be defined in a table set with a new keyword
in the ITF file and a new database layer for the corresponding gate.

Example

Device-Dependent Gate-to-Diffusion Capacitance Table


You can specify a table based on device type. Note that the number of tables and the table
name must be specified when multiple gate-to-diffusion tables are specified in the ITF file.
A contact etch table and a gate-diffusion capacitance table for the same type of device
should have the same table name.
The following example shows multiple gate-to-diffusion capacitance tables, one for an n-
type device and another for a p-type device.
CONDUCTOR gpoly {
THICKNESS= 0.080000 WMIN= 0.040 SMIN= 0.100 RPSQ=12.000
GATE_TO_CONTACT_SMIN=0.040 CRT1=1.924e-03 CRT2=-8.751e-07
GATE_TO_DIFFUSION_CAP {
NUMBER_OF_TABLES=2
NMOS{
CONTACT_TO_CONTACT_SPACINGS {0.08 0.12}
GATE_TO_CONTACT_SPACINGS {0.04 0.08}
CAPS_PER_MICRON {0.062 0.088 0.080 0.096}
}
PMOS {
CONTACT_TO_CONTACT_SPACINGS {0.08 0.12}
GATE_TO_CONTACT_SPACINGS {0.04 0.08}
GAPS_PER_MICRON {0.088 0.1200.108 0.128}
}
}
}

Chapter 2: Conventional ITF Syntax Specification


Conventional ITF Syntax Specification
GATE_TO_DIFFUSION_CAP 2-61
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GLOBAL_TEMPERATURE
Specifies the default nominal global temperature.

Syntax
GLOBAL_TEMPERATURE = temp_value

Arguments

Argument Description

temp_value Global temperature


Units: degrees Celsius
Default: 25

Description
The GLOBAL_TEMPERATURE statement is optional. If the GLOBAL_TEMPERATURE statement is
not specified, the nominal global temperature defaults to 25 degrees Celsius.
The nominal layer temperature overrides the global temperature when both are specified.

Example
TECHNOLOGY = example_tech
GLOBAL_TEMPERATURE = 31.0

Conventional ITF Syntax Specification 2-62


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HALF_NODE_SCALE_FACTOR
Shrinks the design database before extraction begins.

Syntax
HALF_NODE_SCALE_FACTOR = scale_factor

Arguments

Argument Description

scale_factor A positive, nonzero scale factor


Default:1.0

Description
The HALF_NODE_SCALE_FACTOR statement is an optional statement that can be included in
the global parameters section of the ITF file. The HALF_NODE_SCALE_FACTOR statement
directs the extraction tool to shrink the design database by the specified value before
extraction begins, which is useful if you are using a half-node process technology.

Examples
This is an example of an ITF header using the HALF_NODE_SCALE_FACTOR statement:
TECHNOLOGY = 65nm_example
GLOBAL_TEMPERATURE = 25
HALF_NODE_SCALE_FACTOR = 0.9

DIELECTRIC PASS2 {THICKNESS=0.800000 ER=6.9}


DIELECTRIC PASS1 {THICKNESS=0.700000 ER=4.0}

Chapter 2: Conventional ITF Syntax Specification


Conventional ITF Syntax Specification
HALF_NODE_SCALE_FACTOR 2-63
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ILD_VS_WIDTH_AND_SPACING
Models the microloading effect or bottom conductor thickness variation. Valid within a
CONDUCTOR block.

Syntax
ILD_VS_WIDTH_AND_SPACING {
DIELECTRIC = ILD_Layer_Name
WIDTHS {w1 w2 w3 }
SPACINGS {s1 s2 s3 }
THICKNESS_CHANGES {
v(s1,w1) v(s2,w1)
v(s1,w2) v(s2,w2)

}
}

Arguments

Argument Description

ILD_Layer_Name The name of the dielectric layer below the conductor


corresponding to the thickness variation

WIDTHS {} Width in drawn dimensions

SPACINGS {} Spacing in drawn dimensions

THICKNESS_CHANGES {} Absolute thickness variation of the ILD layer specified. A positive


variation indicates an increase of thickness, and a decrease of
thickness is represented by a negative variation. The maximum
value is 0.2. The minimum value is -0.2.

Description
The ILD_VS_WIDTH_AND_SPACING option models the microloading effect or bottom
conductor thickness variation.
WIDTH and SPACING are drawn dimensions. The DIELECTRIC keyword specifies the
dielectric layer below the conductor that exhibits the thickness variation. Each entry in the
THICKNESS_CHANGES field specifies the absolute thickness variation of the specified
dielectric layer. A positive value indicates a thickness increase, while a negative value
represents a thickness decrease. The SPACING option can be specified before the WIDTH
option; however, the mapping of the values remains the same regardless of the order of
specification of the two options.

Conventional ITF Syntax Specification 2-64


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The ILD_VS_WIDTH_AND_SPACING option cannot be used in the same CONDUCTOR statement


as the BOTTOM_THICKNESS_VS_SI _WIDTH option or the MEASURED_FROM option.

Examples
ILD_VS_WIDTH_AND_SPACING {
DIELECTRIC = ILD3
WIDTHS {0.1 0.2 0.3 0.4}
SPACINGS {0.11 0.22 0.33 0.44}
THICKNESS_CHANGES {0.130 0.134 0.138 0.140
0.135 0.138 0.139 0.142
0.138 0.139 0.139 0.143
0.140 0.142 0.144 0.146
}
}

The DIELECTRIC statement specifies the dielectric layer below which the ILD variation is to
be accounted for. The VALUES specified are absolute ILD variation values.

See Also
BOTTOM_THICKNESS_VS_SI_WIDTH

Chapter 2: Conventional ITF Syntax Specification


Conventional ITF Syntax Specification
ILD_VS_WIDTH_AND_SPACING 2-65
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IS_CONFORMAL
Defines the material the conductor layer is deposited around and allows conformal layers to
be associated with a specified conductor layer. Valid within a DIELECTRIC block.

Syntax
IS_CONFORMAL

Arguments
The IS_CONFORMAL option does not have arguments.

Description
The IS_CONFORMAL statement is optional, but if used, it must be specified with an
ASSOCIATED_CONDUCTOR statement within a DIELCTRIC block. The combination of
statements specifies that the dielectric is conformal and defines the conductor around which
the dielectric layer is deposited.
An IS_CONFORMAL layer can use the SW_T or TW_T statements to define the sidewall and
topwall thicknesses around the conductor. If the TW_T or SW_T values are not specified,
the defaults are 0.0.
When an ASSOCIATED_CONDUCTOR material drops with a DROP_FACTOR defined for a
conductor below it, conformal dielectric layers associated with that condoctor also drop.
If a conductor layer above a conformal dielectric layer overlaps with the top wall
thickness of the conformal dielectric layer, the conductor cuts into the conformal
dielectric layer.
A conformal dielectric layer can be specified without an ASSOCIATED_CONDUCTOR. See
also ASSOCIATED_CONDUCTOR reference page for more information.

Examples
DIELECTRIC D1 {
IS_CONFORMAL ASSOCIATED_CONDUCTOR=met1
SW_T=0.1 TW_T=0.1 ER=2.5
}

See Also
ASSOCIATED_CONDUCTOR

DROP_FACTOR

Conventional ITF Syntax Specification 2-66


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IS_PLANAR
Specifies planar layers.

Syntax
IS_PLANAR

Arguments
The IS_PLANAR keyword does not have any arguments.

Description
Specifies that from this conductor and above, the layers do not drop because the
DROP_FACTOR command is specified for the lower layers.

Examples
CONDUCTOR ELEC1 {
THICKNESS = 0.010
WMIN = 0.180
SMIN = 0.100
RPSQ = 0.00001
CAPACITIVE_ONLY_ETCH = 0
IS_PLANAR
}

See Also
DROP_FACTOR

Chapter 2: Conventional ITF Syntax Specification


Conventional
IS_PLANAR ITF Syntax Specification 2-67
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LAYER_TYPE
Specifies the layer type within a CONDUCTOR block.

Syntax
LAYER_TYPE = GATE | FIELD_POLY | DIFFUSION | TRENCH_CONTACT |
BUMP | FLOATING_GATE

Arguments

Argument Description

GATE Identifies conducting layers that form the gate of a device. If


separate ITF conducting layers are not specified for gate and field
polysilicon, specify the combined gate-field polysilicon layer as
LAYER_TYPE = GATE.

FIELD_POLY Identifies field polysilicon outside of the device region.

DIFFUSION Identifies source or drain diffusion regions.

TRENCH_CONTACT Identifies conducting layers used for trench contacts. This


includes both M1-to-diffusion trench contacts and M1-to-
polysilicon trench contacts that can be used both inside and
outside of the device region.

BUMP Defines the layer as a pseudo-metal via layer, used to connect


microbumps to the top metal layer.

FLOATING_GATE Identifies conducting layers used as floating gates.

Description
For advanced process technologies, information in the ITF file about the function of the
conducting layers improves accuracy. You can optionally include a LAYER_TYPE keyword
within a CONDUCTOR section to guide the analysis. If a conducting layer does not have a
specified layer type, the layer type defaults to a standard routing layer.
When specifying the layer type, note the following constraints on the relative vertical position
of the conductors in the interconnect stack:
Conductors with LAYER_TYPE = GATE and LAYER_TYPE = FIELD_POLY must be
covertical.

Conventional ITF Syntax Specification 2-68


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Conductors with LAYER_TYPE = TRENCH_CONTACT must be covertical with or above


conductors with LAYER_TYPE = GATE or LAYER_TYPE = FIELD_POLY.
Conductors with LAYER_TYPE = DIFFUSION must be below the conductors with
LAYER_TYPE = GATE.

Example
The following example uses the LAYER_TYPE option to identify gate and diffusion layers:
CONDUCTOR PS {
THICKNESS = 0.04
WMIN = 0.04
SMIN = 0.04
GATE_TO_CONTACT_SMIN = 0.02
LAYER_TYPE = GATE

}
DIELECTRIC DP1 {
THICKNESS = 0.001

}
DIELECTRIC D_DIFF {
THICKNESS = 0.04

}
CONDUCTOR DIFF {
THICKNESS = 0.04
WMIN=0.04
SMIN=0.04
LAYER_TYPE = DIFFUSION

}

See Also
CONDUCTOR

VIA

Chapter 2: Conventional ITF Syntax Specification


Conventional
LAYER_TYPEITF Syntax Specification 2-69
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MEASURED_FROM
Modifies the reference location where thickness is measured.

Syntax
MEASURED_FROM = dielectric_layer | TOP_OF_CHIP

Arguments

Argument Description

dielectric_layer The name of the dielectric layer from which the measurement is
made. This layer name must be defined in the ITF.
The default is the dielectric layer immediately below.

TOP_OF_CHIP Facilitates the creation of conformal dielectrics. It creates the


bottom plane from the layers already present below the new layer
and mimics the topology of the existing base (copies any existing
nonplanarities to the new layer, which has a conformal
thickness).

Description
Modifies the reference location where thickness is measured. The default is the dielectric
layer immediately below it; be careful when using this feature for a conducting layer, as it is
possible to create a conductor that cuts a dielectric, which might not be the desired effect.
The MEASURED_FROM option provides the ability to customize the model to account for such
process characteristics as conformal dielectrics, mixed conformal and planar dielectrics,
and covertical conductors. When used with a DIELECTRIC layer definition, the
MEASURED_FROM keyword can refer to a lower dielectric or can have the value TOP_OF_CHIP.
When used with a CONDUCTOR layer definition, the MEASURED_FROM keyword can refer only to
a lower planar dielectric.
The heights of the conductors and dielectrics are determined exclusively by the order in
which they are specified and by the thicknesses of the lower layers. When you are
specifying a new conductor or dielectric layer, the bottom plane of that layer is exactly the
top plane of the dielectric layer immediately below it unless a MEASURED_FROM option is
included (to explicitly specify the location of the bottom plane).
Specify the MEASURED_FROM option within a CONDUCTOR or DIELECTRIC statement.

Conventional ITF Syntax Specification 2-70


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Examples
In the following example, TOP is planarized by measuring from D2:
DIELECTRIC TOP {
THICKNESS = 3.6
MEASURED_FROM = D2
ER = 3.9
}

In the following example, D3 is a conformal dielectric:


DIELECTRIC D3 {
THICKNESS=0.2
MEASURED_FROM = TOP_OF_CHIP
ER=3.9
}

See Also
CONDUCTOR

DIELECTRIC

SW_T

TW_T

Chapter 2: Conventional ITF Syntax Specification


Conventional
MEASURED_FROMITF Syntax Specification 2-71
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MULTIGATE
Describes FinFET devices.

Syntax
MULTIGATE fin {
FIN_SPACING = fin_spacing
FIN_WIDTH = fin_width
FIN_LENGTH = fin_length (optional)
FIN_THICKNESS = fin_thickness
RAISED_DIFFUSION_GROWTH = raised_diffusion_growth (optional)
GATE_POLY_EXTENSION = gate_poly_extension (optional)
GATE_OXIDE_TOP_T = gate_oxide_top_thickness
GATE_OXIDE_SIDE_T = gate_oxide_side_thickness
GATE_OXIDE_ER = gate_oxide_permittivity
GATE_POLY_TOP_T = gate_poly_top_thickness
GATE_POLY_SIDE_T = gate_poly_side_thickness
CHANNEL_ER = channel_permittivity
GATE_DIFFUSION_LAYER_PAIR { (PGATE PDIFF) (NGATE NDIFF) ...}
}

Arguments

Argument Description

FIN_SPACING Fin spacing; the distance between adjacent fin sidewalls


Units: microns

FIN_WIDTH Fin width


Units: microns

FIN_LENGTH Fin length (optional); the distance between the gate


sidewall and the raised diffusion region
Units: microns

FIN_THICKNESS Fin thickness


Units: microns

RAISED_DIFFUSION_GROWTH Raised diffusion growth (optional); distance that raised


diffusion extends laterally from fin sidewall
Units: microns

GATE_POLY_EXTENSION Gate poly extension (optional); distance that gate poly


extends laterally outside the diffusion region
Units: microns

Conventional ITF Syntax Specification 2-72


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Argument Description

GATE_OXIDE_TOP_T Gate oxide top thickness


Units: microns

GATE_OXIDE_SIDE_T Gate oxide side thickness


Units: microns
Default: value of GATE_OXIDE_TOP_T

GATE_OXIDE_ER Gate oxide relative permittivity


Units: none (ratio)

GATE_POLY_TOP_T Gate poly top thickness


Units: microns

GATE_POLY_SIDE_T Gate poly side thickness


Units: microns
Default: value of GATE_POLY_TOP_T

CHANNEL_ER Channel relative permittivity


Units: none (ratio)

GATE_DIFFUSION_LAYER_PAIR Identifies the gate diffusion layer pair

Description
A block starting with the MULTIGATE keyword represents FinFET or other advanced devices.
Inside the block, you specify parameters that describe a three-dimensional structure. The
units for all length parameters are microns. Figure 2-10 and Figure 2-11 illustrate transistor
parameters and cross sections.
The FIN_LENGTH parameter is optional. If the parameter is not specified, the final fin length
is the distance from the gate edge to the far edge of the diffusion region, labeled as diffusion
length in Figure 2-10.

Chapter 2: Conventional ITF Syntax Specification


Conventional
MULTIGATE ITF Syntax Specification 2-73
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Figure 2-10 FinFET Top View and Cross Section Along Gate and Along Fin

gate poly
gate top gate oxide
thickness thickness top thickness

fin length fin width

fin spacing gate poly


side thickness
gate oxide
side thickness

gate raised
raised
thickness diffusion
diffusion to
gate smin thickness

fin
diffusion length thickness diffusion
thickness

source/drain field poly

gate poly gate oxide

fin

The RAISED_DIFFUSION_GROWTH parameter is optional; it represents the distance that a


raised source/drain region extends laterally from the fin sidewall. If the value is larger than
half the spacing between the fins, the raised diffusion regions merge, as shown by the large
green boxes in Figure 2-10. If the value is less than half the fin spacing, the raised diffusion
regions remain separate, as shown by the smaller green boxes in Figure 2-11.

Conventional ITF Syntax Specification 2-74


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Figure 2-11 FinFET Top View With Different Diffusion Bounding Boxes

gate poly gate poly


side thickness extension

diffusion diffusion
width width

raised diffusion growth raised diffusion growth

source/drain field poly

gate poly gate oxide

fin region boundary

If the RAISED_DIFFUSION_GROWTH parameter is not specified, a merged region is assumed.


If the parameter is specified, the dimensions of the unmerged raised diffusion box are:
Length (parallel to the fin length), calculated as:
DIFFUSION_LENGTH - RAISED_DIFFUSION_TO_GATE_SMIN

Width (perpendicular to the fin length), calculated as:


FIN_WIDTH + 2*RAISED_DIFFUSION_GROWTH

Height or thickness, equal to the RAISED_DIFFUSION_THICKNESS parameter


Two styles of diffusion regions are supported, as shown by the dashed lines in Figure 2-11.
If the GATE_POLY_SIDE_T parameter is specified and the GATE_POLY_EXTENSION
parameter is undefined, the diffusion region boundary extends beyond the outermost fins
by the distance specified in the GATE_POLY_SIDE_T parameter.

Chapter 2: Conventional ITF Syntax Specification


Conventional
MULTIGATE ITF Syntax Specification 2-75
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If the GATE_POLY_EXTENSION parameter is defined, the diffusion region boundary


coincides with the outer sidewall of the outermost fins; the gate poly extends beyond the
diffusion region boundary by that distance.

Examples
The following two MULTIGATE blocks model NMOS and PMOS FinFET transistors. In the
presence of a MULTIGATE statement, the DEVICE_TYPE keyword must be used to identify the
conductor layers that compose a specified device if there is more than one layer with
LAYER_TYPE=FIELD_POLY in the ITF file.

Example 2-1 NMOS And PMOS FinFET Transistor Models


MULTIGATE Nmos_fin {
Fin_spacing=0.040
Fin_width=0.02
Fin_length=0.06
Fin_thickness=0.05
Raised_diffusion_growth=0.01
Gate_oxide_top_t=0.003
Gate_oxide_side_t=0.003
Gate_oxide_er=8.0
Gate_poly_top_t=0.03
Gate_poly_side_t=0.04
Channel_er=10.0
Gate_diffusion_layer_pair {(Ngate Ndiff) }
}
MULTIGATE Pmos_fin {
Fin_spacing=0.045
Fin_width=0.025
Fin_length=0.065
Fin_thickness=0.05
Raised_diffusion_growth=0.01
Gate_oxide_top_t=0.0025
Gate_oxide_side_t=0.0025
Gate_oxide_er=8.0
Gate_poly_top_t=0.035
Gate_poly_side_t=0.045
Channel_er=10.0
Gate_diffusion_layer_pair {(Pgate Pdiff) }
}

If two device types have the same parameters, you can define them with a single MULTIGATE
block as follows:
MULTIGATE MOS_FIN {
...
GATE_DIFFUSION_LAYER_PAIR { (NGATE NDIFF) (PGATE PDIFF) }
}

Conventional ITF Syntax Specification 2-76


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POLYNOMIAL_BASED_THICKNESS_VARIATION
Models conductor thickness variation as a function of feature density and width in a
polynomial format. Valid within a CONDUCTOR block.

Syntax
POLYNOMIAL_BASED_THICKNESS_VARIATION {
[SI_]DENSITY_POLYNOMIAL_ORDERS = { do(n) do(n-1) do(0) }
[SI_]WIDTH_POLYNOMIAL_ORDERS = { wo(m) wo(m-1) wo(0) }
WIDTH_RANGES = { wt0 wt1 }
POLYNOMIAL_COEFFICIENTS = {
a(n,m) a(n,m-1) a(n,0)
a(n-1,m) a(n-1,m-1) a(n-1,0)

a(0,m) a(0,m-1) a(0,0)
}
POLYNOMIAL_COEFFICIENTS = {
b(n,m) b(n,m-1) b(n,0)
b(n-1,m) b(n-1,m-1) b(n-1,0)

b(0,m) b(0,m-1) b(0,0)
}
POLYNOMIAL_COEFFICIENTS = {
c(n,m) c(n,m-1) c(n,0)
c(n-1,m) c(n-1,m-1) c(n-1,0)

c(0,m) c(0,m-1) c(0,0)
}
...
[DENSITY_BOUNDS_VS_WIDTH {
(wd1 dmin_wd1 dmax_wd1)
(wd2 dmin_wd2 dmax_wd2)

(wdn dmin_wdn dmax_wdn)
} ]
[THICKNESS_BOUNDS {
tmin tmax
} ]
}

SYNTAX NOTES: If the WIDTH_RANGES keyword is not used, there must be


exactly one POLYNOMIAL_COEFFICIENTS table. If the WIDTH_RANGES keyword
is used, the number of POLYNOMIAL_COEFFICIENTS tables must be one more
than the number of widths in the WIDTH_RANGES argument list.

Chapter 2: Conventional ITF Syntax Specification


Conventional ITF Syntax Specification
POLYNOMIAL_BASED_THICKNESS_VARIATION 2-77
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Arguments

Argument Description

do(n) ... do(0) Density exponents


Format: integer

wo(n) ... wo(0) Width exponents


Format: integer

wt0, wt1, ... Conductor widths that determine which coefficient table to use;
must appear in ascending order
Units: microns

a(n,m), b(n,m), ... Polynomial coefficients

wd1, wd2, ... Conductor widths that define density bounds; must appear in
ascending order
Units: microns

dmin_wd1, dmax_wd1 Minimum and maximum density for the corresponding width

tmin Minimum absolute thickness; must be smaller than conductor


nominal thickness
Units: microns

tmax Maximum absolute thickness; must be larger than conductor


nominal thickness
Units: microns

Description
The POLYNOMIAL_BASED_THICKNESS_VARIATION command uses a polynomial to model
conductor thickness variation as a function of density and width. You can use either the as-
drawn or the post-etch values of density and width in the calculations.
The command contains one or more tables of polynomial coefficients. A specific table
applies to a range of conductor widths defined by the WIDTH_RANGES keyword. The
coefficients table is selected as follows:
If the WIDTH_RANGES keyword is not used, one coefficients table is used for all conductor
widths. Only one table should be provided.
If the WIDTH_RANGES keyword has an argument list with one width value, there must be
exactly two POLYNOMIAL_COEFFICIENTS tables. The first coefficients table applies to

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conductor widths less than or equal to the listed width, while the second table applies to
conductor widths larger than the listed width.
If the WIDTH_RANGES keyword has an argument list with more than one width value, the
widths define a series of ranges. The first coefficients table applies to conductor widths
less than or equal to the first width in the list. The second table applies to widths greater
than the first width in the list and less than or equal to the second width, and so on. The
last table applies to conductor widths larger than the last width in the list.
Thickness variation is calculated as follows, where W is the conductor width and D is the
density:

a ( n, m ) wo ( m )
a ( n, m 1 ) a ( n, 1 ) a ( n, 0 ) W
a ( n 1, m ) a ( n 1, 0 ) W wo ( m 1 )
dT
------- = D do ( n ) D do ( n 1 ) D do ( 1 ) D do ( 0 )
T
wo ( 1 )
a ( 1, m ) a ( 1, 0 ) W
wo ( 0 )
a ( 0, m ) a ( 0, m 1 ) a ( 0, 1 ) a ( 0, 0 ) W

The following example illustrates the calculation by using symbols to represent the
coefficients. In this example, one coefficients table is used for all conductor widths because
no WIDTH_RANGES keyword is included:
POLYNOMIAL_BASED_THICKNESS_VARIATION {
DENSITY_POLYNOMIAL_ORDERS = { 2 1 0 }
WIDTH_POLYNOMIAL_ORDERS = { 4 2 0 }
POLYNOMIAL_COEFFICIENTS = {
a b c
d e f
g h i
}
}

The resulting thickness variation equation is as follows:

dT 2 4 2 0 1 4 2 0 0 4 2 0
------- = D ( aW + bW + cW ) + D ( dW + eW + fW ) + D ( gW + hW + iW )
T

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Specifying As-Drawn or Silicon Values for Width and Density


You can use either the as-drawn layout dimensions or post-etch (silicon) dimensions in the
calculations, as follows:
Conductor width
If you use the WIDTH_POLYNOMIAL_ORDERS keyword, conductor widths used in
calculations are based on the as-drawn layout dimensions. This includes the widths
used in the WIDTH_RANGES keyword and and the widths (but not the densities) used
in the DENSITY_BOUNDS_VS_WIDTH keyword.
If you use the SI_WIDTH_POLYNOMIAL_ORDERS keyword, conductor widths are based
on the post-etch (silicon) dimensions.
Conductor density
If you use the DENSITY_POLYNOMIAL_ORDERS keyword, conductor densities used in
calculations are based on the as-drawn layout dimensions. This includes the
densities used in the DENSITY_BOUNDS_VS_WIDTH keyword.
If you use the SI_DENSITY_POLYNOMIAL_ORDERS keyword, conductor densities are
based on the post-etch (silicon) dimensions.

Using the global USE_SI_DENSITY command in the ITF file might conflict with these
keywords. Table 2-3 describes the allowed usages.
Table 2-3 Effect of USE_SI_DENSITY Command Settings

POLYNOMIAL_BASED_THICKNESS_VARIATION USE_SI_DENSITY USE_SI_DENSITY


Keyword = YES = NO (or not used)

WIDTH_POLYNOMIAL_ORDERS drawn width drawn width

DENSITY_POLYNOMIAL_ORDERS silicon density drawn density

SI_WIDTH_POLYNOMIAL_ORDERS error silicon width

SI_DENSITY_POLYNOMIAL_ORDERS error silicon density

Density Bounds
Use the optional DENSITY_BOUNDS_VS_WIDTH keyword to limit the conductor densities to be
used in the calculations. Each entry in the argument list consists of one width value and two
density values enclosed in parentheses; you can provide more than one such entry.

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Whether the width and density values in the DENSITY_BOUNDS_VS_WIDTH keyword use as-
drawn or post-etch (silicon) values is determined by the presence or absence of the SI_
prefix in the WIDTH_POLYNOMIAL_ORDERS and DENSITY_POLYNOMIAL_ORDERS keywords.
The density bounds in the DENSITY_BOUNDS_VS_WIDTH keyword are applied as follows:
If the density is outside the range defined by the minimum and maximum densities, the
nearest density bound is used in the calculation.
If there is only one entry (in other words, one triplet of values) in the
DENSITY_BOUNDS_VS_WIDTH argument list, the minimum and maximum densities apply
to all conductor widths regardless of the width specified in the triplet.
If there are multiple triples in the keyword argument list, the behavior is as follows:
If the conductor width is smaller than the smallest width specified, the minimum and
maximum densities for the smallest width are used.
If the conductor width is larger than the largest width specified, the minimum and
maximum densities for the largest width are used.
If the conductor width is between two specified widths, the minimum and maximum
densities are determined by interpolating between the enclosing density values.
In the following example, only density values between 0.05 and 1.00 are used when
calculating thickness variation for conductor widths up to and including 0.1 microns. Density
values from 0.07 to 0.50 are used for conductor widths greater than 0.2 microns. If the
conductor width is 0.15 microns, the allowable range of density values is 0.06 to 0.75, as
determined by linear interpolation.
DENSITY_BOUNDS_VS_WIDTH {
(0.1 0.05 1.00)
(0.2 0.07 0.50)
}

If you do not use the DENSITY_BOUNDS_VS_WIDTH keyword, the density bounds are
calculated using the minimum and maximum width and spacing values in the
ETCH_VS_WIDTH_AND_SPACING command defined for the same conductor. This method is
available for backward compatibility, but might result in unreasonable values.
In this method, the minimum and maximum densities are calculated as follows, where D is
density, W is width, and S is spacing:

W min
D min = ------------------------------------
( W min + S max )

W max
D max = ------------------------------------
( W max + S min )

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Thickness Bounds
Use the optional THICKNESS_BOUNDS keyword to apply limits to the calculated conductor
thickness values, as follows:
If the conductor thickness calculated from the polynomial function is smaller than the
minimum thickness in the THICKNESS_BOUNDS argument list, the minimum thickness
value is used instead of the calculated thickness.
If the conductor thickness calculated from the polynomial function is larger than the
maximum thickness in the THICKNESS_BOUNDS argument list, the maximum thickness
value is used instead of the calculated thickness.

Example
In the following example, the first coefficients table is used for widths less than or equal to
0.27 microns, while the second table is used for widths greater than 0.27 microns. All widths
and densities are calculated using post-etch (silicon) dimensions.
CONDUCTOR M1 { THICKNESS=0.18 SIDE_TANGENT = 0.0556
POLYNOMIAL_BASED_THICKNESS_VARIATION {
SI_DENSITY_POLYNOMIAL_ORDERS = { 3 2 1 0 }
SI_WIDTH_POLYNOMIAL_ORDERS = { 4 3 2 1 0 }
WIDTH_RANGES = { 0.27 }
$ Coefficients for width <= 0.27
POLYNOMIAL_COEFFICIENTS = {
0 1.656E+03 -9.488E+02 1.731E+02 -1.041E+01
0 -1.212E+03 6.935E+02 -1.262E+02 7.666E+00
0 2.314E+02 -1.320E+02 2.400E+01 -1.580E+00
0 -5.211E+00 3.417E+00 -6.853E-01 1.131E-01
}
$ Coefficients for width > 0.27
POLYNOMIAL_COEFFICIENTS = {
1.027E-03 -2.006E-02 8.996E-02 -5.189E-02 -1.814E-01
-2.805E-03 5.795E-02 -3.084E-01 4.211E-01 1.152E-01
2.097E-03 -4.375E-02 2.394E-01 -3.662E-01 -2.697E-02
-4.866E-04 1.001E-02 -5.416E-02 1.012E-01 4.308E-02
}
DENSITY_BOUNDS_VS_WIDTH {
(0.1 0.05 0.97)
(0.2 0.07 0.49)
(0.3 0.10 0.52)
(1.0 0.50 0.97)
}
THICKNESS_BOUNDS { 0.30 0.45 }
}
}

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Error Conditions
Several ITF commands provide alternative methods for modeling conductor thickness
variation. Therefore, they cannot be specified for the same conducting layer when the
POLYNOMIAL_BASED_THICKNESS_VARIATION command is used. These commands are as
follows:
THICKNESS_VS_DENSITY

THICKNESS_VS_WIDTH_AND_SPACING

DENSITY_BOX_WEIGHTING_FACTOR

See Also
THICKNESS_VS_DENSITY

THICKNESS_VS_WIDTH_AND_SPACING

DENSITY_BOX_WEIGHTING_FACTOR

ETCH_VS_WIDTH_AND_SPACING

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RAISED_DIFFUSION_ETCH
Specifies the etch distance of the raised diffusion conductor.

Syntax
RAISED_DIFFUSION_ETCH = distance

Arguments

Argument Description

distance Etch distance of the raised diffusion conductor


Units: microns

Description
The RAISED_DIFFUSION_ETCH option specifies the etch distance of the raised diffusion
conductor, on the sides of the diffusion conductor that are not adjacent to a gate or field
polysilicon conductor, as shown in Figure 2-12.
Figure 2-12 Cross Section and Top Views of the Trench Contact Process

Cross Section View

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Figure 2-13 shows the specific scenarios in which the RAISED_DIFFUSION_ETCH and
RAISED_DIFFUSION_TO_GATE_SMIN options are applied. In a typical process, raised
diffusion growth is impacted by the location of the polysilicon spacer dielectric. The
RAISED_DIFFUSION_TO_GATE_SMIN option models this process effect. The
RAISED_DIFFUSION_ETCH option models a different process effect in regions that do not
overlap with the polysilicon spacer dielectric. Note that the raised diffusion edge geometry is
solely determined by the RAISED_DIFFUSION_THICKNESS,
RAISED_DIFFUSION_TO_GATE_SMIN, and RAISED_DIFFUSION_ETCH options. Therefore, the
RAISED_DIFFUSION_TO_GATE_SMIN option is independent of the polysilicon conductors
conformal dielectrics. The RAISED_DIFFUSION_ETCH and
RAISED_DIFFUSION_TO_GATE_SMIN options are applied based on the post-etch silicon
dimensions of the polysilicon and diffusion conductors.
Figure 2-13 Polysilicon Spacing From Raised Diffusion Regions

The RAISED_DIFFUSION_ETCH option has the following constraints:


RAISED_DIFFUSION_ETCH must be greater than or equal to 0.0.

RAISED_DIFFUSION_ETCH must be specified with both RAISED_DIFFUSION_THICKNESS


and RAISED_DIFFUSION_TO_GATE_SMIN.
RAISED_DIFFUSION_ETCH must be specified in a conductor layer with
LAYER_TYPE = DIFFUSION.

The value of RAISED_DIFFUSION_ETCH must be constrained to ensure that nonphysical


conductor geometries are not generated.

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Examples
CONDUCTOR DIFF {
THICKNESS = 0.05
LAYER_TYPE = DIFFUSION
RAISED_DIFFUSION_ETCH = 0.005
RAISED_DIFFUSION_THICKNESS = 0.015
RAISED_DIFFUSION_TO_GATE_SMIN = 0.01

}

See Also
CONDUCTOR

LAYER_TYPE

RAISED_DIFFUSION_THICKNESS

RAISED_DIFFUSION_TO_GATE_SMIN

Conventional ITF Syntax Specification 2-86


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RAISED_DIFFUSION_GATE_SIDE_CONFORMAL_ER
Specifies the dielectric constant of the area between the raised diffusion and the gate
processes.

Syntax
RAISED_DIFFUSION_GATE_SIDE_CONFORMAL_ER = er_value

Arguments

Argument Description

er_value Specifies the dielectric constant of the area between the raised
diffusion and the gate processes.
Units: microns
Default: Dielectric constant of the raised diffusion area.

Description
The RAISED_DIFFUSION_GATE_SIDE_CONFORMAL_ER option specifies the dielectric constant
of the dielectric region between the raised diffusion and the gate processes when you model
silicon dielectrics underneath the gate and diffusion conductors, as shown in Figure 2-14.
This option works with the BW_T option, which models the associated silicon dielectrics.
Place the RAISED_DIFFUSION_GATE_SIDE_CONFORMAL_ER option within the raised diffusion
CONDUCTOR statement. This option can only be placed in conductors containing
RAISED_DIFFUSION_THICKNESS and RAISED_DIFFUSION_TO_GATE_SMIN definitions.

Chapter 2: Conventional ITF Syntax Specification


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Figure 2-14 Area Between the Raised Diffusion and the Gate Processes

gate poly trench contact

raised diffusion

raised diffusion
dielectric region

gate oxide

Examples
The following example uses the RAISED_DIFFUSION_GATE_SIDE_CONFORMAL_ER option to
specify the dielectric constant of the raised diffusion dielectric region.
CONDUCTOR DIFF { THICKNESS=0.1
RAISED_DIFFUSION_THICKNESS=0.02
RAISED_DIFFUSION_TO_GATE_SMIN=0.03
RAISED_DIFFUSION_GATE_SIDE_CONFORMAL_ER=5.0 }

See Also
MEASURED_FROM

SW_T

BW_T

THICKNESS

Conventional ITF Syntax Specification 2-88


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RAISED_DIFFUSION_THICKNESS
Specifies additional diffusion thickness in raised source and drain regions.

Syntax
RAISED_DIFFUSION_THICKNESS = thickness

Arguments

Argument Description

thickness Additional diffusion thickness in raised source and drain regions


Units: microns

Description
The RAISED_DIFFUSION_THICKNESS option specifies additional diffusion thickness in raised
source and drain regions.
Specify the RAISED_DIFFUSION_THICKNESS option within a CONDUCTOR block with the
LAYER_TYPE set to DIFFUSION. The raised portion of the diffusion is not applied to regions
that are closer than the specified RAISED_DIFFUSION_TO_GATE_SMIN value to conductors
with the GATE or FIELD_POLY layer type.

Examples
In the following example, the raised diffusion region exists in all diffusion conductors at a
spacing of 10 nm from adjacent polysilicon conductors. The raised diffusion region extends
11 nm above the nominal diffusion height. Therefore, the raised diffusion region is covertical
with the bottom 10 nm of the polysilicon conductor. The DIFF_NO_RSD layer is a standard
diffusion layer without raised source and drain regions, which can also exist in the process.

Chapter 2: Conventional ITF Syntax Specification


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The ITF description of the structure is as follows:


CONDUCTOR PS {
THICKNESS=0.04
WMIN=0.04
SMIN=0.04
GATE_TO_CONTACT_SMIN=0.02
LAYER_TYPE=GATE

}
DIELECTRIC DP1 {
THICKNESS=0.001

}
DIELECTRIC D_DIFF {
THICKNESS=0.04

}
CONDUCTOR DIFF {
THICKNESS=0.04
WMIN=0.04
SMIN=0.04
RAISED_DIFFUSION_THICKNESS=0.011
RAISED_DIFFUSION_TO_GATE_SMIN=0.01
LAYER_TYPE=DIFFUSION

}
CONDUCTOR DIFF_NO_RSD {
THICKNESS=0.04
WMIN=0.04
SMIN=0.04
LAYER_TYPE=DIFFUSION

}

See Also
CONDUCTOR

LAYER_TYPE

RAISED_DIFFUSION_ETCH

RAISED_DIFFUSION_TO_GATE_SMIN

Conventional ITF Syntax Specification 2-90


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RAISED_DIFFUSION_TO_GATE_SMIN
Specifies the minimum lateral spacing between raised source and drain regions and gate or
field polysilicon conductors.

Syntax
RAISED_DIFFUSION_TO_GATE_SMIN = spacing

Arguments

Argument Description

spacing Minimum lateral spacing between raised source and drain


regions
Units: microns

Description
The RAISED_DIFFUSION_TO_GATE_SMIN option specifies the minimum lateral spacing
between raised source and drain regions and gate or field polysilicon conductors.
Specify the RAISED_DIFFUSION_THICKNESS option within a CONDUCTOR block with the
LAYER_TYPE set to DIFFUSION.

See Also
CONDUCTOR

LAYER_TYPE

RAISED_DIFFUSION_ETCH

RAISED_DIFFUSION_THICKNESS

Chapter 2: Conventional ITF Syntax Specification


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REFERENCE_DIRECTION
Specifies the reference direction of the process technology.

Syntax
REFERENCE_DIRECTION = VERTICAL | HORIZONTAL

Arguments

Argument Description

VERTICAL Reference direction is vertical

HORIZONTAL Reference direction is horizontal

Description
The REFERENCE_DIRECTION statement defines the reference direction of the process
technology for the application of orientation-dependent etch values, which are defined by
the ETCH_VS_WIDTH_AND_SPACING option. Specify the REFERENCE_DIRECTION statement in
the header of the ITF file.

Examples
The following statement specifies that the reference direction is horizontal:
REFERENCE_DIRECTION = HORIZONTAL

See Also
ETCH_VS_WIDTH_AND_SPACING

Conventional ITF Syntax Specification 2-92


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RESISTIVE_ONLY_ETCH
identical to the ETCH option, except that only resistance is affected. Valid within a CONDUCTOR
block.

Syntax
RESISTIVE_ONLY_ETCH = etch_value

Arguments

Argument Description

etch_value Absolute width adjustment for one sidewall. A positive value


shrinks the conductor; a negative value expands it.
Units: microns

Description
The RESISTIVE_ONLY_ETCH option applies an etch value to the sidewalls of a conductor. A
positive value denotes conductor shrink; a negative value denotes conductor expansion.
The adjusted conductor width is equal to the drawn width minus twice the etch value.
Use this option instead of the ETCH option to specify that an etch operation is to be used only
for resistance calculations.
If you use one of the ETCH options in addition to one or more ETCH_VS_WIDTH_AND_SPACING
tables, the ETCH_VS_WIDTH_AND_SPACING operations are applied first, followed by the ETCH
operation.
This option is not the same as ETCH_VS_WIDTH_AND_SPACING RESISTIVE_ONLY.

Example
CONDUCTOR metal1 {
RESISTIVE_ONLY_ETCH = 0.05
THICKNESS=0.66
WMIN=0.15 SMIN=0.15 RPSQ=0.078
}

See Also
CAPACITIVE_ONLY_ETCH

ETCH

Chapter 2: Conventional ITF Syntax Specification


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RHO
Defines the bulk resistivity of a VIA or CONDUCTOR layer.

Syntax
RHO = rho_value

Arguments

Argument Description

rho_value Bulk resistivity of the via or conductor layer


Units: ohms-micron
Default: 0.0 for conductors or RPV x AREA of 1.0e-6 for VIAs

Description
The resistive properties of the via and conductor layers must be specified.
The via layers can be specified in two ways: RHO, or RPV and AREA, however, only one
specification method is required.
The conductor layers resistive properties can be specified in two ways: RHO or RPSQ.
Specify this option within a CONDUCTOR or VIA statement. You cannot specify the
RPV_VS_AREA option with the RPV or RHO option.

Examples
VIA via1 {FROM=M1 TO=M2 RHO=0.263}
CONDUCTOR M1 {THICKNESS=0.4 SMIN=0.15 WMIN=0.18 RHO=0.8}

See Also
RHO_VS_SI_WIDTH_AND_THICKNESS

RHO_VS_WIDTH_AND_SPACING

RPV

RPV_VS_AREA

RPV_VS_COVERAGE

RPV_VS_WIDTH_AND_LENGTH

Conventional ITF Syntax Specification 2-94


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RHO_VS_SI_WIDTH_AND_THICKNESS
Models resistivity as a function of silicon width and thickness of the conductor.

Syntax
RHO_VS_SI_WIDTH_AND_THICKNESS {
WIDTH { w1 w2 w3 }
THICKNESS { t1 t2 t3 }
VALUES { v(w1,t1) v(w1,t2) v(w1,t3)
v(w2,t1) v(w2,t2) v(w2,t3)
v(w3,t1) v(w3,t2) v(w3,t3)

}
}

Arguments

Argument Description

w1 w2 w3 Silicon widths of the conductor


Units: microns

t1 t2 t3 Silicon thicknesses of the conductor


Units: microns

v(w1,t1) v(w1,t2) v(w1,t3) Resistivity values for the corresponding widths and
thicknesses

Description
The RHO_VS_SI_WIDTH_AND_THICKNESS option models resistivity as a function of silicon
width and thickness. Specify the RHO_VS_SI_WIDTH_AND_THICKNESS option within a
CONDUCTOR statement.

You can define the THICKNESS values before the WIDTH values; however, the mapping of the
resistivity values remains the same regardless of the order of the WIDTH and THICKNESS
definitions.

Chapter 2: Conventional ITF Syntax Specification


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Examples
RHO_VS_SI_WIDTH_AND_THICKNESS {
WIDTH {0.1 0.2 0.3 0.4}
THICKNESS {0.11 0.22 0.33 0.44}
VALUES { 0.304 0.410 0.518 0.640
0.210 0.340 0.438 0.560
0.504 0.530 0.618 0.720
0.604 0.710 0.818 0.940
}
}

See Also
ETCH

ETCH_VS_WIDTH_AND_SPACING

POLYNOMIAL_BASED_THICKNESS_VARIATION

RESISTIVE_ONLY_ETCH

RPSQ_VS_SI_WIDTH

RPSQ_VS_WIDTH_AND_SPACING

THICKNESS_VS_DENSITY

THICKNESS_VS_WIDTH_AND_SPACING

Conventional ITF Syntax Specification 2-96


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RHO_VS_WIDTH_AND_SPACING
Models the RHO variation with respect to width and spacing. Valid within a CONDUCTOR block.

Syntax
RHO_VS_WIDTH_AND_SPACING
SPACINGS {s1 s2}
WIDTHS {w1 w2 w3}
VALUES {v(s1 w1) v(s2 w1)
v(s1 w2) v(s2 w2)
v(s1 w3) v(s2 w3)
}

Arguments

Argument Description

SPACINGS {} A list of spacings to the nearest CONDUCTOR


Units: microns

WIDTHS {} A list of widths of the nearest CONDUCTOR


Units: microns

VALUES {} A list of the RHO values for the corresponding width and spacing

Description
Specify this option within a CONDUCTOR statement to model the RHO variation with respect to
width and spacing.
The RHO_VS_WIDTH_AND_SPACING option cannot be used in conjunction with RHO, RPSQ,
RPSQ_VS_WIDTH_AND_SPACING, or multiple ETCH_VS_WIDTH_AND_SPACING tables.

See Also
ETCH_VS_WIDTH_AND_SPACING

RHO

RPSQ_VS_WIDTH_AND_SPACING

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RPSQ
Specifies the resistance per square (RPSQ) of a conductor layer.

Syntax
RPSQ = rpsq_value

Arguments

Argument Description

rpsq_value Resistance per square of the conducting layer


Default: 0
Units: ohms/square

Description
RPSQ is the resistance per square of a conductor. You can specify the resistive properties
of conductor layers in terms of either resistance per square or resistivity.

Examples
CONDUCTOR metal1 {
RESISTIVE_ONLY_ETCH=0.05 THICKNESS=0.66
WMIN=0.15 SMIN=0.15 RPSQ=0.078
}

See Also
RHO

RPSQ_VS_SI_WIDTH

RPSQ_VS_WIDTH_AND_SPACING

Conventional ITF Syntax Specification 2-98


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RPSQ_VS_SI_WIDTH
Defines the nonlinear relation of resistance per square (RPSQ) of the measured silicon
width.

Syntax
RPSQ_VS_SI_WIDTH {(SIW1, R1) (SIW2, R2) (SIWn, Rn)}

Arguments

Argument Description

SIWn The nth measured width of the conductor


Units: microns

Rn RPSQ of the conductor at silicon width SIWn


Units: ohms/square

Description
The RPSQ_VS_SI_WIDTH table defines the nonlinear relation of resistance per square
(RPSQ) of the measured silicon width because of process effects such as cladding and
dishing. The first entry of SIW does not have to be the same as WMIN.
This option cannot be used with RPSQ, RHO, or RPSQ_VS_WIDTH_AND_SPACING.

Examples
This example specifies a varying RPSQ value with respect to the measured width.
CONDUCTOR MET1 {
THICKNESS=0.6 WMIN=0.34 SMIN=0.40
RPSQ_VS_SI_WIDTH {
(0.34, 0.075) (0.40, 0.062)
(0.823, 0.0817)(2.0, 0.0321)
(6.0,0.0173)
}
}

See Also
RPSQ

RPSQ_VS_WIDTH_AND_SPACING

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RPSQ_VS_WIDTH_AND_SPACING
Specifies the resistance per square (RPSQ) for different conductor widths and spacings.

Syntax
RPSQ_VS_WIDTH_AND_SPACING {
SPACINGS {s1 s2 s3 }
WIDTHS {w1 w2 w3 }
VALUES {v(s1,w1) v(s2,w1)
v(s1,w2) v(s2,w2)
}
}

Arguments

Argument Description

SPACINGS {} A list of spacings to the nearest CONDUCTOR.


Units: microns

WIDTHS {} A list of widths of the nearest CONDUCTOR


Units: microns

VALUES {} A list of the RPSQ values for the corresponding width and spacing
Units: ohms per square

Description
The RPSQ_VS_WIDTH_AND_SPACING table models the effect of different conductor widths and
spacings on RPSQ. Use this table to model process effects such as conductor cladding or
dishing. The first entry of SPACINGS and WIDTHS should be the same as SMIN and WMIN,
respectively.
Specify the RPSQ_VS_WIDTH_AND_SPACING table within a CONDUCTOR block. Do not use this
option in conjunction with multiple ETCH_VS_WIDTH_AND_SPACING tables.

Examples
CONDUCTOR m1 {
THICKNESS = 0.6 WMIN = 0.25 SMIN = 0.25
RPSQ_VS_WIDTH_AND_SPACING {
SPACINGS {0.25 0.3}
WIDTHS {0.25 0.3}
VALUES {0.1 0.05 0.05 0.01} }
}
}

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See Also
ETCH_VS_WIDTH_AND_SPACING

RPSQ

RPSQ_VS_SI_WIDTH

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RPV
Specifies the resistive properties of a via layer.

Syntax
RPV = rpv_value

Arguments

Argument Description

rpv_value Resistance per default via


Units: ohms

Description
The resistive properties of the via layer must be specified. The via layers can be specified in
three ways: RHO, RPV and AREA, or RPV_VS_AREA. However, only one specification method is
required.
If RPV is specified, then AREA is required.
The default of RPV is such that RPV x AREA = 1-0e-6.
You specify this option within a VIA statement. You cannot specify RPV_VS_AREA together
with RPV or RHO in the same VIA statement.

Examples
VIA via1 {
FROM=m1 TO=m2 AREA=0.5 RPV=4
}

See Also
RHO

RPV_VS_AREA

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RPV_VS_AREA
Specifies the resistance per via (RPV) for different via areas.

Syntax
RPV_VS_AREA {
(area1, rpv1)
(area2, rpv2)
(area3, rpv3)

}

Arguments

Argument Description

area Via or contact area


Units: square microns

rpv Resistance per via or contact specified


Units: ohms

Description
You can use a RPV_VS_AREA table in a VIA block to specify the via resistance for different via
sizes. There is no limit to the number of entries you can specify. You cannot specify
RPV_VS_AREA together with RPV or RHO in the same VIA definition.

If the actual via area falls between two area entries in the RPV_VS_AREA table, linear
interpolation is used to calculate the RPV value.
If the actual via area is less than the smallest area entry in the RPV_VS_AREA table, the
conductivity of the via with the smallest area entry is used to calculate the via resistance
for any vias with smaller areas.
If the actual via area is greater than the largest area entry in the RPV_VS_AREA table, the
conductivity of the via with the largest area entry is used to calculate the via resistance
for any vias with larger areas.

Examples
VIA via1 {
FROM=m1 TO=m2
RPV_VS_AREA { (200, 0.5) (350, 0.5) (600, 0.25) }
}

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RPV_VS_COVERAGE
Specifies resistance per via values with respect to via size, upper layer coverage, and lower
layer coverage. Valid within a VIA block.

Syntax
RPV_VS_COVERAGE [UPPER_LAYER_ONLY] {
VIA_SIZE {sx1 sy1}
COV_X { cx1, cx2, cxm }
COV_Y { cy1, cy2, cyn }
VALUES {r(cx1,cy1) r(cx1,cy2) r(cx1,cyn)
r(cx2,cy1) r(cx2,cy2) r(cx2,cyn)
...
r(cxm,cy1) r(cxm,cy2) ... r(cxm,cyn)
}
[VIA_SIZE {sx2 sy2}
COV_X { dx1, dx2, dxm }
COV_Y { dy1, dy2, dyn }
VALUES {r(dx1,dy1) r(dx1,dy2) r(dx1,dyn)
r(dx2,dy1) r(dx2,dy2) r(dx2,dyn)
...
r(dxm,dy1) r(dxm,dy2) ... r(dxm,dyn)
}
]

}

Arguments

Argument Description

UPPER_LAYER_ONLY Optional keyword restricting the coverage check to the upper layer

sx1 sy1 Via size in the x- and y-dimensions (as-drawn dimensions)


Units: microns

cx1, cx2, X-direction coverage values, in ascending order; coverage values


dx1, dx2, for different via sizes do not have to match
Uunits: microns

cy1, cy2, Y-direction coverage values, in ascending order; coverage values


dy1, dy2, for different via sizes do not have to match
Uunits: microns

r(cx1,cy1) Resistance per via (RPV) for the corresponding coverage values
r(dx1,dy1) Units: ohms

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Description
The RPV_VS_COVERAGE command specifies resistance per via (RPV) values based on the
via size and the amount of upper and lower conductor layer coverage.
The RPV_VS_COVERAGE command block contains one or more tables of RPV values. Each
table applies to a specific via size based on the drawn dimension, without taking etch into
account. The via dimensions must match exactly; however, the x- and y-dimensions can be
rotated by 90 degrees. When rotation is required to match the via size, the table indexes and
values are also rotated.
If a via does not match any of the via sizes specified in the RPV_VS_COVERAGE command, the
RPV_VS_AREA command is used to determine the via resistance.

If a via exactly matches a via size specified by a VIA_SIZE keyword in the


RPV_VS_COVERAGE command, the via resistance is determined using the following
procedure:
1. Find the enclosing shape that covers the via
Perform a Boolean AND operation of the upper conductor layer and lower conductor
layer to get the enclosing shape that covers the via, as shown in Figure 2-15.
You can optionally use only the upper layer for the coverage check by specifying the
UPPER_LAYER_ONLY keyword immediately after the RPV_VS_COVERAGE command.

2. Decompose the enclosing shape into rectangles


A complex enclosing shape can be viewed as a set of overlapping boxes, as shown in
Figure 2-16.
3. Select one coverage box
If multiple coverage boxes fit within the enclosing shape, the box with the largest
minimum dimension is selected, as shown in Figure 2-16.
If multiple coverage boxes have the same minimum dimension values, the box with the
largest maximum dimension is selected. An example is shown in Figure 2-17.
4. Look up or calculate the resistance value
The dimensions of the selected coverage box are compared to the COV_X and COV_Y
values. If the dimensions match exactly, the COV_X and COV_Y values are used as
indexes to look up the resistance value in the VALUES table.
If the selected coverage box dimensions are within the range of available COV_X and
COV_Y values but do not match exactly, interpolation between available values is used to
calculate the resistance.
If the selected coverage box dimensions are outside the range of available COV_X and
COV_Y values, use the smallest via resistance value if the box is too small and the largest
resistance value if the box is too big.

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Figure 2-15 Via Coverage Enclosing Shape

Upper layer metal

Via

Lower layer metal

Enclosing shape
(region used for
coverage check)

Figure 2-16 Coverage Rule Selection Example 1

3 Box B has the largest minimum dimension.

Box A: X=3, Y=0.5


2 0.5

Box B: X=1, Y=2

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Figure 2-17 Coverage Rule Selection Example 2

2 Box A has the largest


maximum dimension.

Box A: X=2, Y=0.5


0.5 Box B: X=1, Y=0.5

Example
The following example provides tables for two via sizes:
RPV_VS_COVERAGE {
VIA_SIZE { 0.032 0.032 }
COV_X { 0.064, 0.096, 0.2 }
COV_Y { 0.064, 0.096, 0.2 }
VALUES { 18 20 25 21 26 30 27 32 35 }
VIA_SIZE { 0.064 0.64 }
COV_X { 0.064, 0.096, 0.2 }
COV_Y { 0.064, 0.096, 0.2 }
VALUES { 6 8 13 9 14 18 15 20 23 }
}

See Also
RPV_VS_AREA

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RPV_VS_SI_WIDTH_AND_LENGTH
Models the resistivity of a trench contact virtual via according to the silicon width and length
of one of the associated trench contact conductor layers. Valid within a VIA block.

Syntax
ETCH_ASSOCIATED_LAYER = tc_layer
RPV_VS_SI_WIDTH_AND_LENGTH {
LENGTHS { l1 l2 l3 lm }
WIDTHS { w1 w2 w3 wn }
VALUES { r(l1,w1) r(l2,w1) r(l3,w1) r(lm,w1)
r(l1,w2) r(l2,w2) r(l3,w2) r(lm,w2)

r(l1,wn) r(l2,wn) r(l3,wn) r(lm,wn)
}
}

Arguments

Argument Description

tc_layer Either the FROM or TO layer in the VIA definition; must be


a trench contact layer defined with the
LAYER_TYPE=TRENCH_CONTACT statement

l1, l2, ... Via lengths, in ascending order


Units: microns

w1, w2, ... Via widths, in ascending order


Units: microns

r(l1,w1), r(l2,w1), ... Resistance per via


Units: ohms

Description
In trench contact layers, electrical current flows both along the routing direction and in the
vertical direction. As a result, the contact resistance behavior can be complex.
You can model the vertical current flow as follows:
Use the VIA statement to define a virtual via between two trench contact layers or
between a trench contact layer and another conductor layer.
To specify the variation of via resistance with respect to drawn length and width
dimensions, use the RPV_VS_WIDTH_AND_LENGTH statement within the via definition.

Conventional ITF Syntax Specification 2-108


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To specify the variation of via resistance with respect to silicon length and width
dimensions (in other words, the dimensions after applying etch operations), use the
RPV_VS_SI_WIDTH_AND_LENGTH statement within the via definition.

Figure 2-18 shows a trench contact layer and the virtual via that connects it to the diffusion
layer. The length dimension of the trench contact is parallel to the length dimension of the
gate.
Figure 2-18 As-Drawn Trench Contact Virtual Via

diffusion gate trench contact

Top View
width

length

trench contact
virtual via
Side View diffusion

Figure 2-19 shows how a trench contact conductor layer might be changed after an etch
operation. For accurate modeling, the trench contact virtual via dimensions must match the
post-etch (silicon) dimensions of the FROM or TO layers associated with the via. The
ETCH_ASSOCIATED_LAYER keyword specifies which of the two layers the virtual via
dimensions should match.

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Figure 2-19 Post-Silicon Trench Contact Virtual Via

trench contact
Drawn layout
virtual via
diffusion

trench contact
Effect of etch on
virtual via
trench contact layer
diffusion

Adjustment of trench contact


virtual via based on virtual via
trench contact layer
diffusion

If you want to use the drawn dimensions of the virtual via instead of the silicon dimensions,
use the RPV_VS_WIDTH_AND_LENGTH statement in the via definition instead of the
RPV_VS_SI_WIDTH_AND_LENGTH statement.

Example
In the following example, the trench contact virtual via VTC is defined between layers POD
and M0. The via dimensions are set to match the dimensions of layer M0 after the
application of the etch operation defined by the ETCH_VS_WIDTH_AND_SPACING command.
CONDUCTOR M0 {THICKNESS=0.9 WMIN=0.09 SMIN=0.09 LAYER_TYPE=TRENCH_CONTACT
ETCH_VS_WIDTH_AND_SPACING { }
}
VIA VTC { FROM=POD TO=M0
ETCH_ASSOCIATED_LAYER = M0
RPV_VS_SI_WIDTH_AND_LENGTH {
LENGTHS { 0.03 0.04 0.08 0.12 0.6 }
WIDTHS { 0.02 0.03 0.04 }
VALUES {
360 160 80 60 22
260 90 80 50 21
200 80 70 40 20
}
}
}

See Also
VIA

RPV_VS_WIDTH_AND_LENGTH

Conventional ITF Syntax Specification 2-110


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RPV_VS_WIDTH_AND_LENGTH
Models the resistivity of a trench contact virtual via according to the drawn width and length
of one of the associated trench contact conductor layers. Valid within a VIA block.

Syntax
RPV_VS_WIDTH_AND_LENGTH {
LENGTHS { l1 l2 l3 lm }
WIDTHS { w1 w2 w3 wn }
VALUES { r(l1,w1) r(l2,w1) r(l3,w1) r(lm,w1)
r(l1,w2) r(l2,w2) r(l3,w2) r(lm,w2)

r(l1,wn) r(l2,wn) r(l3,wn) r(lm,wn)
}
}

Arguments

Argument Description

l1, l2, Via lengths, in ascending order (units: microns)

w1, w2, Via widths, in ascending order (units: microns)

r(l1,w1), r(l2,w1), Resistance per via or RPV (units: ohms)

Description
In trench contact layers, electrical current flows both along the routing direction and in the
vertical direction. You can model the vertical current flow as follows:
Use the VIA statement to define a virtual via between two trench contact layers or
between a trench contact layer and another conductor layer.
To specify the variation of via resistance with respect to drawn length and width
dimensions, use the RPV_VS_WIDTH_AND_LENGTH statement within the via definition.
To specify the variation of via resistance with respect to silicon length and width
dimensions (in other words, the dimensions after applying etch operations), use the
RPV_VS_SI_WIDTH_AND_LENGTH statement within the via definition.

The resistance of the virtual via is dependent on its length and width. If the top conductor
layer is affected by etch operations, the virtual via size should also change to match the final
silicon dimensions of the conductor layer. To use the silicon dimensions instead of the drawn
dimensions, use the RPV_VS_SI_WIDTH_AND_LENGTH statement instead of the
RPV_VS_WIDTH_AND_LENGTH statement.

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Figure 2-20 shows a trench contact layer and the virtual via that connects it to the diffusion
layer. The length dimension of the trench contact is parallel to the length dimension of the
gate.
Figure 2-20 As-Drawn Trench Contact Virtual Via

diffusion gate trench contact

Top View
width

length

trench contact
virtual via
Side View diffusion

Example
In the following example, the trench contact virtual via VTC is defined between layers POD
and M0. The via dimensions are the as-drawn dimensions and are not changed by any etch
operations on the associated conductors.
VIA VTC { FROM=POD TO=M0 }
RPV_VS_WIDTH_AND_LENGTH {
LENGTHS { 0.02 0.04 0.05 }
WIDTHS {0.01]
VALUES { 100 80 60 }
}

See Also
VIA

RPV_VS_SI_WIDTH_AND_LENGTH

Conventional ITF Syntax Specification 2-112


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SIDE_TANGENT
Specifies the tangent of an angular shift from vertical of the conductor sides.

Syntax
SIDE_TANGENT = tan_value

Arguments

Argument Description

tan_value Tangent value


Default: 0

Description
The SIDE_TANGENT option specifies the tangent of an angular shift from vertical of the
conductor sides, as shown in Figure 2-21.
Figure 2-21 Effect of the SIDE_TANGENT Option
Before After
o o
20 20
W_center W_center

o o
-20 -20

Figure 2-22 Positive Versus Negative SIDE_TANGENT Values


o
-20 o
+20
W_center
W_center

Negative SIDE_TANGENT Positive SIDE_TANGENT

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If you specify a positive value for SIDE_TANGENT, a trapezoid is produced with a top width
larger than the center width. If W denotes the width of the conductor without any trapezoidal
enhancement, and t is the vertical thickness of the conducting layer, then:
W_top = W + (SIDE_TANGENT * t)
W_bottom = W - (SIDE_TANGENT * t)
W_center = W
t = conductor thickness

The center width (W_center) is not affected by the trapezoidal adjustment. Also note that the
trapezoidal cross section is effectively a capacitive effect because the cross sectional area
does not change if top and bottom widths are greater than or equal to zero.

Examples
This example shows how you can specify that the conductor has a 20 degree angular shift
(tan 20=0.364).
CONDUCTOR met4 {
SIDE_TANGENT=0.364 THICKNESS=0.66 WMIN=0.15
SMIN=0.15 RPSQ=0.078
}

See Also
ETCH_VS_WIDTH_AND_SPACING

Conventional ITF Syntax Specification 2-114


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SMIN
Specifies the minimum spacing between two geometries of this conductor layer.

Syntax
SMIN = spacing_value

Arguments

Argument Description

spacing_value Minimum spacing value


Units: microns

Description
The SMIN option specifies the minimum spacing between two geometries of this conductor
layer.
Specify this option within a CONDUCTOR statement.

Examples
CONDUCTOR m1 {
THICKNESS=1.00 WMIN=0.13 SMIN=0.15 RPSQ=0.015
}

See Also
WMIN

Chapter 2: Conventional ITF Syntax Specification


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SPACER_ER_VS_WIDTH_AND_SPACING
Specifies relative permittivity values as a function of gate width and gate-to-contact spacing
for tuning of coupling capacitance. Valid within a DIELECTRIC block for conformal dielectrics.

Syntax
SPACER_ER_VS_WIDTH_AND_SPACING {
SPACINGS { s1 s2 sm }
WIDTHS { w1 w2 wn }
VALUES { er(s1,w1) er(s2,w1) er(sm,w1)
er(s1,w2) er(s2,w2) er(sm,w2)

er(s1,wn) er(s2,wn) er(sm,wn)
}
}

Arguments

Argument Description

s1 s2 sm Gate to contact spacings specified in ascending order


Units: microns

w1 w2 wn Gate widths specified in ascending order


Units: microns

er(s1,w1) er(sm,wn) Relative permittivity for corresponding index values


Units: none

Description
Specify the SPACER_ER_VS_WIDTH_AND_SPACING option within a DIELECTRIC block to vary
the relative permittivity of conformal dielectrics. This option is most commonly used to
modify coupling capacitance values rather than to model true physical effects.
The specified gate width and gate-to-contact spacing values are used as indexes for the
two-dimensional table of relative permittivity values. Each combination of length s and width
w has a corresponding relative permittivity value er(s,w).

Conventional ITF Syntax Specification 2-116


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This keyword can only be used in a DIELECTRIC block that also include the following
keywords:
An ASSOCIATED_CONDUCTOR keyword specifying a conductor layer whose definition
includes a LAYER_TYPE keyword set to a value of GATE
An IS_CONFORMAL keyword

Figure 2-23 shows the gate width and gate-to-contact spacing values required for the
WIDTHS and SPACINGS lists.

Figure 2-23 Index Dimension Definitions

gate-to-
contact
spacing
gate width w s

polysilicon spacer conductor M0

Example
In the following example, when the gate width is 0.1 and the spacing is 0.4, the relative
permittivity is 3.1. When the gate width is 0.1 and the spacing is 1.2, the relative permittivity
is 2.8.
SPACER_ER_VS_WIDTH_AND_SPACING {
SPACINGS { 0.1 0.2 }
WIDTHS { 0.4 1.0 1.2 }
VALUES { 3.1 3.2 3.4 3.5 2.8 2.6 }
}

See Also
DIELECTRIC

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SW_T
Defines the sidewall thickness of a conformal layer.

Syntax
SW_T = thickness_value

Arguments

Argument Description

thickness_value The sidewall thickness


Units: microns
Default: dielectric THICKNESS value

Description
SW_T=0 is allowed for conformal dielectrics. If not specified, the thickness of the dielectric is
used for the SW_T value.

Examples
DIELECTRIC D3 {
THICKNESS = 0.2
MEASURED_FROM = TOP_OF_CHIP
SW_T = 0.15
TW_T = 0.18
ER = 5.9
}

See Also
MEASURED_FROM

THICKNESS

TW_T

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TECHNOLOGY
Specifies the name of the process technology for tracking and identification purposes.

Syntax
TECHNOLOGY = process_name

Arguments

Argument Description

process_name The process name represented by a single word that can contain
alphanumeric characters and underscores

Description
The TECHNOLOGY statement is mandatory and should precede all other statements, but it
does not need to be the first line of the ITF.

Examples
In the following example, the process name is example_tech:
TECHNOLOGY = example_tech

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THICKNESS
Specifies the thickness of a dielectric or conductor layer.

Syntax
THICKNESS = thk_value

Arguments

Argument Description

thk_value The thickness of the dielectric or conductor


Units: microns

Description
The dielectric or conductor thickness measured from the top of the dielectric layer below it.
The reference point can be changed by using the MEASURED_FROM statement. Specifying
THICKNESS=0 is allowed for a conformal dielectric layer; for planar layers THICKNESS should
not be set to 0.
Specify this option within a CONDUCTOR or DIELECTRIC statement.

Examples
CONDUCTOR M2 { THICKNESS=0.60 WMIN=0.55 SMIN=0.50 RPSQ=0.062 }
DIELECTRIC D2 { THICKNESS=1.20 ER=3.9 }

See Also
MEASURED_FROM

THICKNESS

Conventional ITF Syntax Specification 2-120


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THICKNESS_VS_DENSITY
Models the thickness of a conductor as a function of its density. Valid within a CONDUCTOR
block.

Syntax
THICKNESS_VS_DENSITY [ RESISTIVE_ONLY | CAPACITIVE_ONLY ]
{(D1 R1) (D2 R2) (D3 R3) (D4 R4) }

Arguments

Argument Description

RESISTIVE_ONLY Applies thickness adjustment to resistance only

CAPACITIVE_ONLY Applies thickness adjustment to capacitance only

D1, D2, D3, D4, Density value

R1, R2, R3, R4, Relative change in thickness (dT/dTnominal)


A negative R value indicates a decrease in thickness; positive R
indicates a thickness increase. The value of R must be between
-1 and 1 (not inclusive). Values close to 1 or -1 are undesirable.

Description
In chemical-mechanical polishing (CMP) processes, the density of features in the vicinity of
a specific feature affects the amount of polishing that the feature receives. The
THICKNESS_VS_DENSITY option provides two methods for density-based conductor
thickness computation: the single box (linear table) method or the multiple box method. The
box refers to the area around the feature in question within which the average feature
density is calculated.
The values in a density-relative thickness pair can be separated by either a comma or
space.
Thickness variation affects both resistance and capacitance. However, you can use different
coefficients for resistance and capacitance calculations by using the RESISTIVE_ONLY or
CAPACITANCE_ONLY options.

The two methods are as follows:


Single-box method (default method)
The box is square with a default size of 50 microns. To specify a different size box, use
the DENSITY_BOX_WEIGHTING_FACTOR option.

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For a linear table model, specify a multipoint thickness variation versus the density table
in the process file.
Multiple-Box Method
To specify a multiple box size and its weighting factor for effective density calculation,
you must characterize the wafer in greater detail than you do in the single box method.
This method is preferred when the single box method does not represent the process
behavior. The density box is a square. T

Examples
The following example shows the single-box method:
CONDUCTOR metal3 {
THICKNESS=0.5 SMIN=0.25 WMIN=0.25 RPSQ=0.01
THICKNESS_VS_DENSITY RESISTIVE_ONLY
{(0.1,-0.1) (0.2, 0.1)(0.3, 0.2)(0.4, 0.3)}
}

The following example shows the multiple-box method:


CONDUCTOR metal3 {
THICKNESS = 0.5 SMIN = 0.25 WMIN=0.25 RPSQ = 0.01
THICKNESS_VS_DENSITY{(0.1 -0.1)(0.2 0.1)(0.3 0.2)(0.4 0.3)}
DENSITY_BOX_WEIGHTING_FACTOR {
(10 1) (20 0.23) (30 0.29)
(40 0.18) (50 -0.12)
}
}

See Also
DENSITY_BOX_WEIGHTING_FACTOR

THICKNESS_VS_WIDTH_AND_SPACING

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THICKNESS_VS_WIDTH_AND_SPACING
Models the thickness of a conductor as a function of its width and spacing.

Syntax
THICKNESS_VS_WIDTH_AND_SPACING
[ RESISTIVE_ONLY | CAPACITIVE_ONLY ] {
SPACINGS { S1 S2 }
WIDTHS ( W1 W2 }
VALUES { v(S1,W1) v(S2,W1) v(S1,W2) v(S2,W2) }
}

Arguments

Argument Description

RESISTIVE_ONLY Applies thickness adjustment to resistance only

CAPACITIVE_ONLY Applies thickness adjustment to capacitance only

SPACINGS Spacing values specified in ascending order


Units: microns

WIDTHS Width of a conductor. Values are specified in ascending order


Units: microns

VALUES Values represent the relative change in thickness for a conductor. Order of
the components of the values table is determined by the indexes in the
SPACINGS an WIDTHS table. Entry in the VALUES table are ordered such that
SPACINGS indexes change first for a given index in the WIDTHS table and
then this is repeated for all indexes in the WIDTHS table.

Description
In this method, the variation of thickness as a function of the width of a conductor and
relative spacing to the neighboring conductor is modeled. The variation is modeled in an ITF
with THICKNESS_VS_WIDTH_AND_SPACING specified as a keyword in a CONDUCTOR definition.
This thickness variation can be either negative or positive. It is a very local phenomenon and
is independent of the density box. If specified with either single or multiple boxes, then this

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thickness variation is computed independently from the density box. The effective thickness
is calculated with the following equation:

T = Tnom ( 1 + RTf(Deff) + RTf(W, S) + RTf(SiW) )

In this equation,
Tnom is the nominal thickness specified in the ITF.
RTf(Deff) is the relative thickness change due to density.
RTf(W,S) is the relative change in thickness due to width and spacing.
RTf(SiW) is the relative change in thickness due to silicon width.

Examples
CONDUCTOR m1 {
THICKNESS = 0.60 WMIN 0.25 SMIN = 0.25
THICKNESS_VS_WIDTH_AND_SPACING {
SPACINGS { 0.25 0.30 0.50}
WIDTHS {0.25 0.4 0.50}
VALUES {0.3 0.2 0.1
0 -0.1 -0.20
-0.3 -0.2 -0.1}
}
}

See Also
DENSITY_BOX_WEIGHTING_FACTOR

THICKNESS_VS_DENSITY

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TO
Specifies a conductor layer connected by a via. Valid within a VIA block.

Syntax
TO = layer

Arguments

Argument Description

layer The layer connected by the defined via

Description
The TO option specifies the upper or lower layer connected by a via. A via can only connect
two conductor layers.

Examples
VIA v1 {
FROM = m2
TO = m3
RPV = 40
AREA = 0.16
}

See Also
FROM

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TSV
Describes a through-silicon via (TSV) layer.

Syntax
TSV tsv_name {
FROM = layer1
TO = layer2
RHO = rho_value
AREA = area_value
THICKNESS = thickness_value
INSULATION_THICKNESS = ins_thickness_value
INSULATION_ER = er_value
[CRT1 = lin_coeff] [CRT2 = quad_coeff] [T0 = nominal_temp]
CSUB_VS_SPACING { (s1, v1) (s2, v2) (sn, vn)}
RSUB_VS_SPACING { (s1, v1) (s2, v2) (sn, vn)}
}

Arguments

Argument Description

FROM = layer1 Conductor layer connected by the TSV

TO = layer2 Conductor layer connected by the TSV

RHO = rho_value Resistivity of the TSV


Units: ohm-microns

AREA = area_value Area of the TSV


Units: square microns

THICKNESS = Thickness of the TSV


thickness_value Units: microns

INSULATION_THICKNESS = Thickness of the insulation layer between the TSV and the
ins_thickness_value substrate
Units: microns

INSULATION_ER = er_value Relative permittivity of the TSV insulation layer

CRT1 = lin_coeff Layer-specific linear temperature coefficient


Default: 0

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Argument Description

CRT2 = quad_coeff Layer-specific quadratic temperature coefficient


Default: 0

T0 = nominal_temp Nominal temperature for the layer


Units: degrees Celsius
Default: temperature specified by GLOBAL_TEMPERATURE

CSUB_VS_SPACING (sn,vn) Defines the distance and substrate-related capacitance between


one through-silicon via and its neighboring through-silicon via.
You can specify a maximum of eight neighboring through-silicon
vias.
Units: microns

RSUB_VS_SPACING (sn,vn) Defines the distance and substrate-related resistance between


one through-silicon via and its neighboring through-silicon via.
You can specify a maximum of eight neighboring through-silicon
vias.
Units: microns

Description
A through-silicon via (TSV) connects metal conductor layers on the frontside and the
backside of the silicon substrate, as shown in Figure 2-24.

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Figure 2-24 Cross Section of Through-Silicon Via

FRONT
insulation TSV
thickness thickness
SUBSTRATE
TSV insulator

ILDB
BACK
PASS

insulating layers through-silicon via substrate

device layers TSV insulator passivation

M1 backside metal

To model a through-silicon via, you must include descriptions of the frontside and backside
layers in the ITF file. The syntax of each ITF stack, either the frontside or the backside,
follows the same ITF syntax. Place the TSV statement after the frontside ITF statements and
before the backside ITF statements.
The substrate effect should be considered when using high frequencies. Specify the
substrate-related RC network using CSUB_VS_SPACING and RSUB_VS_SPACING options.

Examples
TSV tsv {
FROM=M1 TO=M1b
RHO=0.05 AREA=49.0 THICKNESS=20.0
INSULATION_THICKNESS=0.4 INSULATION_ER=5.5
CRT1=7.0e-03 CRT2=-3.0e-08 }

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TVF_ADJUSTMENT_TABLES
Specifies tables to adjust the bottom thickness variation.

Syntax
TVF_ADJUSTMENT_TABLES {
[BOTTOM_THICKNESS_VS_WIDTH_AND_SPACING {
SPACINGS { S1 S2 }
WIDTHS { W1 W2 }
VALUES { V(S1, W1) V(S2, W1)
V(S1, W2) V(S2, W2)
}
}]
[BOTTOM_THICKNESS_VS_WIDTH_AND_DELTAPD {
DELTAPD { D1 D2 }
WIDTHS { W1 W2 }
VALUES { V(D1, W1) V(D2, W1)
V(D1, W2) V(D2, W2)
}
}]
}

Description
The TVF_ADJUSTMENT_TABLES option specifies tables to adjust the bottom thickness
variation based on a separately provided thickness variation file.
The TVF_ADJUSTMENT_TABLES option allows the specification of one or both the following
tables:
BOTTOM_THICKNESS_VS_WIDTH_AND_SPACING Bottom thickness adjustment based on
the conductor width and the nearest spacing.
BOTTOM_THICKNESS_VS_WIDTH_AND_DELTAPD Bottom thickness adjustment based on
the conductor width and the neighboring tiles pattern density (PD).

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Examples
An example is as follows:
CONDUCTOR M1 {

TVF_ADJUSTMENT_TABLES {
BOTTOM_THICKNESS_VS_WIDTH_AND_SPACING {
SPACINGS { 0.100000 0.200000 0.300000 }
WIDTHS { 0.060000 0.120000 0.240000 }
VALUES { 0.500000 0.150000 0.250000
0.100000 0.250000 0.350000
0.150000 0.350000 0.450000
}
}
BOTTOM_THICKNESS_VS_WIDTH_AND_DELTAPD {
DELTAPD { -0.750000 -0.500000 0.000000 0.500000 0.750000 }
WIDTHS { 0.060000 0.120000 0.240000 }
VALUES { 0.150000 0.500000 0.000000 -0.500000 -0.150000
0.150000 0.500000 0.000000 -0.500000 -0.150000
0.150000 0.500000 0.000000 -0.500000 -0.150000
}
}
}
}

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TW_T
Defines the topwall thickness of a conformal layer.

Syntax
TW_T = thickness_value

Arguments

Argument Description

thickness_value Topwall thickness


Units: microns
Default: thickness value of the dielectric

Description
The TW_T parameter defines the topwall thickness of a conformal layer. TW_T=0 is allowed
for conformal dielectrics. If not specified, the THICKNESS of the dielectric is used.

Examples
DIELECTRIC D3 {
THICKNESS=0.2 MEASURE_FROM=TOP_OF_CHIP
SW_T=0.15 TW_T=0.18 ER=5.9
}

See Also
MEASURED_FROM

SW_T

THICKNESS

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USE_SI_DENSITY
Specifies the density-based thickness variation effect.

Syntax
USE_SI_DENSITY = YES | NO

Arguments

Argument Description

YES Specifies that the thickness variation computation is based on


silicon density.

NO Specifies that the thickness variation computation is based on


drawn (database) density.
This is the default.

Description
Use this optional statement in the ITF when the density-based (THICKNESS_VS_DENSITY or
POLYNOMIAL_BASED_THICKNESS_VARIATION) thickness variation effect applies to silicon
density rather than drawn density.

Examples
USE_SI_DENSITY = YES

See Also
POLYNOMIAL_BASED_THICKNESS_VARIATION

THICKNESS_VS_DENSITY

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VARIATION_PARAMETERS
Defines variation parameters for a variation-aware ITF file.

Syntax
VARIATION_PARAMETERS {
param1 = {(layer, param_type, coeff_of_variation)
(layer, param_type, coeff_of_variation)
(layer, param_type, coeff_of_variation) }
param2 = {(layer, param_type, coeff_of_variation)
(layer, param_type, coeff_of_variation)
(layer, param_type, coeff_of_variation) }

}

Arguments

Argument Description

param Variation parameter name

layer Layer name

coeff_of_variation Coefficient of variation

param_type Type of parameter. THICKNESS, WIDTH, RHO, and ER are supported.

Description
You can create a variation-aware ITF file by appending variation parameters. The format you
specify in the ITF to represent parameter variations is added to the existing nonvariation-
aware ITF file. There is no need for you to modify the process cross section or values in the
nominal ITF file.

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VIA
Describes the properties of a via layer. The syntax depends on the type of via: standard via,
as-drawn trench contact via, or post-etch trench contact via.

Syntax
$ Standard via
VIA via_name {
FROM = layer1
TO = layer2
[CRT1 = lin_coeff
| [CRT2 = quad_coeff]
| [CRT_VS_AREA {}]
| [T0 = nominal_temp]]
RHO = rho_value
| RPV = rpv_value AREA = area_value
| RPV_VS_AREA {}
[RPV_VS_COVERAGE { }]
[ETCH_VS_CONTACT_AND_GATE_SPACINGS CAPACITIVE_ONLY {}
| ETCH_VS_WIDTH_AND_LENGTH CAPACITIVE_ONLY {}]
}

$ Trench contact via using as-drawn dimensions


VIA via_name {
FROM = layer1
TO = layer2
RPV_VS_WIDTH_AND_LENGTH {}
}

$ Trench contact via using post-etch dimensions


VIA via_name {
FROM = layer1
TO = layer2
ETCH_ASSOCIATED_LAYER = tc_layer
RPV_VS_SI_WIDTH_AND_LENGTH {}
}

Arguments

Argument Description

FROM = layer1 Upper conductor layer connected by the via

TO = layer2 Lower conductor layer connected by the via

ETCH_ASSOCIATED_LAYER = Either the FROM or TO layer in the VIA definition; must be a trench
tc_layer contact layer defined with the LAYER_TYPE=TRENCH_CONTACT
statement

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Argument Description

CRT1 = lin_coeff Layer-specific linear temperature coefficient


Default: 0

CRT2 = quad_coeff Layer-specific quadratic temperature coefficient


Default: 0

T0 = nominal_temp Nominal temperature for the layer


Units: degrees Celsius
Default: temperature specified by GLOBAL_TEMPERATURE

RHO = rho_value Bulk resistivity of the via or conductor layer


Units: ohm-microns
Default: RPV x AREA

RPV = rpv_value Resistance per default via


Units: ohms

AREA = area_value Area of default via


Units: square microns)
Default: 1.0e -6 / RPV

Description
The VIA statement describes the properties of a via layer. The syntax depends on the type
of via, as follows:
Standard via
Most vias use this format. You must specify the two layers connected by the via and the
basic resistive properties of the via. In addition, you can specify tables that modify the via
resistance based on size, spacing, or coverage.
Trench contact via
Trench contact vias are artificial layers that enable the correct modeling of current in
trench contact structures. At least one of the connected layers must be a trench contact
layer. Specialized commands define the resistance of trench contact vias.

Examples
The following example is a simple via definition:
VIA VIA1 { FROM=M1 TO=M2 AREA=0.36 RPV=4 }

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The following example defines several properties of a standard via:


VIA NMOS_CONTACT {
FROM = NDIFF TO = M1
AREA = 0.002
RPV = 80.0
CRT1 = 0.003
LAYER_TYPE = DEVICE_CONTACT }

The following example is a trench contact via:


VIA VTC { FROM=POD TO=M0
ETCH_ASSOCIATED_LAYER = M0
RPV_VS_SI_WIDTH_AND_LENGTH {
LENGTHS { 0.03 0.04 0.08 0.12 0.6 }
WIDTHS { 0.02 0.03 0.04 }
VALUES {
360 160 80 60 22
260 90 80 50 21
200 80 70 40 20
}
}
}

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WMIN
Specifies the minimum width of a geometry of this conductor layer. Valid within a CONDUCTOR
block.

Syntax
WMIN = width_value

Arguments

Argument Description

width_value The minimum width of the layer


Units: microns

Description
Minimum width of a conductor geometry on a specific layer.

Examples
CONDUCTOR metal1 {
THICKNESS=1.00 WMIN=0.13 SMIN=0.15 RPSQ=0.015
}

See Also
SMIN

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Conventional ITF Syntax Specification 2-138


3
Electromigration ITF Syntax Specification 3
This chapter describes the ITF syntax that describes electromigration rules. This syntax is
extension of the conventional ITF syntax.
Overview
Including Electromigration Information in the ITF File
ITF-EM Structure
ITF-EM Keywords and Syntax

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Overview
Electromigration (EM) is the transport of material caused by the gradual movement of ions
in a conductor due to the momentum transfer between conducting electrons and diffusing
metal atoms. Electromigration decreases the reliability of integrated circuits (ICs). In the
worst case, electromigration leads to the eventual loss of one or more connections and
intermittent failure of the entire circuit by increasing the metal line resistance or, in extreme
cases, opening the metal line. As the structure size of integrated circuits decreases,
electromigration effects become more significant. However, in modern electronic devices,
ICs rarely fail due to electromigration effects. This is because proper semiconductor design
practices incorporate the effects of electromigration into the IC layout. Nearly all IC design
houses use automated EDA tools to check and correct electromigration problems using
electromigration analysis tools at the transistor level.
Existing electromigration rule formats include the LEF/MW technology file and Advanced
Library Format (ALF). The LEF/MW technology file is the earliest source of electromigration
rules and is part of the place and route technology file. However, only simple
electromigration rules are allowed in a LEF/MW technology file. ALF allows for more
complex rules than LEF/MW files, but is also no longer sufficient for advanced process
technologies.
At advanced process nodes, a single format that integrates device geometry definition with
electrical analysis reduces the effort needed to implement, support and deploy EM analysis.
The Interconnect Technology Format (ITF) offers a unified, general, stable, and extendable
format to natively describe complete electromigration rule sets for advanced process
technologies.

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Including Electromigration Information in the ITF File


Electromigration information is appended to the conventional ITF file. Because ITF-EM rules
are applied to metal and via layers, which are defined by conventional ITF statements, the
ITF-EM rule section must appear after the conventional ITF statements in the ITF file. The
ITF-EM section must begin with the keyword EM_INFORMATION and must end with the paired
keyword END_OF_EM_INFORMATION.
You can include the electromigration information in the following ways:
Specify all of the electromigration information directly in the ITF
EM_INFORMATION
complete_EM_information
END_OF_EM_INFORMATION

Specify all of the electromigration information in an external file that is designated with an
absolute or relative path
EM_INFORMATION
INCLUDE_EM_INFORMATION_FILE = /path/itf_em_info_filename
END_OF_EM_INFORMATION

Specify the electromigration information in both the ITF file and external files
EM_INFORMATION
partial_EM_information
INCLUDE_EM_INFORMATION_FILE = /path/itf_em_info_filename1
[partial_EM_information]
[INCLUDE_EM_INFORMATION_FILE = /path/itf_em_info_filename2]
...
END_OF_EM_INFORMATION

The EM_INFORMATION and END_OF_EM_INFORMATION keywords are ITF keywords, intended


for use only within an ITF file.
Electromigration information can be specified in the same ITF file that contains a process
definition, in a separate EM-specific ITF file, or by a combination of the two methods. If
duplicate electromigration information is given, information read in last supersedes any
previously read information.
Because the ITF parser reads the electromigration information from ITF files in the specified
order, it is important to place each part of the electromigration information in the correct
order to follow association rules.

Chapter 3: Electromigration ITF Syntax Specification


Electromigration ITF Syntax
Including Electromigration Specification
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Example of EM and Process Information in One ITF File


The following example shows electromigration information specified directly in the ITF file:
TECHNOLOGY = SIMPLE
DIELECTRIC TOP { THICKNESS = 3.600 ER = 3.9 }
CONDUCTOR M2 { THICKNESS = 0.250 WMIN = 0.5 SMIN = 0.5 RPSQ = 0.05 }
DIELECTRIC D3 { THICKNESS = 0.300 ER = 3.9 }
CONDUCTOR M1 { THICKNESS = 0.212 WMIN = 0.5 SMIN = 0.5 RPSQ = 0.05 }
DIELECTRIC D2 { THICKNESS = 0.200 ER = 4.2 }
CONDUCTOR POLY{ THICKNESS = 0.100 WMIN = 0.3 SMIN = 0.3 RPSQ = 10.0}
DIELECTRIC D1 { THICKNESS = 0.300 ER = 3.9 }
VIA via1 { FROM=M1 TO=M2 RHO=0.263 }
VIA polyCont { FROM=POLY TO=M1 RHO=0.352 }
VIA diffCont { FROM=SUBSTRATE TO=M1 RHO=0.500 }

EM_INFORMATION $Start of EM section

$ The entire EM information in ITF is specified here


$ and presented in detail in the following subsections.

COMMON_INFO { $COMMON_INFO block


AVERAGE {} $AVERAGE limitation module
RMS {} $RMS limitation module
PEAK {} $PEAK limitation module
}
LAYER { $LAYER block for metal
AVERAGE {}
RMS {}
PEAK {}
}
VIA { $VIA block for via
AVERAGE {}
RMS {}
PEAK {}
}

END_OF_EM_INFORMATION $End of EM section

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Example of EM and Process Information in Separate ITF Files


Alternatively, the following example specifies the electromigration information in an external
file by using the INCLUDE_EM_INFORMATION_FILE statement:
TECHNOLOGY = SIMPLE
DIELECTRIC TOP { THICKNESS = 3.600 ER = 3.9 }
CONDUCTOR M2 { THICKNESS = 0.250 WMIN = 0.5SMIN = 0.5 RPSQ = 0.05 }
DIELECTRIC D3 { THICKNESS = 0.300 ER = 3.9 }
CONDUCTOR M1 { THICKNESS = 0.212 WMIN = 0.5 SMIN = 0.5 RPSQ = 0.05 }
DIELECTRIC D2 { THICKNESS = 0.200 ER = 4.2 }
CONDUCTOR POLY{ THICKNESS = 0.100 WMIN = 0.3 SMIN = 0.3 RPSQ = 10.0}
DIELECTRIC D1 { THICKNESS = 0.300 ER = 3.9 }
VIA via1 { FROM=M1 TO=M2 RHO=0.263 }
VIA polyCont { FROM=POLY TO=M1 RHO=0.352 }
VIA diffCont { FROM=SUBSTRATE TO=M1 RHO=0.500 }

EM_INFORMATION $Start of EM section


INCLUDE_EM_INFORMATION_FILE = simple_em_rules.itf
END_OF_EM_INFORMATION $End of EM section

ITF-EM Structure
This section describes the hierarchical structure of the electromigration section in the ITF.
Use these values in power and ground EM analysis as follows:
1. Obtain the power and ground current distribution, typically found by analyzing the
parasitic network and device power consumption.
2. Perform static rail analysis to find currents to check against the AVERAGE EM rules.
3. Perform dynamic rail analysis to find currents to check against the RMS and PEAK EM
rules.
Use these values in signal EM analysis as follows:
1. Obtain the current distribution of wire or via segments by analyzing the corresponding
parasitic network and driver or receiver models.
2. Check the results against the AVERAGE, RMS, and PEAK EM rules.

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Keywords fall into one of the following categories:


Block
The top level of the ITF-EM section contains the following blocks:
COMMON_INFO Contains information common to the entire electromigration section.

LAYER Defines electromigration rules for metal layers.

VIA Defines electromigration rules for via layers.

STACKED_VIAS Defines electromigration rules for stacked vias.

VIA_ARRAY Defines electromigration rules for a via array in a specified via layer.

Module
Each block can contain one or more of the following modules. Each of these modules
defines a specific type of electromigration rule or limit:
AVERAGE Defines long-term DC effects.

RMS Defines Joule heating effects on electromigration lifetime.

PEAK Defines fuse effects.

Function
A function uses keywords, variables, and mathematical operators to calculate values.
The ITF-EM standard contains one function-based rule, the CURRENT_FUNCTION rule.
Downstream tools that read ITF-EM might have different ways to represent, interpolate,
or extrapolate the function. The ITF-EM description conveys information provided by the
foundry to a downstream tool, but does not specify how that information is used.
Table
A table definition includes keywords that define the table indexes and a list of values.
Several rules are defined with tables.
Constant
Predefined constant values or strings that are allowable values for keywords. For
example, the VIA_TYPES keyword only accepts values of SINGLE and ARRAY to identify
via types.
Constant variable
Variables used to store values or strings that are used as constants in other statements.
For example, the CURRENT_DEFAULT_AVERAGE keyword is used to store the default DC
current limit.

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Variable type
Variables for use in function expressions. For example, WIDTH is used to define a width
variable in the CURRENT_FUNCTION function.
List
A list of strings to use as index identifiers for values stored in tables. For example, the
METAL_WIDTH_VALUES list is used to list the metal width values whose currents are stored
in the CURRENT_VALUES table.

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ITF-EM Keywords and Syntax


This section describes keywords and syntax used in the ITF-EM section.
Notes:
In this document, uppercase letters are used for the ITF-EM keywords. However, the
keywords can be written in lowercase or uppercase in the ITF-EM file.
In the ITF-EM section, the EM rule for allowable electrical current for a layer or via can
be expressed as either a total current value or a current density value. The default is the
total current value.
All units in the ITF-EM section should be consistent with the conventional ITF section.

The dollar sign character ($) serves as the comment delimiter in the ITF file. The
conventional ITF uses the same comment delimiter.

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AVERAGE
Syntax
AVERAGE {
...
}

Description
The AVERAGE module contains electromigration rules to model long-term DC effects.
The AVERAGE module can be used only within the block statements, such as COMMON_INFO,
LAYER, and VIA. Braces { } indicate the start and end of the AVERAGE module.

The AVERAGE module is optional for each LAYER or VIA block. If the AVERAGE module is
empty or does not appear, it means that the LAYER or VIA block has no corresponding
AVERAGE electromigration limits.

Examples
COMMON_INFO {
AVERAGE {
TTF_TEMPERATURE {110 115 120 125 130 140}
TTF_FACTOR {1 0.704 0.500 0.358 0.258 0.138}
}
}

See Also
COMMON_INFO
LAYER
VIA

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COMMON_INFO
Syntax
COMMON_INFO {
ITF_EM_VERSION = version_name
AVERAGE { ... }
RMS { ... }
PEAK { ... }
}

Description
The COMMON_INFO block contains information common to the entire ITF-EM section.This
block must be placed at the beginning of the ITF-EM section.

Examples
COMMON_INFO {
ITF_EM_VERSION = v1.5
AVERAGE {
TTF_TEMPERATURE { 110 115 120 125 130 140 }
TTF_FACTOR { 1 0.704 0.500 0.358 0.258 0.138 }
VIA_COVER_LANDING_TYPE {
FF FQ FS FP QF QQ QS QP SF SQ SS SP PF PQ PS PP
}
}
}

See Also
ITF_EM_VERSION
AVERAGE
PEAK
RMS
TTF_TEMPERATURE, TTF_FACTOR
VIA_COVER_LANDING_TYPE

Electromigration ITF Syntax Specification 3-10


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CONDITION
Syntax
CONDITION { ... }

Description
The CONDITION statement defines a conditional choice that returns a value depending on an
assigned variable or range of values. The unit of the returned value depends on the
EXPRESSION in the CONDITION statement.

Examples
CURRENT_FUNCTION {
WIDTH w
CONDITION {
LENGTH l {5 10}
EXPRESSION = 4 * 8.096 * ( w - 0.020 )
EXPRESSION = 1.5 * 8.096 * ( w - 0.020 )
EXPRESSION = 1 * 8.096 * ( w - 0.020 )
}
}

See Also
EXPRESSION

Chapter 3: Electromigration ITF Syntax Specification


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CONDITION ITF Syntax Specification 3-11
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CONTACT_AREA
Syntax
CONTACT_AREA { v1 v2 v3 ... }

Arguments

Argument Description

v1 v2 v3 ... Contact area values


Units: square microns

Description
The CONTACT_AREA keyword defines a vector that is used to specify contact area values as
indexes of the table defined by the CURRENT_VALUES statement in a VIA_CURRENT_TABLE
block.
The CONTACT_AREA keyword is valid within a VIA_CURRENT_TABLE block that is part of the
AVERAGE module for a via definition.

This index accounts for the effect of contact area on current flow.

See Also
CURRENT_VALUES
VIA_CURRENT_TABLE

Electromigration ITF Syntax Specification 3-12


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CURRENT_DEFAULT_AVERAGE
Syntax
CURRENT_DEFAULT_AVERAGE = current_value

Arguments

Argument Description

current_value Current value


Units: mA

Description
The CURRENT_DEFAULT_AVERAGE statement specifies a constant that is used as the default
electromigration current limit in the AVERAGE module.

See Also
COMMON_INFO
AVERAGE
LAYER

Chapter 3: Electromigration ITF Syntax Specification


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CURRENT_DEFAULT_PEAK
Syntax
CURRENT_DEFAULT_PEAK = current_value

Arguments

Argument Description

current_value Current
Units: mA

Description
The CURRENT_DEFAULT_PEAK statement specifies a constant that is used as the default
electromigration current limit in the PEAK module.

See Also
COMMON_INFO
LAYER
PEAK

Electromigration ITF Syntax Specification 3-14


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CURRENT_DEFAULT_RMS
Syntax
CURRENT_DEFAULT_RMS = current_value

Arguments

Argument Description

current_value Current
Units: mA

Description
The CURRENT_DEFAULT_RMS statement specifies a constant that is used as the default
electromigration current limit in the RMS module.

See Also
COMMON_INFO
LAYER
RMS

Chapter 3: Electromigration ITF Syntax Specification


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CURRENT_DEFAULT_RMS 3-15
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CURRENT_DENSITY_DEFAULT_AVERAGE
Syntax
CURRENT_DENSITY_DEFAULT_AVERAGE = current_density_value

Arguments

Argument Description

current_density_value Current density


Units: mA per micron

Description
The CURRENT_DENSITY_DEFAULT_AVERAGE statement specifies a constant that is used as
the default electromigration current density limit in the AVERAGE module.

See Also
COMMON_INFO
AVERAGE
LAYER

Electromigration ITF Syntax Specification 3-16


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CURRENT_DENSITY_DEFAULT_PEAK
Syntax
CURRENT_DENSITY_DEFAULT_PEAK = current_density_value

Arguments

Argument Description

current_density_value Current density


Units: mA per micron

Description
The CURRENT_DENSITY_DEFAULT_PEAK statement specifies a constant that is used as the
default electromigration current density limit in the PEAK module.

See Also
COMMON_INFO
LAYER
PEAK

Chapter 3: Electromigration ITF Syntax Specification


Electromigration ITF Syntax Specification
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CURRENT_DENSITY_DEFAULT_RMS
Syntax
CURRENT_DENSITY_DEFAULT_RMS = current_density_value

Arguments

Argument Description

current_density_value Current density


Units: mA per micron

Description
The CURRENT_DENSITY_DEFAULT_RMS statement specifies a constant that is used as the
default electromigration current density limit in the RMS module.

See Also
COMMON_INFO
LAYER
RMS

Electromigration ITF Syntax Specification 3-18


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CURRENT_DENSITY_VALUES
Syntax
CURRENT_DENSITY_VALUES {
value_11 value_12 ...
value_21 value_22 ...
...
}

Arguments

Argument Description

value_xy Current density


Units: mA per micron

Description
The CURRENT_DENSITY_VALUES statement specifies a table that defines electromigration
rules for a specified layer. CURRENT_DENSITY_VALUES should be specified with the
LAYER_CURRENT_DENSITY_TABLE statement.

See Also
COMMON_INFO
LAYER_CURRENT_DENSITY_TABLE

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CURRENT_DIRECTION
Syntax
CURRENT_DIRECTION DOWNSTREAM | UPSTREAM

Arguments

Argument Description

DOWNSTREAM Specifies that the current direction is horizontal.


The electromigration limit depends on the via width.

UPSTREAM Specifies that the current direction is vertical.


The electromigration limit depends on the overlap area of the M0
layer with diffusion.

Description
The CURRENT_DIRECTION keyword specifies the current direction in a via. This keyword is
valid within the AVERAGE block of a via definition.

Example
CURRENT_DIRECTION UPSTREAM

Electromigration ITF Syntax Specification 3-20


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CURRENT_FUNCTION
Description
The CURRENT_FUNCTION statement defines a current calculation function in the LAYER or VIA
block. The general description of the CURRENT_FUNCTION definition is as follows:
CURRENT_FUNCTION {
Variable_type1 name_of_variable1
Variable_type2 name_of_variable2
...
CONDITION {
Condition_variable_type name_of_condition_variable {
boundary_value1_of_condition_variable
boundary_value2_of_condition_variable
}
| name_of_condition_variable == {
value1_of_condition_variable
value2_of_condition_variable
}
$ Function expression for
$ name_of_condition_variable < value1_of_condition_variable
EXPRESSION = function_expression1(
name_of_variable1,
name_of_variable2,
...,
name_of_condition_variable
)
$ Function expression for
$ value1_of_condition_variable < name_of_condition_variable
$ < value2_of_condition_variable
EXPRESSION = function_expression2(
name_of_variable1,
name_of_variable2,
...,
name_of_condition_variable
)
$ Function expression for
$ name_of_condition_variable > value2_of_condition_variable
EXPRESSION = function_expression3(
name_of_variable1,
name_of_variable2,
...,
name_of_condition_variable
)
}
}

Notes:
The number of EXPRESSION statements should equal the number of possible cases.

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The following mathematical symbols and expressions are supported in an EXRESSION


statement: +, , *, /, sqrt, and ^. Parentheses ( ) indicate priority.
Only one CURRENT_FUNCTION statement is supported for each LAYER or VIA block in
AVERAGE, RMS, and PEAK statements.

Downstream tools that read ITF-EM might have different ways to represent, interpolate,
or extrapolate the function. The ITF-EM description conveys information provided by the
foundry to a downstream tool, but does not specify how that information is used.

Examples
The following equations are examples of electromigration information provided by a foundry:

These four equations can be expressed in the ITF-EM with the following statements:
CURRENT_FUNCTION {
WIDTH w
CONDITION {
LENGTH m_len { 5 10 }
EXPRESSION = m_len * 1.104 * ( w - 0.010 )
EXPRESSION = 1.5 * 1.104 * ( w - 0.010 )
EXPRESSION = 4 * 1.104 * ( w - 0.010 )
}
}
CURRENT_FUNCTION {
WIDTH w
DELTA_TEMPERATURE delta_T
EXPRESSION = sqrt( 2.54 * delta_T * w * (w + 2.924 ) )
}
CURRENT_FUNCTION {
WIDTH w
DELTA_TEMPERATURE delta_T
EXPRESSION = sqrt( 3.98 * delta_T * ( w - 0.02 )^2 *
( w - 0.02+ 2.303 ) / ( w - 0.02 + 0.0443) )
}

Electromigration ITF Syntax Specification 3-22


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CURRENT_FUNCTION {
CONDITION {
LENGTH == { 3 2 }
EXPRESSION = 7
EXPRESSION = 5.4
}
}

See Also
COMMON_INFO

LAYER

VIA

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CURRENT_FUNCTION ITF Syntax Specification 3-23
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CURRENT_VALUES
Syntax
CURRENT_VALUES {
value_11 value_12 ...
value_21 value_22 ...
...
}

Arguments

Argument Description

value_xy Current
Units: mA

Description
The CURRENT_VALUES statement specifies a table that defines electromigration rules for a
specific layer. The CURRENT_VALUES keyword is valid within a LAYER_CURRENT_TABLE block
or a VIA_CURRENT_TABLE block. The number of current values should correspond to the
number of possible combinations of the variables included within the block.

See Also
COMMON_INFO
LAYER_CURRENT_TABLE
VIA_CURRENT_TABLE

Electromigration ITF Syntax Specification 3-24


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DELTA_TEMPERATURE
Syntax
DELTA_TEMPERATURE variable_name

Or

DELTA_TEMPERATURE { v1 v2 ... vn }

Arguments

Argument Description

variable_name The name of a variable used to represent temperature in an


expression.

v1 v2 ... vn Delta temperature values.


Units: degrees Celsius (C)

Description
Delta temperature is the temperature difference calculated as the working temperature
minus the reference temperature. The reference temperature is defined by the
REFERENCE_TEMPERATURE statement.

The DELTA_TEMPERATURE keyword can be used in two ways:


Within a CURRENT_FUNCTION block, use the DELTA_TEMPERATURE keyword to specify the
name of a variable that represents delta temperature in an EXPRESSION statement.
Within a layer RMS module, use the DELTA_TEMPERATURE keyword to specify an array of
values that represent the increase in temperature of a metal line due to RMS current.
If the ambient temperature is T, the temperature of the metal line is
T + DELTA_TEMPERATURE.

See Also
CURRENT_FUNCTION
REFERENCE_TEMPERATURE

Chapter 3: Electromigration ITF Syntax Specification


Electromigration
DELTA_TEMPERATUREITF Syntax Specification 3-25
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EM_INFORMATION, END_OF_EM_INFORMATION
Syntax
EM_INFORMATION
...
END_OF_EM_INFORMATION

Description
The EM_INFORMATION and END_OF_EM_INFORMATION keywords identify the beginning and
end of the ITF-EM section, respectively. They must be the first and last statements of the
ITF-EM section.

Examples
EM_INFORMATION
INCLUDE_EM_INFORMATION_FILE = ~/my_advanced_EM.itf
END_OF_EM_INFORMATION

Electromigration ITF Syntax Specification 3-26


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EXPRESSION
Syntax
EXPRESSION = mathematical_expression | constant_value

Description
The EXPRESSION statement defines a mathematical expression that is used to calculate an
electromigration limit value. The unit of returned value depends on the parent statement.

Examples
The following equations are examples of electromigration information provided by a foundry:

These four equations can be expressed in the ITF-EM with the following statements:
CURRENT_FUNCTION {
WIDTH w
CONDITION {
LENGTH m_len { 5 10 }
EXPRESSION = m_len * 1.104 * ( w - 0.010 )
EXPRESSION = 1.5 * 1.104 * ( w - 0.010 )
EXPRESSION = 4 * 1.104 * ( w - 0.010 )
}
}
CURRENT_FUNCTION {
WIDTH w
DELTA_TEMPERATURE delta_T
EXPRESSION = sqrt( 2.54 * delta_T * w * (w + 2.924 ) )
}
CURRENT_FUNCTION {
WIDTH w
DELTA_TEMPERATURE delta_T
EXPRESSION = sqrt( 3.98 * delta_T * ( w - 0.02 )^2 *
( w - 0.02+ 2.303 ) / ( w - 0.02 + 0.0443) )
}

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EXPRESSION ITF Syntax Specification 3-27
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CURRENT_FUNCTION {
CONDITION {
LENGTH == { 3 2 }
EXPRESSION = 7
EXPRESSION = 5.4
}
}

See Also
COMMON_INFO
CONDITION
CURRENT_FUNCTION

Electromigration ITF Syntax Specification 3-28


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FF, FQ, FS, FP, QF, QQ, QS, QP, SF, SQ, SS, SP, PF, PQ, PS, PP
Description
These keywords represent via cover landing types.

See Also
VIA_COVER_LANDING_TYPE

Chapter 3: Electromigration ITF Syntax Specification


Electromigration ITFQQ,
FF, FQ, FS, FP, QF, Syntax
QS,Specification
QP, SF, SQ, SS, SP, PF, PQ, PS, PP 3-29
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INCLUDE_EM_INFORMATION_FILE
Syntax
INCLUDE_EM_INFORMATION_FILE = path/file_name

Arguments

Argument Description

path/file_name Path and filename of the electromigration information file. The


path can be an absolute or relative path.

Description
The INCLUDE_EM_INFORMATION_FILE statement specifies the inclusion of an external file
that contains the electromigration information.

Examples
INCLUDE_EM_INFORMATION_FILE = ~/my_advanced_EM.itf

Electromigration ITF Syntax Specification 3-30


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ITF_EM_VERSION
Syntax
ITF_EM_VERSION = version_number

Arguments

Argument Description

version_number Current ITF-EM version

Description
The ITF_EM_VERSION statement specifies the current ITF-EM version.

Examples
COMMON_INFO {
ITF_EM_VERSION = v1.5
AVERAGE {
TTF_TEMPERATURE { 110 115 120 125 130 140 }
TTF_FACTOR { 1 0.704 0.500 0.358 0.258 0.138 }
VIA_COVER_LANDING_TYPE {
FF FQ FS FP QF QQ QS QP SF SQ SS SP PF PQ PS PP
}
}
}

See Also
COMMON_INFO

Chapter 3: Electromigration ITF Syntax Specification


Electromigration
ITF_EM_VERSION ITF Syntax Specification 3-31
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LAYER
Syntax
LAYER layer_name {
[ AVERAGE { ... } ]
[ RMS { ... } ]
[ PEAK { ... } ]
}

Arguments

Argument Description

layer_name Case-sensitive name of the process layer

Description
The LAYER block defines electromigration rules for a specified metal layer.
Important notes:
The layer_name string is a case-sensitive string that refers to the process layer name.
The layer_name string must begin with an alphabetic character.
Unless otherwise noted, the layer_name string must contain only alphanumeric
characters and the underscore character (_).
The return value of CURRENT_FUNCTION is a current value, while the return values of
CURRENT_DENSITY_DEFAULT_AVERAGE, CURRENT_DENSITY_DEFAULT_RMS and
CURRENT_DENSITY_DEFAULT_PEAK are current densities.

In the LAYER description, the three statements, RATING_TEMPERATURE, RATING_FACTOR


and CURRENT_FUNCTION, are for TSMC's iRCX electromigration rules, and all of the rest
statements in LAYER are for Intel's electromigration rules. Currently, they co-exist in ITF-
EM spec, but will not co-exist in real ITF-EM files from different foundries, i.e.,
RATING_TEMPERATURE, RATING_FACTOR and CURRENT_FUNCTION should appear
together, and the rest appear together.
All LAYER blocks are optional in the electromigration section. If the LAYER block is empty
or does not appear in electromigration section, it means that the LAYER has no
corresponding electromigration limits.

Electromigration ITF Syntax Specification 3-32


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Examples
The following example shows the typical structure of the LAYER block in the ITF-EM section.
LAYER layer_name {
AVERAGE {
RATING_TEMPERATURE { t1 t2 ... }
RATING_FACTOR {v1 v2 ... }
CURRENT_FUNCTION {
$ function content as shown in
$ CURRENT_FUNCTION specification
}

CURRENT_DENSITY_DEFAULT_AVERAGE = current_density_default_avg_value
METAL_WIDTH_CUTOFF = cutoff_width
LAYER_CURRENT_TABLE {
VIA_SIZE via_size_name { width length }
VIA_TYPES { vt1 vt2 }
METAL_WIDTH_VALUES {mwv1 mwv2 mwv3 ... }
CURRENT_VALUES {
v(vt1, mwv1) v(vt1, mwv2) v(vt1,mwv3) v(vt1, ...)
v(vt2, mwv1) v(vt2,m wv2) v(vt2, mwv3) v(vt2, ...)
}
}
}

RMS {
CURRENT_FUNCTION {
$ function content as shown in FUNCTION specification
}
CURRENT_DENSITY_DEFAULT_RMS = current_density_rms_default_value
}

PEAK {
CURRENT_FUNCTION {
$ function content as shown in FUNCTION specification
}
CURRENT_DENSITY_DEFAULT_PEAK = current_density_max_default_value
}
}

See Also
COMMON_INFO
VIA

Chapter 3: Electromigration ITF Syntax Specification


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LAYER ITF Syntax Specification 3-33
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LAYER_CURRENT_DENSITY_TABLE
Syntax
LAYER_CURRENT_DENSITY_TABLE {
...
}

Description
The LAYER_CURRENT_DENSITY_TABLE keyword is similar to the LAYER_CURRENT_TABLE
keyword except that it describes current density instead of current.

See Also
CURRENT_DENSITY_VALUES
LAYER
LAYER_CURRENT_TABLE

Electromigration ITF Syntax Specification 3-34


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LAYER_CURRENT_TABLE
Syntax
LAYER_CURRENT_TABLE {
...
}

Description
The LAYER_CURRENT_TABLE statement specifies a table that describes electromigration
limits with respect to one or more index values. The corresponding electromigration limit
values are specified by using the CURRENT_VALUES keyword.
Index values must include the via type as defined by the VIA_SIZE or VIA_TYPES
statements.
The following is an example of a LAYER_CURRENT_TABLE block:
LAYER_CURRENT_TABLE {
VIA_SIZE_LIST { a1 a2 ... }
VIA_TYPES { b1 b2 ... }
METAL_WIDTH_VALUES {c1 c2 ... }
CURRENT_VALUES {
v(a1, b1, c1) v(a2, b1, c1) v(..., b1, c1)
v(a1, b2, c1) v(a2, b2, c1) v(..., b2, c1)
v(a1, ..., c1) v(a2, ..., c1) v(..., ..., c1)
v(a1, b1, c2) v(a2, b1, c2) v(..., b1, c2)
v(a1, b2, c2) v(a2, b2, c2) v(..., b2, c2)
v(a1, ..., c2) v(a2, ..., c2) v(..., ..., c2)
v(a1, b1, ...) v(a2, b1, ...) v(..., b1, ...)
v(a1, b2, ...) v(a2, b2, ...) v(..., b2, ...)
v(a1, ..., ...) v(a2, ..., ...) v(..., ..., ...)
}
}

Important Notes:
LAYER_CURRENT_TABLE is the identifier of a table, VIA_SIZE_LIST, VIA_TYPES,
METAL_WIDTH_VALUES and CURRENT_VALUES belong to the list group.

VIA_SIZE_LIST, VIA_TYPES and METAL_WIDTH_VALUES give three-dimensional table


index values, and CURRENT_VALUES gives table values of the table
LAYER_CURRENT_TABLE.

LAYER_CURRENT_TABLE support multi-dimensional indexes. For a table with multi-


dimensional indexes, the table values are indexed according to the order of appearance
of the index parameters. The first index is in the inner loop; the last index is in the outer
loop.

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The LAYER_CURRENT_DENSITY_TABLE and VIA_CURRENT_TABLE keywords follows the


same rules as the LAYER_CURRENT_TABLE keyword.

Examples
LAYER_CURRENT_TABLE {
VIA_SIZE_LIST {via_size_1 via_size_2}
VIA_TYPES {SINGLE ARRAY}
METAL_WIDTH_VALUES { 0.3 0.4 0.5 }
CURRENT_VALUES {
0.2 0.2
0.25 0.3
0.24 0.24
0.30 0.33
0.25 0.25
0.34 0.4
}
}

This example contains three table indexes: VIA_SIZE_LIST, VIA_TYPES, and


METAL_WIDTH_VALUES. The first value in the third line in CURRENT_VALUES is 0.24, which
corresponds to via_size_1, SINGLE and 0.4 in the VIA_SIZE_TYPE_LIST, VIA_SIZE and
METAL_WIDTH_VALUES statements, respectively.

See Also
COMMON_INFO
LAYER
LAYER_CURRENT_DENSITY_TABLE
VIA_CURRENT_TABLE

Electromigration ITF Syntax Specification 3-36


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LENGTH
Syntax
LENGTH == len_variable { v1 v2 ... vN }

Or
LENGTH len_variable { v1 v2 ... vN }

Arguments

Argument Description

len_variable The name of a variable used to represent length in an


expression.

v1 v2 ... vN Allowable discrete metal length values.


Units: microns

r1 r2 ... rN Metal length values that define length ranges.


Units: microns

Description
The LENGTH statement is used within a CURRENT_FUNCTION block to specify a variable name
that represents length in subsequent EXPRESSION statements. The LENGTH statement also
specifies which EXPRESSION statements should be used for specific length values or length
ranges.
The form of the statement affects the meaning, as follows:
If you use the == operator, the length variable can only take on the exact values in the
list. Each subsequent EXPRESSION statement is used for one length value in the list, in
the order provided. The number of length values in the list should equal the number of
EXPRESSION statements.

If you do not use the == operator, the length values represent break points in a range of
lengths. The first EXPRESSION statement is used when the metal length is less than or
equal to the first length value in the list. The second EXPRESSION statement is used when
the metal length is greater than the first length value and less than or equal to the second
length value, and so on. The number of length values in the list should be one less than
the number of EXPRESSION statements.

Chapter 3: Electromigration ITF Syntax Specification


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Examples
In the following example, variable m_len represents length. The first EXPRESSION statement
is used when the length is less than or equal to 5, the second EXPRESSION statement is used
when the length is greater than 5 but less than or equal to 10, and the third EXPRESSION
statement is used when the length is greater than 10.
CURRENT_FUNCTION {
WIDTH w
CONDITION {
LENGTH m_len { 5 10 }
EXPRESSION = m_len * 1.104 * ( w - 0.010 )
EXPRESSION = 1.5 * 1.104 * ( w - 0.010 )
EXPRESSION = 4 * 1.104 * ( w - 0.010 )
}
}

In the following example, the first EXPRESSION statement is used when the length equals 3
and the second EXPRESSION statement is used when the length equals 2. In this case, the
expressions are simple constant values.
CURRENT_FUNCTION {
CONDITION {
LENGTH == { 3 2 }
EXPRESSION = 7
EXPRESSION = 5.4
}
}

See Also
COMMON_INFO
CURRENT_FUNCTION
LAYER
EXPRESSION

Electromigration ITF Syntax Specification 3-38


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METAL_LENGTH_VALUES
Syntax
METAL_LENGTH_VALUES { v1 v2 v3 ... }

Arguments

Argument Description

v1 v2 v3 ... Metal length values


Units: microns

Description
The METAL_LENGTH_VALUES statement specifies a list of metal length values to use as index
values of the table defined by the CURRENT_VALUES statement in a LAYER_CURRENT_TABLE
or VIA_CURRENT_TABLE block.
The METAL_LENGTH_VALUES keyword is valid within a LAYER_CURRENT_TABLE block that is
part of the AVERAGE module for a layer definition or a VIA_CURRENT_TABLE block that is part
of the AVERAGE module for a via definition.
This index accounts for the effect of metal length on current flow. The total length of metal is
from one line-end site to another line-end site of metal on the same layer. For layout
structures such as T-junctions and fingered structures, the length is the longest path.

See Also
COMMON_INFO
CURRENT_VALUES
LAYER_CURRENT_TABLE
VIA_CURRENT_TABLE

Chapter 3: Electromigration ITF Syntax Specification


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METAL_WIDTH_CUTOFF
Syntax
METAL_WIDTH_CUTOFF = metal_width_value

Arguments

Argument Description

metal_width_value Minimum allowed width of assigned metal


Units: microns

Description
The METAL_WIDTH_CUTOFF statements specifies the allowed minimum width of the assigned
metal.

See Also
COMMON_INFO
LAYER

Electromigration ITF Syntax Specification 3-40


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METAL_WIDTH_RANGES
Syntax
METAL_WIDTH_RANGES { r1 r2 r3 ... }

Arguments

Argument Description

r1 r2 r3 ... Metal width range values


Units: microns

Description
The METAL_WIDTH_RANGES statement specifies a list of metal width boundary values to
serve as indexes of the CURRENT_DENSITY_VALUES table in a
LAYER_CURRENT_DENSITY_TABLE block.

Metal width ranges are divided by the values supplied in the METAL_WIDTH_RANGES
statement. A metal width is located in one of the following intervals: (0, r1], (r1, r2], (r2, r3],
(r3, ...]. If a metal width is located in the interval (r1, r2], it means that this metal width is
greater than r1 and less than or equal to r2.

See Also
CURRENT_DENSITY_VALUES
LAYER_CURRENT_DENSITY_TABLE

Chapter 3: Electromigration ITF Syntax Specification


Electromigration ITF Syntax Specification
METAL_WIDTH_RANGES 3-41
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METAL_WIDTH_VALUES
Syntax
METAL_WIDTH_VALUES { v1 v2 v3 ... }

Arguments

Argument Description

v1 v2 v3 ... Metal width values


Units: microns

Description
The METAL_WIDTH_VALUES keyword specifies a list of metal width values to use as index
values of the table defined by the CURRENT_VALUES statement in a LAYER_CURRENT_TABLE
block. This keyword is valid in all modules of a layer definition.

See Also
CURRENT_VALUES
LAYER_CURRENT_TABLE

Electromigration ITF Syntax Specification 3-42


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PEAK
Syntax
PEAK {
...
}

Description
The PEAK module contains electromigration rules to model long fuse effects.
The PEAK module can be used only within the block statements, such as COMMON_INFO,
LAYER, and VIA. Braces { } indicate the start and end of the PEAK module.

The PEAK module is optional for each LAYER or VIA block. If the PEAK module is empty or
does not appear, it means that the LAYER or VIA block has no corresponding PEAK
electromigration limits.

See Also
COMMON_INFO
LAYER
VIA

Chapter 3: Electromigration ITF Syntax Specification


Electromigration
PEAK ITF Syntax Specification 3-43
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RATING_TEMPERATURE, RATING_FACTOR
Syntax
RATING_TEMPERATURE { rt1 rt2 rt3 ... }
RATING_FACTOR { rt1 rt2 rt3 ... }

Arguments

Argument Description

rt Scaling factor

Description
The RATING_TEMPERATURE and RATING_FACTOR statements define tables that are used to
specify the temperatures related to rating factors given by the RATING_FACTOR statement.

See Also
COMMON_INFO
AVERAGE
PEAK
RMS

Electromigration ITF Syntax Specification 3-44


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REFERENCE_TEMPERATURE
Syntax
REFERENCE_TEMPERATURE = temperature_value

Arguments

Argument Description

temperature_value Temperature
Units: degrees Celsius (C)

Description
The REFERENCE_TEMPERATURE defines the reference temperature for the ITF-EM rules. The
reference temperature is specified by a foundry.

See Also
COMMON_INFO
DELTA_TEMPERATURE

Chapter 3: Electromigration ITF Syntax Specification


Electromigration ITF Syntax Specification
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RMS
Syntax
RMS {
...
}

Description
The RMS module contains electromigration rules to model long Joule heating effects on
electromigration lifetime.
The RMS module can be used only within the block statements, such as COMMON_INFO,
LAYER, and VIA. Braces { } indicate the start and end of the RMS module.

The RMS module is optional for each LAYER or VIA block. If the RMS module is empty or does
not appear, it means that the LAYER or VIA block has no corresponding RMS
electromigration limits.

See Also
COMMON_INFO
LAYER
VIA

Electromigration ITF Syntax Specification 3-46


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RMS_SPACING_FACTOR_TABLE
Syntax
RMS_SPACING_FACTOR_TABLE {
VIA_VIA_SPACING { s1 s2 .. sn }
FACTOR_VALUES { f1 f2 .. fn }
}

Arguments

Argument Description

s1 s2 sn Spacing between vias.


Units: microns

f1 f2 .. fn Current derating factors.


Unitless factor

Description
Use the RMS_SPACING_FACTOR_TABLE keyword to specify current derating factors due to the
spacing between vias. The number of arguments in each row of the table must be equal.
The spacing between vias is measured as the shortest combination of horizontal and
vertical distance from the center of one via to another. If a metal wire has a single via, the
derating factor is set to 1 (i.e. no derating).
Lists of values are interpreted on a sequential basis, independent of any carriage returns or
other hidden characters.

Example
LAYER metal9 {
RMS
RMS_SPACING_FACTOR_TABLE {
VIA_VIA_SPACING { 1 3 10 }
FACTOR_VALUES { 2.0 1.3 1.05 }
} }

Chapter 3: Electromigration ITF Syntax Specification


Electromigration ITF Syntax Specification
RMS_SPACING_FACTOR_TABLE 3-47
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SINGLE, ARRAY
Description
The SINGLE keyword indicates a single via. The ARRAY keyword indicates multiple vias that
connect two polygons.

See Also
LAYER_CURRENT_TABLE
VIA_TYPES

Electromigration ITF Syntax Specification 3-48


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STACKED_VIAS
Electromigration limits to stacked vias will be supported in a later version of the ITF-EM
syntax.

Chapter 3: Electromigration ITF Syntax Specification


Electromigration
STACKED_VIASITF Syntax Specification 3-49
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TEMPERATURE
Syntax
TEMPERATURE { v1 v2 ... vn }

Arguments

Argument Description

v1 v2 ... vn Delta temperature values.


Units: degrees Celsius (C)

Description
The TEMPERATURE keyword is valid within a LAYER_CURRENT_TABLE block that is part of the
AVERAGE module for a layer definition or a VIA_CURRENT_TABLE block that is part of the
AVERAGE module for a via definition.

The TEMPERATURE keyword specifies a list of temperatures to use as one of the index values
for the matrix of currents in the current table.

See Also
LAYER_CURRENT_TABLE
VIA_CURRENT_TABLE

Electromigration ITF Syntax Specification 3-50


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TTF_TEMPERATURE, TTF_FACTOR
Syntax
TTF_TEMPERATURE { t1 t2 t3 ... }
TTF_FACTOR { t1 t2 t3 ... }

Arguments

Argument Description

t1 t2 t3 ... Scaling factor

Description
The TTF_TEMPERATURE and TTF_FACTOR statements define a pair of tables that specify the
temperature-related time-to-failure (TTF) factors in TTF_FACTOR. These keywords should be
specified inside the AVERAGE module in the COMMON_INFO block.

Examples
COMMON_INFO {
AVERAGE {
TTF_TEMPERATURE {110 115 120 125 130 140}
TTF_FACTOR {1 0.704 0.500 0.358 0.258 0.138}
}
}

See Also
COMMON_INFO
AVERAGE

Chapter 3: Electromigration ITF Syntax Specification


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TTF_TEMPERATURE, ITF Syntax Specification
TTF_FACTOR 3-51
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VIA
Syntax
VIA via_name {
[ AVERAGE { ... } ]
[ RMS { ... } ]
[ PEAK { ... } ]
}

Description
The VIA block defines electromigration limits for a specified via layer.
Important Notes:
via_name refers to the process via name.

The return value of CURRENT_FUNCTION, CURRENT_DEFAULT_AVERAGE,


CURRENT_DEFAULT_RMS and CURRENT_DEFAULT_PEAK are all current values.

All VIA blocks are optional in the electromigration section. If the VIA block is empty or
does not appear in electromigration section, it means that the VIA has no corresponding
electromigration limits.
In the VIA description, the three statements, RATING_TEMPERATURE, RATING_FACTOR and
CURRENT_FUNCTION, are for TSMC's iRCX electromigration rules, and all of the rest
statements in LAYER are for Intel's electromigration rules. Currently, they co-exist in ITF-
EM specification, but will not co-exist in real ITF-EM files from different foundries, i.e.,
RATING_TEMPERATURE, RATING_FACTOR and CURRENT_FUNCTION should appear
together, and the rest appear together.

Electromigration ITF Syntax Specification 3-52


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Examples
The following example shows the typical structure of the VIA block in the ITF-EM section.
VIA via_name {
AVERAGE {
RATING_TEMPERATURE { t1 t2 ... }
RATING_FACTOR {v1 v2 ... }

CURRENT_FUNCTION {
$ function content as shown in FUNCTION specification.
}
CURRENT_DEFAULT_AVERAGE = current_avg_default_value
VIA_ARRAY_MULTIPLIER {
current_up_multiplier
current_down_multiplier
}
VIA_SIZE size_type1 { width1 length1}
VIA_SIZE size_type2 { width2 length2}
VIA_CURRENT_TABLE size_type1 {
CURRENT_UP { current_limit_table_for_cover/landing_types }
CURRENT_DOWN { current_limit_table_for_cover/landing_types }
}
VIA_CURRENT_TABLE size_type2 {
CURRENT_UP { current_limit_table_for_cover/landing_types }
CURRENT_DOWN { current_limit_table_for_cover/landing_types }
}
}
RMS {
CURRENT_DEFAULT_RMS = current_rms_default_value
}
PEAK {
CURRENT_DEFAULT_PEAK = current_peak_default_value
}
}

Chapter 3: Electromigration ITF Syntax Specification


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VIA ITF Syntax Specification 3-53
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VIA_ARRAY
Syntax
VIA_ARRAY {
via_name1 value1
via_name2 value2
...
}

Description
The VIA_ARRAY statement specifies electromigration limits for a via array in a specified via
layer.

Electromigration ITF Syntax Specification 3-54


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VIA_ARRAY_MULTIPLIER
Syntax
VIA_ARRAY_MULTIPLIER = value1 ... value2

Description
The VIA_ARRAY_MULTIPLIER statement identifies a constant or constant list that is used as
rating factor of electromigration limit for assigned single via.

Syntax
COMMON_INFO
VIA
VIA_SIZE

Chapter 3: Electromigration ITF Syntax Specification


Electromigration ITF Syntax Specification
VIA_ARRAY_MULTIPLIER 3-55
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VIA_COVER_LANDING_TYPE
Syntax
VIA_COVER_LANDING_TYPE {
[FF] [FQ] [FS] [FP] [QF] [QQ] [QS] [QP]
[SF] [SQ] [SS] [SP] [PF] [PQ] [PS] [PP]
}

Arguments

Argument Description

[FF] [FQ] [FS] [FP] [QF] The via cover/landing types


[QQ] [QS] [QP] [SF] [SQ]
[SS] [SP] [PF] [PQ] [PS]
[PP]

Description
The VIA_COVER_LANDING_TYPE statement specifies the via cover and landing types.
Currently, 16 types specified by keywords FF, FQ, FS, FP, QF, QQ, QS, QP, SF, SQ,
SS, SP, PF, PQ, PS, PP can be used. These types are used to indicate the via cover and
landing types for the current values defined by the statements CURRENT_UP or
CURRENT_DOWN.

Examples
VIA_COVER_LANDING_TYPE {
FF FQ FS FP QF QQ QS QP SF SQ SS SP PF PQ PS PP
}

See Also
CURRENT_VALUES
VIA
VIA_CURRENT_TABLE

Electromigration ITF Syntax Specification 3-56


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VIA_CURRENT_TABLE
Syntax
VIA_CURRENT_TABLE {
$ Statements with keywords that belong to list group are
$ placed here to define this table.
}

Description
The VIA_CURRENT_TABLE statement specifies a table that describes electromigration limits
with respect to one or more index values. The corresponding electromigration limit values
are specified by using the CURRENT_VALUES keyword.

Examples
VIA_SIZE via1_size1 { 0.2 0.2 }
VIA_SIZE via1_size2 { 0.4 0.4 }
VIA_CURRENT_TABLE {
$ current limit for via cover landing types
VIA_COVER_LANDING_TYPE {
FF FQ FS FP QF QQ QS QP SF SQ SS SP PF PQ PS PP
}
CURRENT_DIRECTION { CURRENT_UP CURRENT_DOWN }
VIA_SIZE_LIST { via1_size1 via1_size2 }
CURRENT_VALUES {
1.2 1.1 1.0 0.9 1.1 1.0 0.9 0.8 1.0 0.9 0.8 0.7 0.9 0.8 0.7 0.6
1.4 1.3 1.2 1.1 1.3 1.2 1.1 1.0 1.2 1.1 1.0 0.9 1.1 1.0 0.9 0.8
2.2 2.1 2.0 1.9 2.1 2.0 1.9 1.8 2.0 1.9 1.8 1.7 1.9 1.8 1.7 1.6
2.4 2.3 2.2 2.1 2.3 2.2 2.1 2.0 2.2 2.1 2.0 1.9 2.1 2.0 1.9 1.8
}
}

See Also
COMMON_INFO
CURRENT_DIRECTION
CURRENT_VALUES
LAYER
VIA
VIA_SIZE
VIA_SIZE_LIST
VIA_COVER_LANDING_TYPE

Chapter 3: Electromigration ITF Syntax Specification


Electromigration
VIA_CURRENT_TABLEITF Syntax Specification 3-57
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VIA_SIZE
Syntax
VIA_SIZE via_size_type [ { via_width via_length } ]

Or
VIA_SIZE {
via_size_type_1 { via_width_1 via_length_1 }
via_size_type_2 { via_width_2 via_length_2 }
...
}

Or , to use a predefined via size type,


VIA_SIZE via_size_type

Description
The VIA_SIZE statement defines a via size type or multiple via size types. Note that the
name of via size type should be unique in the entire ITF-EM section.

Electromigration ITF Syntax Specification 3-58


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VIA_SIZE_LIST
Syntax
VIA_SIZE_LIST {via_size_type1 via_size_type2 ... }

Arguments

Argument Description

via_size_type Name of the via size type

Description
The VIA_SIZE_LIST statement lists via size types. These via size types are defined by the
VIA_SIZE statement. It can be used only inside the table defined by LAYER_CURRENT_TABLE.

See Also
LAYER_CURRENT_TABLE
VIA_SIZE

Chapter 3: Electromigration ITF Syntax Specification


Electromigration
VIA_SIZE_LIST ITF Syntax Specification 3-59
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VIA_TYPES
Syntax
VIA_TYPES { [SINGLE] [ARRAY] }

Arguments

Argument Description

SINGLE Specifies a single via type

ARRAY Specifies an array via type

Description
The VIA_TYPES statement defines a via type. Currently, only two types of vias are
supported: SINGLE and ARRAY. The VIA_TYPES statement can be used only inside table
defined by LAYER_CURRENT_TABLE.

See Also
LAYER_CURRENT_TABLE
SINGLE, ARRAY

Electromigration ITF Syntax Specification 3-60


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WIDTH
Syntax
WIDTH width_variable == { v1 v2 ... vN }

Or
WIDTH width_variable { r1 r2 ... rN }

Arguments

Argument Description

r1 r2 ... rN Width values


v1 v2 ... vN Units: m

Description
The WIDTH statement specifies a metal width value or a range of metal widths.
When specifiying a metal width value, width_variable must equal one of the values v1 v2
... vN .

When specifiying a range of metal widths, width_variable is divided into several intervals:
(0, r1], (r1, r2], (r2, ], (, rN]. If a width variable belongs in the interval (r1, r2], this metal
width is greater than r1 and less than or equal r2.

See Also
COMMON_INFO
CURRENT_FUNCTION
LAYER

Chapter 3: Electromigration ITF Syntax Specification


Electromigration
WIDTH ITF Syntax Specification 3-61
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Electromigration ITF Syntax Specification 3-62


A
ITF Examples A
This chapter contains examples of ITF files for several process technologies.
Each of the following sections contains an ITF file example and a diagram of the process
cross section:
Fully Planar Process
Conformal Dielectric Process
Gate Poly Process
Local Interconnect Process
Dielectric Air Gaps Process
Layer Etch Process
Metal Fill Process (Emulated)
Transistor-Level Process
Through-Silicon Via Process
Trench Contact Process

A-1
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Fully Planar Process


The following ITF statements describe the fully planar process shown in Figure A-25.
TECHNOLOGY = planar
DIELECTRIC TOP { THICKNESS=3.4 ER=3.9 }
DIELECTRIC D3 { THICKNESS=0.2 ER=4.7 }
CONDUCTOR M2 { THICKNESS=0.6 WMIN=0.5 SMIN=0.5 RPSQ=0.05 }
DIELECTRIC D2 { THICKNESS=1.2 ER=3.9 }
CONDUCTOR M1 { THICKNESS=0.6 WMIN=0.3 SMIN=0.3 RPSQ=0.05 }
DIELECTRIC D1 { THICKNESS=0.725 ER=3.9 }
CONDUCTOR POLY{ THICKNESS=0.125 WMIN=0.3 SMIN=0.3 RPSQ=10.0 }

DIELECTRIC D0{ THICKNESS=0.375 ER=3.9 }

VIA sub_tie { FROM=SUBSTRATE TO=M1 AREA=0.25 RPV=5 }


VIA poly_cont { FROM=POLY TO=M1 AREA=0.25 RPV=4 }
VIA via { FROM=M1 TO=M2 AREA=0.36 RPV=4 }

Figure A-25 Fully Planar Process

TOP 3.4

M2 0.6
D3 0.2

D2 1.2
M1 0.6

D1 0.725
0.125 POLY
D0 0.375

SUBSTRATE

ITF Examples A-2


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Conformal Dielectric Process


The following ITF statements describe the conformal dielectric process shown in
Figure A-26.
TECHNOLOGY = conformal
$ TOP is planarized by measuring from D2
DIELECTRIC TOP { THICKNESS=3.6 MEASURED_FROM=D2 ER=3.9 }
$ D3 is a conformal dielectric
DIELECTRIC D3 {
THICKNESS=0.2 MEASURED_FROM=TOP_OF_CHIP
SW_T=0.15 TW_T=0.18 ER=5.9 }
CONDUCTOR M2 { THICKNESS=0.6 WMIN=0.5 SMIN=0.5 RPSQ=0.05 }
DIELECTRIC D2 { THICKNESS=1.2 ER=3.9 }
CONDUCTOR M1 { THICKNESS=0.6 WMIN=0.3 SMIN=0.3 RPSQ=0.05 }
DIELECTRIC D1 { THICKNESS=0.725 ER=3.9 }
CONDUCTOR POLY { THICKNESS=0.125 WMIN=0.3 SMIN=0.3 RPSQ=10.0 }
DIELECTRIC D0 { THICKNESS=0.375 ER=3.9 }

VIA DIFF_CONT { FROM=SUBSTRATE TO=M1 AREA=0.25 RPV=5 }


VIA POLY_CONT { FROM=POLY TO=M1 AREA=0.25 RPV=4 }
VIA V1 { FROM=M1 TO=M2 AREA=0.36 RPV=4 }

Figure A-26 Conformal Dielectric Process

TOP 3.6

0.18
0.15
M2
D3 0.2

D2 1.2
0.6 M1

D1 0.725
0.125 POLY
D0 0.375

SUBSTRATE

Chapter A: ITF Examples


ITF Examples
Conformal Dielectric Process A-3
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Gate Poly Process


The following ITF statements describe the gate poly process shown in Figure A-27.
TECHNOLOGY = polygate
DIELECTRIC TOP { THICKNESS=1.2 ER=3.9 }
CONDUCTOR M2 { THICKNESS=0.4 WMIN=0.5 SMIN=0.5 RPSQ=0.05
DIELECTRIC D4 { THICKNESS=0.7 ER=3.9}
CONDUCTOR M1 { THICKNESS=0.4 WMIN=0.4 SMIN=0.4 RPSQ=0.05 }
DIELECTRIC D3 { THICKNESS=0.5 ER=3.9 }
CONDUCTOR POLY { THICKNESS=0.2 WMIN=0.3 SMIN=0.3 RPSQ=10.0 }
DIELECTRIC D2 { THICKNESS=0.1 ER=3.9 }
CONDUCTOR GATE { THICKNESS=0.2 WMIN=0.2 SMIN=0.2 RPSQ=8.0 }
DIELECTRIC TOX { THICKNESS=0.2 ER=3.9 }
VIA DIFF_CONT { FROM=SUBSTRATE TO=M1 AREA=0.25 RPV=5 }
VIA POLY_CONT { FROM=POLY TO=M1 AREA=0.25 RPV=4 }
VIA V1 { FROM=M1 TO=M2 AREA=0.36 RPV=4 }

Figure A-27 Gate Poly Process

TOP
1.2

M2 0.4

D4 0.7
0.4 M1

D3 0.5
0.2 POLY 0.2
D2 GATE 0.1
TOX 0.2

SUBSTRATE

ITF Examples A-4


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Local Interconnect Process


The following ITF statements describe the local interconnect process shown in Figure A-28.
TECHNOLOGY = polyli
DIELECTRIC TOP { THICKNESS=1.2 ER=3.9 }
CONDUCTOR M2 { THICKNESS=0.4 WMIN=0.5 SMIN=0.5 RPSQ=0.05
DIELECTRIC D4 { THICKNESS=0.7 ER=3.9 }
$ D4 thickness measured from D3
CONDUCTOR M1 { THICKNESS=0.4 WMIN=0.4 SMIN=0.4 RPSQ=0.05 }
DIELECTRIC D3 { THICKNESS=0.6 ER=3.9 }
$ D3 thickness measured from D21
CONDUCTOR LI { THICKNESS=0.3 WMIN=0.4 SMIN=0.4 RPSQ=1 }
$ LI thickness measured from top of D21
CONDUCTOR POLY { THICKNESS=0.2 WMIN=0.2 SMIN=0.2 RPSQ=10.0 }

$ POLY thickness measured from top of D21

DIELECTRIC D21 { THICKNESS=0.2 ER=3.9 }

VIA LI_SUB { FROM=SUBSTRATE TO=LI AREA=0.25 RPV = 4 }


VIA CONT { FROM=LI TO=M1 AREA=0.25 RPV=5 }
VIA V1 { FROM=M1 TO=M2 AREA=0.25 RPV=4 }

Figure A-28 Local Interconnect

TOP
1.2
M2 0.4

D4 0.7
0.4 M1

D3 0.6
0.2 POLY LI 0.3
D21 0.2

SUBSTRATE

Chapter A: ITF Examples


ITF Examples
Local Interconnect Process A-5
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Dielectric Air Gaps Process


The following ITF statements describe the dielectric air gaps process shown in Figure A-29.
TECHNOLOGY = airgap
DIELECTRIC TOP { THICKNESS=3.4 ER=3.9 }
DIELECTRIC D3 { THICKNESS=0.2 ER=4.7 }
CONDUCTOR M2 { THICKNESS=0.6 WMIN=0.5 SMIN=0.5 RPSQ=0.05 }
DIELECTRIC D2 { THICKNESS=1.2 ER=3.9 }
CONDUCTOR M1 {THICKNESS=0.5 WMIN=0.3 SMIN=0.3 RPSQ=0.05
AIR_GAP_VS_SPACING {
SPACINGS {0.3 0.5 0.7 1.0 3.0}
AIR_GAP_WIDTHS {0.1 0.09 0.09 0.08 0.07}
AIR_GAP_THICKNESSES {0.2 0.23 0.25 0.26 0.28}
AIR_GAP_BOTTOM_HEIGHTS {0.1 0.14 0.18 0.20 0.22}}
DIELECTRIC D1 { THICKNESS=0.725 ER=3.9 }
CONDUCTOR POLY{ THICKNESS=0.125 WMIN=0.3 SMIN=0.3 RPSQ=10.0 }
DIELECTRIC D0 { THICKNESS=0.375 ER=3.9 }
VIA sub_tie { FROM=SUBSTRATE TO=M1 AREA=0.25 RPV=5 }
VIA poly_cont { FROM=POLY TO=M1 AREA=0.25 RPV=4 }
VIA via { FROM=M1 TO=M2 AREA=0.36 RPV=4 }

Figure A-29 Dielectric Air Gap Process


S = spacing between neighboring lines
(SPACINGS)
W= width of the air gap
TOP 3.4 (AIR_GAP_WIDTH)
T= thickness of the air gap formed
M2 (AIR_GAP_THICKNESS)
B= height of the bottom of the airgap
0.6 from the bottom of metal
D3 0.2 (AIR_GAP_BOTTOM_HEIGHT)
L= spacing between the metal and air gap.
W ((S-W) /2)
D2 1.2
1.6
L AIR T
M1 M1
B

S
D1 0.725
0.125 POLY
D0 0.375

SUBSTRATE

ITF Examples A-6


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Layer Etch Process


The following ITF statements describe the layer etch process shown in Figure A-30.
TECHNOLOGY = etch
DIELECTRIC TOP { THICKNESS=3.4 ER=3.9 }
DIELECTRIC D3 { THICKNESS=0.2 ER=3.9 }
CONDUCTOR M2 {
THICKNESS=0.6 WMIN=0.5 SMIN=0.5 RPSQ=0.05
ETCH=0.1 }
DIELECTRIC D2 { THICKNESS=1.2 ER=3.9 }
CONDUCTOR M1 {
THICKNESS=0.6 WMIN=0.3 SMIN=0.3 RPSQ=0.05
ETCH=0.05 }
DIELECTRIC D1 { THICKNESS=0.725 ER=3.9 }
CONDUCTOR POLY{ THICKNESS=0.125 WMIN=0.3 SMIN=0.3 RPSQ=10.0 }
DIELECTRIC D0 { THICKNESS=0.375 ER=3.9 }

VIA sub_tie { FROM=SUBSTRATE TO=M1 AREA=0.25 RPV=5 }


VIA poly_cont { FROM=POLY TO=M1 AREA=0.25 RPV=4 }
VIA via { FROM=M1 TO=M2 AREA=0.36 RPV=4 }

Figure A-30 Layer Etch Process

TOP 3.4

M2 0.6
D3 0.2

D2 1.2
M1 0.6

D1 0.725
0.125 POLY
D0 0.375

SUBSTRATE

Chapter A: ITF Examples


ITF Examples
Layer Etch Process A-7
Interconnect
Interconnect Technology
Technology Format
Format Specification
Specification 2015.06
Version 2015.06

Metal Fill Process (Emulated)


The following ITF statements describe the metal fill process shown in Figure A-31.
TECHNOLOGY = metal_fill
DIELECTRIC TOP { THICKNESS=3.4 ER=3.9 }
DIELECTRIC D3 { THICKNESS=0.2 ER=3.9 }
CONDUCTOR M2 {
THICKNESS=0.6 WMIN=0.5 SMIN=0.5 RPSQ=0.05
DIELECTRIC D2 { THICKNESS=1.2 ER=3.9 }
CONDUCTOR M1 {
THICKNESS=0.6 WMIN=0.3 SMIN=0.3 RPSQ=0.05
FILL_RATIO=0.4 FILL_SPACING=1.0 FILL_WIDTH=2.0 }
DIELECTRIC D1 { THICKNESS=0.725 ER=3.9 }
CONDUCTOR POLY{ THICKNESS=0.125 WMIN=0.3 SMIN=0.3 RPSQ=10.0 }
DIELECTRIC D0 {THICKNESS = 0.375 ER = 5.2}

VIA sub_tie { FROM=SUBSTRATE TO=M1 AREA=0.25 RPV=5 }


VIA poly_cont { FROM=POLY TO=M1 AREA=0.25 RPV=4 }
VIA via { FROM=M1 TO=M2 AREA=0.36 RPV=4 }

Figure A-31 Metal Fill Process (Emulated)

TOP 3.4

M2 0.6
D3 0.2

2.0 1.0
D2 1.2
M1FILL M1 0.6

D1 0.725
0.125 POLY
D0 0.375

SUBSTRATE

ITF Examples A-8


Interconnect Technology Format Specification Version 2015.06

Transistor-Level Process
The following ITF statements describe the transistor-level process shown in Figure A-32.
TECHNOLOGY=xtor
DIELECTRIC TOP { THICKNESS=3.40 ER=4.3 }
DIELECTRIC D3 { THICKNESS=0.20 ER=3.9 }]
CONDUCTOR M2 { THICKNESS=0.60 WMIN=0.55 SMIN=0.50 RPSQ=0.062 }
DIELECTRIC D2 { THICKNESS=1.20 ER=3.9 }
CONDUCTOR M1 { THICKNESS=0.60 WMIN=0.50 SMIN=0.45 RPSQ=0.062 }

DIELECTRIC D1 { THICKNESS=0.75 ER=3.9 }


CONDUCTOR FP{ THICKNESS=0.30 WMIN=0.35 SMIN=0.40 RPSQ=3.200 }
DIELECTRIC FOX { THICKNESS=0.20 ER=3.9 }
CONDUCTOR GP{ THICKNESS=0.30 WMIN=0.35 SMIN=0.40
RPSQ=3.200 }
DIELECTRIC GOX { THICKNESS=1.02 ER=5.0 }
CONDUCTOR DF{ THICKNESS=1.00 WMIN=1.00 SMIN=0.35
RPSQ=10.00 }
DIELECTRIC D0 { THICKNESS=0.50 ER=3.9 }

VIA via1 { FROM=M1 TO=M2 RHO=0.263 }


VIA pCont { FROM=FP TO=M1 RHO=0.352 }
VIA dCont { FROM=DF TO=M1 RHO=0.500 }
VIA sCont { FROM=SUBSTRATE TO=M1 RHO=0.600 }

Figure A-32 Transistor-Level Process

TOP 3.40

M2
D3 0.20
via1

D2 1.20

M1 M1
pCont

D1 0.75
dCont

sCont

FP
FOX 0.20 GP
GOX 1.02 DF
D0 0.50

SUBSTRATE

Chapter A: ITF Examples


ITF Examples Process
Transistor-Level A-9
Interconnect
Interconnect Technology
Technology Format
Format Specification
Specification 2015.06
Version 2015.06

Through-Silicon Via Process


The following ITF statements describe the through-silicon via process shown in Figure A-33.
The TSV statement must be placed after the frontside ITF statements and before the
backside ITF statements.
TECHNOLOGY = tsv_process
GLOBAL_TEMPERATURE = 25.0

$ Frontside ITF statements


CONDUCTOR M1 {
THICKNESS=0.3 WMIN=0.12 SMIN=0.12 SIDE_TANGENT=0.2
CRT1=7.0e-03 CRT2=-8.0e-07
}
DIELECTRIC ILD_B { ER=5.5 THICKNESS=0.5 }
DIELECTRIC GATE_OXIDE { ER=4.3 THICKNESS=0.03 }
DIELECTRIC FOXIDE_A { ER=5.0 THICKNESS=0.1 }
CONDUCTOR DIFFUSION {
THICKNESS=0.1 WMIN=0.1 SMIN=0.06
CRT1=8.0e-03 CRT2=-1.0e-07 RPSQ=36.0
}
DIELECTRIC FOXIDE { ER=5.0 THICKNESS=0.2 }
VIA via1 { FROM=M1 TO=M2 AREA=0.03 RPV=2.5 CRT1=3.0e-04 CRT2=-6.0e-06 }

$ TSV statement
TSV tsv {
FROM=M1 TO=M1b RHO=0.05 AREA=49.0 THICKNESS=20.0
INSULATION_THICKNESS = 0.4 INSULATION_ER = 5.5
CRT1=7.0e-03 CRT2=-3.0e-08
}

$ Backside ITF statements


DIELECTRIC PASS { ER=9.0 THICKNESS=2.0 }
DIELECTRIC DIELb { ER=5.0 THICKNESS=1.0 }
CONDUCTOR M1b {
THICKNESS=2.0 WMIN=4.0 SMIN=4.0 SIDE_TANGENT=-0.2
CRT1=1.0e-03 CRT2=-7.0e-07
}
DIELECTRIC ILDB{ ER=5.2 THICKNESS=1.0 }

Note:
The locations of the backside dielectric layers ILDB and PASS with respect to the
substrate are shown in Figure A-33.

ITF Examples A-10


Interconnect Technology Format Specification Version 2015.06

Figure A-33 Cross Section of Through-Silicon Via

FRONT
insulation TSV
thickness thickness
SUBSTRATE
TSV insulator

ILDB
BACK
PASS

insulating layers through-silicon via substrate

device layers TSV insulator passivation

M1 backside metal

Chapter A: ITF Examples


ITF Examples Via Process
Through-Silicon A-11
Interconnect
Interconnect Technology
Technology Format
Format Specification
Specification 2015.06
Version 2015.06

Trench Contact Process


The following example shows a trench contact process definition in the ITF file.
CONDUCTOR TC {
THICKNESS=0.05 WMIN=0.025 SMIN=0.060 RPSQ=1.0
GATE_TO_CONTACT_SMIN=0.02
LAYER_TYPE=TRENCH_CONTACT
}

DIELECTRIC D4 {THICKNESS=0.015 ER=4.5 MEASURED_FROM=D3 }

DIELECTRIC DC_POLY {
THICKNESS=0.0 ER=7.0
IS_CONFORMAL ASSOCIATED_CONDUCTOR=POLY
SW_T=0.01 TW_T=0.005
}

CONDUCTOR POLY {
THICKNESS=0.03 WMIN=0.045 SMIN=0.045 RPSQ=1.0
GATE_TO_CONTACT_SMIN=0.02
LAYER_TYPE=GATE
}
DIELECTRIC D3 {THICKNESS=0.001 ER=2.8 }
DIELECTRIC D2 {THICKNESS=0.05 ER =3.4 }

CONDUCTOR DIFF {
THICKNESS=0.05 SMIN=0.045 WMIN=0.06 RPSQ=1.0
RAISED_DIFFUSION_THICKNESS = 0.015
RAISED_DIFFUSION_TO_GATE_SMIN = 0.014
RAISED_DIFFUSION_ETCH = 0.010
LAYER_TYPE=DIFFUSION
}

DIELECTRIC D1 { THICKNESS=0.1 ER=6.8}

ITF Examples A-12