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qxd 7/5/05 10:48 AM Page 1

Vol. III, Issue 8


DESIGN idea: Serial LVDS Improves Routing

Featured Products
Differential, High-Speed Op Amps Low-Power, High-Performance Quad 12-Bit A/D
The LMH6550 and LMH6551 Converter with Serialized LVDS Outputs
are high-performance voltage The ADC12QS065 is a low-power, high-performance, 4-channel
feedback differential amplifiers. analog-to-digital converter with serialized LVDS outputs. This
The fully differential topology A/D converter digitizes signals to 12-bit resolution at sampling
allows balanced inputs to the rates up to 65 MSPS while consuming a typical 187.5 mW per
ADCs and can be used as ADC from a single 3.0V supply. Sampled data is transformed into
single-ended-to-differential or high-speed serial LVDS output data streams. Clock and frame
used as differential-to-differential. These amplifiers also have the LVDS pairs aid in data capture. The six differential pairs of the
high speed and low distortion necessary for driving high-performance ADC12QS065 transmit data over backplanes or cable and simplify
ADCs, as well as the current-handling capability to drive signals PCB design. In addition, the reduced cabling, PCB trace count,
over balanced transmission lines like CAT-5 data cables. The and connector size greatly reduce system cost.
LMH6550/51 can handle a wide range of video and data formats. Features
With external gain set resistors, the LMH6550/51 can be used at I Serialized LVDS outputs allow for lower pin count packages
any desired gain. Gain flexibility coupled with high speed makes I Saves space for number of channels
these amplifiers suitable for use as IF amplifiers in high-perform-
ance communications equipment.
I Pin assignment optimized for board layout
LMH6550 Features
I Low power consumption
I Excellent signal-to-noise ratio, THD, and crosstalk
I 400 MHz, -3 dB bandwidth (VOUT = 0.5 VPP)
I Samples signals as fast as 65 MSPS
I 90 MHz, 0.1 dB bandwidth
I -92/-103 dB HD2/HD3 at 5 MHz (changed order)
I 3000 V/s slew rate
I -68 dB balance error (VOUT = 1.0 VPP, 10 MHz)
I 10 ns shutdown/enable
LMH6551 Features
I 370 MHz, -3 dB bandwidth (VOUT = 0.5 VPP)
I 50 MHz, 0.1 dB bandwidth
I -94/-96 dB HD2/HD3 at 5 MHz (changed order)

I 2400 V/s slew rate

I -70 dB balance error (V

OUT = 0.5 VPP, 10 MHz) The speed, resolution, and single-supply operation of the
I Single +3.3V, +5V, or 5V supply voltages ADC12QS065 make it well suited for a wide variety of applica-
tions in ultrasound, medical imaging, communications, portable
The LMH6550/51 is ideal for use in applications requiring a differ-
instrumentation, and digital video.
ential A/D driver, video twisted pair, differential line driver, single
end-to-differential converter, high-speed differential signaling, Operating over the industrial (-40C to +85C) temperature range,
IF/RF amplifier, or SAW filter buffer/driver. the ADC12QS065 is available in a TQFP-64 package.
The LMH6550/51 are available in the space-saving SOIC-8 and
MSOP-8 packaging.
AD_3025_AnalogEdgeV3_Issue8_no_Ad.qxd 7/5/05 10:48 AM Page 2

Robert LeBoeuf
Senior IC Design Engineer
National Semiconductor

Data Converter Serial LVDS Interface Improves Board Routing

After the input signals are converted to The ADC12QS065 contains four 12-bit

ystems often require signaling
where common-mode signals are digital data, they must be transmitted to ADCs in one chip. Each of its inputs
not welcome or difficult to handle. a DSP or an ASIC/FPGA for processing. accepts fully-differential signals. The input
Some designs turn single-ended signals This is where fully-differential output common-mode voltage may be derived
from the output of transducers to fully signaling can come in handy. Output from the common-mode output reference
differential signals, then send this signal signals that are fully differential source voltages VCOM12 and VCOM34 that
to a differential-input ADC downstream. and sink a current through two symmetric are supplied by the ADC12QS065. The
The advantage of this is that most noise lines. An example of such signaling is ADC12QS065 also has the option of
that gets introduced on this differential the LVDS (Low Voltage Differential using a fully-differential, or single-ended
line is common to both lines. (This is Signal) format. The ADC12QS065 uses clock source. To utilize the LVDS clock
assuming that the differential lines are LVDS to solve all of these system issues simply provide LVDS signals to the CLK
laid out symmetrically.) (Figure 1). and CLKB, terminating close to the input

12-Bit 12 100
VIN1+ ADC Core CH1 Serialized LVDS Out

VCOM12 100

VIN2- CH2 Serialized LVDS Out

12-Bit 12
VIN2+ ADC Core 100

Differential FRAME LVDS Out

Serializer Ring
Oscillator 100
VIN3- 12 Clock LVDS Out
VIN3+ ADC Core
CH3 Serialized LVDS Out
VIN4- 12
ADC Core 100
CH4 Serialized LVDS Out



LVDS Clock In

Figure 1. ADC12QS065 Simplified Block Diagram
AD_3025_AnalogEdgeV3_Issue8_no_Ad.qxd 7/5/05 10:48 AM Page 3

Robert LeBoeuf
enior IC Design Engineer
MSB LSB MSB ADC, or kept separate. Separate supplies
DATA OUT BIT 1 BIT 11 further isolate each part of the internal
BIT 11 BIT 10 BIT 9 BIT 0
National Semiconductor (CH A-D)
circuitry of the ADC. This may be
CLOCK OUT achieved with one supply and passive filters
LVDS employed at each power supply input, or
OUT separate supplies altogether. Another
d Routing Figure 2. Output Timing Diagram
advantage separate supplies is the output
driver voltage may be reduced as low as
2.5V, to save on power consumption.
pins. If a single-ended CMOS clock is Because LVDS uses current from the The ADC12QS065 also has the ability
desired, then CLKB is tied low, and no supply by steering current from one to have its internal references powered
termination resistor is required. LVDS terminal or the other, current is down to allow the reference to be driven
The output of each ADC gets serialized constantly being drawn from the supply. externally. This allows multiple ADCs to
using a differential ring oscillator. The This reduces the switching load that be ganged together, by connecting all
input clock input is multiplied by 12, would otherwise be present on the supply the VREFPs and VREFNs together,
and converted to an LVDS clock output lines. The advantage to this is that lower respectively. This eases system calibration
for data capture. An LVDS FRAME signal, supply noise is induced on the supply requirements by helping to insure that
at the input clock rate, is also generated line, reducing the decoupling capacitor the gain and offset of each chip match.
at the output to identify the sample size, and relaxing layout requirements. Its clear that if systems allow for differ-
number (Figure 2). Serial LVDS allows for an even smaller ential signaling, it is advantageous in
The output timing offers easy data capture package and is very effective in signal terms of low common-mode noise
for an FPGA. The output FRAME signals transmission. In many applications, induction, reduced power supply tran-
when sampled data is ready to be sent. however, low power consumption is very sients, and low digital radiation on the
The MSB of each of the 4 output channels important. Every milliwatt of power output lines. The ADC12QS065 offers a
is present, followed by an LVDS saved per channel makes a significant fully-differential conversion, from the
CLOCK OUT transition. The LVDS difference in systems requiring several analog input, clock input, to the serialized
CLOCK OUT signal is offset from the channels of data. Therefore, in addition LVDS outputs. This ability to separate the
DATA OUT by a quarter cycle to ease to quiet drivers, the ADC12QS065 has power supplies allows for further analog-
clock management. Each data bit is three separate power supplies. Each supply digital domain separation, and offers lower
captured on a CLOCK OUT transition. can be connected making it a single-supply power consumption. I
Another advantage of using LVDS is that
these signals may be sent down a twisted
pair that uses the EIA/TIA 568 standard.
Twisted pairs that meet this standard
12-Bit Data
have a characteristic impedance of 100. Channel 1
Conductors that are close together and
Channel 1
carry opposite currents produce very low Clock Out Channel 2
radiation. This is welcome in areas where 4-Channel Clock Out
Or 4-Channel Frame
high SNR requirements are present. 12-Bit ADC
12-Bit Data 12-Bit ADC
Channel 3
Channel 2
To further illustrate this point, Figure 3 Channel 4
shows two 4-channel, 12-bit ADCs. The 12-Bit Serialized
ADC on the left has the traditional single- LVDS Data
ended parallel CMOS output. 49 traces
are required (4x12+1) to send the con-
12-Bit Data
verter output to the digital processor. If Channel 4 Serialized LVDS Output
the output bits are serialized, each channel
would have a single pair of differential Single-Ended Non-Serialized Output
lines. An output clock and frame signal
wires are also illustrated. Figure 3. CMOS vs LVDS Board Layout Comparison

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AD_3025_AnalogEdgeV3_Issue8_no_Ad.qxd 7/5/05 10:48 AM Page 4

Featured Products
High-Performance, Low-Power, Dual 8-Bit,
500 MSPS A/D Converter
The ADC08D500 is the industrys lowest power dual 8-bit
500 MSPS analog-to-digital converter. It digitizes two signals to
8-bit resolution at sampling rates up to 800 MSPS or one signal
at sampling rates up to 1.6 GSPS. Consuming a typical 1.4 W at
500 MSPS from a single 1.9V supply, this device is
guaranteed to have no missing codes over the full operating
temperature range. The unique folding and interpolating
architecture, the fully differential comparator design, the
innovative design of the internal sample-and-hold amplifier,
and the self-calibration scheme enable a very flat response of Dual 12-Bit, 65 MSPS, 3.3V, 360 mW A/D
all dynamic parameters beyond Nyquist. Converter
Features The ADC12DL065 is a dual, low-power CMOS analog-to-digital
I 7.5 Effective Number of Bits (ENOB) at Nyquist (typ) converter capable of converting analog input signals into 12-bit
I Bit error rate 10-18 (typ)
digital words at 65 MSPS. This converter uses a differential,
I Single +1.9V (0.1V) operation
pipeline architecture with digital error correction and an on-chip
sample-and-hold circuit to minimize power consumption while
I Interleave mode for 2x sampling rate
providing excellent dynamic performance and a 250 MHz full
I Choice of SDR or DDR output clocking
power bandwidth. Operating on a single +3.3V power supply, the
I Multiple ADC synchronization capability ADC12DL065 achieves 11.0 effective bits at Nyquist and consumes
I Serial interface for extended control just 360 mW at 65 MSPS, including the reference current. The
I Fine adjustment of input full-scale range and offset
power down feature reduces power consumption to 36 mW.
I11.0 ENOB at Nyquist (typ)
ISNR = 68.5 dBc with fIN = 10 MHz (typ)
I SFDR = 85 dBc with f
IN = 10 MHz (typ)
I Consumes only 360 mW at 65 MSPS

I Outputs 2.4V to 3.6V compatible

I Power down mode

I Duty cycle stabilizer

I Multiplexed output mode simplifies board routing

The ADC12DL065 is ideal for use in ultrasound and imaging,

instrumentation, communications receivers, sonar/radar, xDSL,
The ADC08D500 is ideal for use in direct RF down conversion, cable modems, and DSP front ends.
digital oscilloscopes, satellite set-top boxes, communications This device is available in a TQFP-64 package and will operate over
systems, and test instrumentation. the industrial temperature range of -40C to +85C.
This A/D converter is available in a thermally-enhanced exposed
pad LQFP-128 and operates over the industrial (-40C to +85C)
temperature range.

National Semiconductor Corporation, 2005. National Semiconductor , , and LMH are registered trademarks and Analog Edge is a service mark of National Semiconductor Corporation.
All other brand or product names are trademarks or registered trademarks of their respective holders. 570102-025