Introduction to n-well CMOS Fabrication

Dr. D. V. Kamat
Professor, Department of E&C Engg.,
Manipal Institute of Technology, Manipal

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 MOS Fabrication

CMOS fabrication
N-well process
P-well process
Twin-tub process

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 n-well CMOS process

The n-well CMOS structure consists of an p-type

substrate and a deep n-well is diffused in to the p-type
substrate
The n-well acts as substrate for the p-devices within the
parent p-substrate
n+ Mask [positive] is used for n-diffusion
n+ Mask [negative] or p+ Mask is used for p-diffusion

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n-well CMOS process steps

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 n-well CMOS process
Selection of Substrate: Starting material is a moderately doped (with impurity
concentration typically less than 1015 cm-3) p-type silicon substrate

p - type Si

Thick oxide formation : p-type substrate is cleaned and a SiO2 (1 m) layer is formed
using oxidation
SiO2

p - type Si

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 n-well CMOS process
Lithography (MASK1) for defining window for n-well
UV

MASK 1

Positive Photoresist
SiO2

p - type Si

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 n-well CMOS process
Removal of solvable photo resist using organic solvents

SiO2

p - type Si

Etching of unprotected thick oxide using HF (Hydrofluoric acid)

SiO2

p -type Si
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 n-well CMOS process
Removal of hardened photo resist by oxide cleaning and PR etching
SiO2

p - type substrate

N-well Formation [4-5 m] using diffusion or ion implantation

N-type impurity implantation

SiO2

N-Well
p - type substrate
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 n-well CMOS process
Thinox Formation : Oxide cleaning and formation of thin oxide using gate oxidation
THINOX

N-Well
p - type substrate

Deposition of Polysilicon over thinox using chemical vapor deposition (CVD)

POLYSILICON
THINOX

N-Well
p - type substrate

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 n-well CMOS process

Lithography(MASK2) to patternize polysilicon

POSITIVE PHOTORESIST
POLYSILICON
THINOX

N-Well
p - type substrate

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 n-well CMOS process
Removal of soluable photo resist and uncovered polysilicon

THINOX

N-Well
p - type substrate

Removal of the remaining hardened photoresist.

THINOX

N-Well
p - type substrate

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 n-well CMOS process
Lithography(MASK3)

Use n+ MASK (MASK 3) to define area for n-diffusion

POSITIVE PHOTORESIST
THINOX

N-Well
p - type substrate

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 n-well CMOS process
Defining windows for n-diffusion
Removal of photoresist
Removal of uncovered thinoxide using HF (Hydrofluoric acid)

N-Well
p - type substrate

THINOX

N-Well
p - type substrate
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 n-well CMOS process
Formation of n+ regions (diffusion or ion implantation)

Formation of n+ regions using diffusion (by diffusing

pentavalent impurity atoms ) or ion implantation

N+ N+ N+

N-Well
p - type substrate

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 n-well CMOS process

Lithography p+ MASK (MASK4) for PMOS

Similar steps (MASK 4) are used to create p diffusion

regions

P+ N+ N+ P+ P+ N+

N-Well
p - type substrate

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 n-well CMOS process

Thick Oxide Deposition

Cover the entire surface with thick oxide layer

P+ N+ N+ P+ P+ N+

N-Well
p - type substrate

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 n-well CMOS process

Lithography (MASK 5) for Oxide Patterning

Oxide layer is masked with photoresist and etched to
expose selected areas where contact cuts are to be made.

P+ N+ N+ P+ P+ N+

N-Well
p - type substrate

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 n-well CMOS process
Metallization and MASK 6 for Metal Patterning
Vin
VSS VDD

Vout

P+ N+ N+ P+ P+ N+

N-Well
p - type substrate

Connections are made to drain, source and gate using aluminum metal layer

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 Steps involved in n-well CMOS process
1 Formation of p-type silicon substrate
2 Cleaning of silicon substrate and Thickoxide formation
3 Lithography(MASK1) to define window for n-well formation
Developing positive photoresist over thickox layer
Exposure to UV light through Mask1 and removal of soluable photoresist
Removal of unprotected thickox using HF (Hydrofluoric acid) followed by removal
of hardened photoresist by oxide cleaning and PR etching
4 N-well Formation using diffusion or Ion Implantation
5 Lithography(MASK2) to patternization of polysilicon
Etching thickoxide layer
Deposition of thinoxide layer
Deposition of polysilicon layer using CVD
Pattern polysilicon layer using MASK2
6 Lithography (Mask 3) to define area for n-diffusion
Pattern thinox layer using MASK3
7 Formation of n+ regions by diffusion or ion implantation
8 Lithography (Mask 4) to define area for p-diffusion and Formation of p+ regions by
diffusion or ion implantation
9 Deposition of thickoxide and Lithography (Mask 5) to patternize thickoxide
10 Metallization and MASK 6 for Metal Patterning
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 n-well CMOS process steps

CMOS Inverter with n-well and p-substrate contacts

N-well fabrication has also gained wide acceptance
N-well CMOS circuits are also superior to p-well because of the lower
substrate bias effects on transistor threshold voltage and inherently
lower parasitic capacitances associated with source and drain regions.
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 Contact

reachdvkamath@yahoo.com
dv.kamath@manipal.edu

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