Construction and calibration of a

Lock-in amplifier
G Gurunadha Reddy
7th semester, SPS
NISER
Dt: 09/10/2017

Course # P441 lab

Instructor: Dr Ashok Mohapatra

Abstract
Precision experiments involve special techniques to obtain the small signal from noise,
magnitudes greater than the signal itself. Such is the phase sensitive detection technique.
A lock-in amplifier is a device which utilizes this technique to perform detections which
may seem like finding a needle in a haystack. This experiment is aimed to learn the theory
of PSD and to design simple lock-in amplifier to test the same. The working and utilization
of the lock-in amplifier was learnt and implemented. The final part of the experiment
involves measuring an unknown resistance. This has been successfully completed and the
observations of each stage were recorded.
Contents

1. Introduction

2. Lock-in amplifier
a. Phase sensitive detector
b. Band-width and noise reduction

3. Construction and working

a. Pre-amplifier
b. Phase shifter
c. Low pass filter
d. Phase sensitive detector (AD630)

4. Debugging

5. Calibration of Lock-in

6. Measurement of unknown resistance

7. Sources of error

8. Conclusion

9. References
Introduction
In signal detection it is often the case that a signal is overwhelmed by noise. Usual
amplification of the signal also unnecessarily amplifies the noise. One of the main
challenges is to isolate and obtain the signal with minimal loss. The signal is usually
within a narrow frequency band whereas, the noise can span over a wide range of
frequencies. At low frequencies, the flicker noise, which is inversely proportional to the
operating frequency, is ever-present in electronic circuits. The noise due to
electromagnetic pickup from motors and choke circuits has its power spectrum at the
frequency of motor or the mains. The Johnson-Nyquist noise, which is of thermodynamic
origin, spans over all frequencies. It is approximately equivalent to white noise and varies
with temperature T as
< ( )2 > = 4

Where, the LHS term represents the mean square fluctuation of voltage and is the
frequency bandwidth. These noises can be respectively minimized by working at higher
frequencies, electromagnetic shielding and reducing the temperature or bandwidth of
amplifier. At room temperature, weak signal detection is achieved by minimizing the
bandwidth of the amplifier to the frequency range of the signal. This is usually achieved
by a lock-in amplifier.

The speciality and working of lock-in amplifiers is explained in the following chapters of
the report and experiments which have been designed to test its effectiveness are also
discussed.

Lock-in amplifier
A lock-in amplifier is a narrow band pass filter attached to a phase-sensitive detector
followed by a low pass filter. It can extract signal from an extremely noisy background
with the help of a carrier or reference waveform. To achieve optimum clarity in the signal
detection, the frequency of the reference wave must be close enough to that of the signal.
State-of-art lock-ins utilize digital signal processors for phase sensitive detection whereas
the traditional models rely on synchronous demodulation technique. The working of a
lock-in amplifier can be algorithmically represented in four sections as shown in Fig. 1.

Signal in DC out
Signal Low
channel Mixer pass filter

Reference
channel

Reference in
Fig. 1. Working of a Lock-in Amplifier
The signal channel comprises of a preamplifier to amplify the weak signal input and a
bandpass filter to select only the band which accommodates the signal. Background noise
outside the selected band is eliminated in this channel. The reference channel comprises
of a phase-shifter for shifting the phase of reference input. A weak signal is often
modulated with a high frequency carrier waveform to eliminate the 1/ noise. The
demodulation or phase sensitive detection process occurs at the mixer channel by
combining the outputs of both reference and signal channels. The output from the mixer
passes through a narrow low-pass filter to give an almost DC output. The greatest
contribution in noise reduction is from the mixer and the low-pass filter sections. These
sections are explored in the later chapters.

The principle of phase sensitive detection, which forms the core of a lock-in amplifier, is
discussed in detail in the following section.

Phase sensitive detector (PSD)

Lock-in amplifier earns it name from the eponymous lock-in or the phase sensitive
detector mechanism. The mixer block shown in Fig. 1. is where the lock-in process is
carried out. The principle of PSD is to blend the reference waveform with the signal input
so that, the frequencies extremely close to the reference, i.e. only the required signal
shows up in the output. So, the reference frequency should by synchronised with the pure
signal for successful detection. Thus, all noise (non-synchronous inputs) can be eliminated
using a lock-in amplifier.

Highly accurate lock-ins employ digital signal processors for PSD whereas, analog ones
such as the one built in this experiment rely on synchronous demodulation. The PSD used
in this experiment can be visualized as an electronic reversing switch whose position is
determined by the polarity of the reference waveform. The switch is used to power an
inverting or a non-inverting amplifier, one at a time such that the output is synchronously
demodulated.
1
Lets consider a signal denoted by sin() and reference by 2 ( + ), where is the
phase shift of the reference wave. The reference wave can be of any shape but should have
same frequency as the signal. Now the PSD flips the sign of signal wave if the reference
is negative (or positive) at a given time and leaves it unchanged if the reference is positive
(or negative). This can be graphically visualized as follows.

1.0

0.5

2 4 6 8 10 12

0.5

1.0

Fig. 2. Reference lags the signal by = /4

1.0

0.5

2 4 6 8 10 12

0.5

1.0

Fig. 3. Reference lags the signal by = /2

1.0

0.5

2 4 6 8 10 12

0.5

1.0

Fig. 4. Reference lags the signal by =

1.0

0.5

2 4 6 8 10 12

0.5

1.0

Fig. 5. Reference and signal are in phase

Clearly, the PSD output voltage is dependent on the amplitude of only the signal,
frequency of both reference and signal waveforms and the phase difference between them.
This output from PSD passes through the low-pass filter, where any AC component is
bypassed to earth to give a DC output. If the signal waveform is sin() and the gain of
lock-in amplifier is , the final DC output of the lock-in amplifier can be calculated as
follows.
sin() for 0 +
= {
sin() for + 2
By calculating the area under the output graph for range [0,2] we obtain .
2

= { sin() sin()}
2

1
= {() ( ) ( ) + (2 )}
2
2
= cos()

Notice that the DC output of lock-in amplifier is only dependent. The amplifier locks in
phase of the signal with the phase shifted reference, thus giving the amplifier its name.
2
When the reference and signal are in phase, the DC output is maximum ( =
)
2
Similarly, the minimum ( =
) occurs at a phase shift of .

Bandwidth and Noise reduction

Modern lock-in amplifiers utilize digital logic to multiply the reference and signal for
phase sensitive detection. Suppose we have noise at a frequency different from the
frequency of the reference signal. So, the output of PSD can be written as
= sin() sin( + )

where, = sin( + )
1
= 2 {cos(( ) ) + cos(( + ) + )}

The output frequency is thus, a mixture of sum and difference of signal and reference
frequencies. After passing through the narrow low-pass filter, the output becomes nearly
DC with extremely low frequencies contributing to the output. So, the (( + ) + )
term is always filtered out and the (( ) ) term contributes to the DC output
only if ( ) is very small. The contribution of this noise to drops rapidly as
1
differs from . At = , the output is pure DC which is equal to 2 cos().

If , the integration time is large compared to the period of the reference signal, then only
noise frequencies differing from by / (where is a small number) will contribute to
VDC. Thus, the effective bandwidth of the lock-in amplifier is /. This implies that the
effective bandwidth W is a few Hz. So, one can understand how thermal noise and other
noises are suppressed by the lock-in amplifier.
Construction and Working
This section deals with the construction of individual channels of the lock-in amplifier.
Their working is demonstrated, and the data is recorded and interpreted. The pin
diagrams of ICs used are given in the Appendix section.

The Pre-amplifier
Often the signal is very small to be fed into the PSD. So, the pre-amplifier is used to
amplify the signal before further processing. It makes up the signal channel of this lock-
in amplifier.

Components: R1 = 1M, R 2 = 100 and OP07 amplifier

Fig. 6. Pre-amplifier circuit

The output of this preamp configuration is

1
= (1 + )
2

The pre-amplifier used in this experiment has gain (1 + 1 ) 104 .
2

There can also be a bandpass filter connected to the output of pre-amplifier, but this had
been omitted in this experiment as the signal was directly taken from the function
generator.
Phase Shifter
The reference signals phase should be adjusted to obtain maximum DC output from the
lock-in amplifier. So, a phase shifter is placed in the reference channel.

Components: R 3 = 9.91K, R 4 = 9.98K, Potentiometer R 5 = 0 to 22K, 1 = 107.7 and

OP07 amplifier

Fig. 7. Phase shifter circuit

If is the angular frequency of the reference waveform then, by using Kirchoffs Laws
and phasor algebra, we obtain

The current through capacitor 1 and 5 is 5 = (1/ + 5 )1 (1)

The current through resistors 3 and 4 is 3 = 5 3 (2)

And the output voltage = 3 (3 5 4 ) (3)

From equations 1, 2 and 3 we obtain

(3 5 4 )
=
3 (1 + 5 )

In this circuit as 3 = 4 , if 5 = 0 then we obtain = . So, the phase shift is 180

or radians when the non-inverting voltage is shorted to the ground. Similarly, for large
enough value of 5 we obtain i.e. the phase shift is 0 at saturation.The
amplitude of the output isnt significantly changed if the frequency is below 10KHz. These
results can be verified from the following observations.
Table. 1. Resistance 5 vs. Delay (phase shift)

Freqency(KHz Freqency(KHz
( ) ) Delay (s) ( ) ) Delay (s)
0 -495 0 -100
0.04 -485 0.03 -105
0.49 -420 0.05 -91
0.92 -360 0.1 -82
1.3 -315 0.16 -75
1.74 1 -265 0.26 5 -63
2.28 -225 0.37 -53
3.04 -185 0.45 -47
4.16 -145 0.66 -37
5.94 -100 0.81 -29
9.96 -70 1.11 -22.5
1.61 -16
3.1 -8
9.97 -5

Resistance 5 vs. Delay (phase shift) for 1KHz

0
-2 0 2 4 6 8 10 12
-100

-200
Delay [/) in s

-300

-400

-500

-600
Resistance R5 in (K)

Resistance 5 vs. Delay (phase shift) for 5KHz

0
0 2 4 6 8 10 12
-20
Delay [/) in s

-40

-60

-80

-100

-120
Resistance R5 in (K)
Low pass filter
The output of the PSD has AC component from the signal and also due to noise. So, a
narrow low pass filter is used to bypass these components to the ground and obtain a
nearly DC output. The narrower the filter, greater the efficiency in giving DC output.

Components: 6 = 7 = 10 , 2 = 102.6 , OP07 amplifier

R7

Fig. 8. Low-pass filter

From Kirchoffs laws and phasor calculus one can obtain,

1
1
= (7 + ( + ) )
7 6

6 1
= ( )
7 1 + 6

Hence,
6 1
= ( )
7 1 + 6
1
As the frequency varies from 0 Hz, the gain is almost constant till = . Above this
6
1
frequency, the gain falls rapidly. Hence, = is the cutoff frequency of the low pass
6
filter. In this experiment, the cutoff frequency of the low pass filter is found to be
= 974.659 / or = 155.122

This can be verified in the observations and plots below as the observed value of cutoff
obtained from the graph is 156.104 Hz
Table. 2. Frequency vs. Gain for Low-pass filter

Frequency rmsVin rmsVout Gain Frequency rmsVin rmsVout Gain in

(Hz) (mV) (mV) in dB (Hz) (mV) (mV) dB
1 125 130 0.3407 160 589 429 -2.7532
2 237 242 0.1813 170 572 418 -2.7244
3 322 329 0.1868 180 564 410 -2.7699
4 384 394 0.2233 190 577 398 -3.2259
5 427 440 0.2605 200 582 385 -3.5892
8 493 508 0.2603 300 563 303 -5.3813
15 538 551 0.2074 341 573 254 -7.0664
30 575 551 -0.3703 400 570 241 -7.4772
60 587 552 -0.5340 410 573 219 -8.3542
70 574 536 -0.5949 500 571 201 -9.0688
80 597 537 -0.9200 600 566 175 -10.1956
90 584 519 -1.0249 700 571 152 -11.4959
100 591 511 -1.2633 710 578 136 -12.5678
110 594 502 -1.4617 1000 570 110 -14.2896
120 573 476 -1.6110 1410 575 73.3 -17.8913
130 594 465 -2.1267 2710 518 43.6 -21.4969
140 571 452 -2.0300 10000 561 12.4 -33.1108
150 586 442 -2.4495

Gain in dB vs. Frequency (Hz) of Low-pass filter

5

0
-3dB
-5

-10
Gain in dB

-15

-20

-25

-30
156.104 Hz
-35

1 10 100 1000 10000

Frequency f (Hz)

So, the observed cutoff frequency is = 156.104

Phase sensitive detector (AD630)
The outputs from the pre-amplifier and the phase shifter are connected to the signal and
reference inputs respectively of the PSD. The output of the PSD then goes into the input
of the low pass filter.

In this experiment, the lock-in mechanism happens through synchronously demodulating

the signal with respect to a reference. This is carried out by using AD630, a high precision
balanced demodulator. It can be thought of as a precision op amp with two independent
differential input stages and a precision comparator that is used to select either of them.
The rapid response time of this comparator coupled with the high slew rate and fast
settling of the linear amplifiers minimize switching distortion.

Fig. 9. Function block diagram of AD630

In a chip there are two-unit gain amplifiers A & B. The comparator is used to switch the
required amplifier through selection pins SEL A and B. Phase shifted reference is fed
through one of these pins while the other is grounded. The internal compensation
capacitor can be controlled by using COMP pin. In this experiment, this pin is connected
to the output pin. The pins are , , are used to give feedback and one of them is
connected to one of the amplifiers non-inverting inputs for feedback. The other non-
inverting input is grounded. Either of the remaining feedback pins are connected
simultaneously to the inverting inputs of both the amplifiers. The remaining feedback
pin is grounded. The differential and common mode offset can be adjusted by connecting
impedances across suitable pins.

The complete circuit diagram of the Lock-in amplifier built in this experiment is given
below.
 Fig. 10. Connections across the pins of AD630 PSD.

Fig. 11. Complete circuit diagram of Lock-in amplifier circuit

Debugging
The output was initially uneven. The outputs of both the amplifiers in the AD630 chip
were of different gain. The differential offset is then adjusted by connecting the.pins 3
and four with a potentiometer. It was found that the peaks are becoming levelled i.e. the
gains becoming equal when the resistance is reduced. So the potentiometer is removed
and the pins are shorted inorder to supply least resistance path. The output obtained is
shown below.

Fig. 12. Output of AD630 before offset adjustment. The sine wave is of the signal.

Fig. 13. After adjusting the differential offset the peak heights became equal

(notice that the scales of signal and output waves are changed for better comparison)
 Fig. 14. Final output from the low-pass filter (yellow).

It is nearly DC but has a low frequency AC component due to the higher low-pass cutoff
frequency

Calibration of Lock-in amplifier

Before using, the lock-in amplifier should be properly calibrated. This is achieved by
measuring the output across a known resistance and voltage. For this we design a
voltage divider circuit as shown below.

V1 V2

Fig. 15. Voltage divider circuit for calibration of the lock-in

The pins V1 and V2 are fed into pre-amplifier and phase shifter respectively. The former
serves as Signal whereas the latter as reference. The voltage difference across the small
2
resistance R3 is given by = + +
1 2 3
By substituting the values, we get

44.44 106 (4)

We now calculate the signal using the above formula and plot it across the output
observed to get the amplification of the lock-in.

Table. 3. Signal voltage vs. lock-in output

Frequency Vin p-p

(kHz) (V) Vsig (V) Vout (V)
1 1.57119E-05 1.257
1.44 2.26252E-05 1.876
1.96 3.07953E-05 2.68
2.32 3.64516E-05 3.14
2.88 4.52503E-05 3.95
3.4 5.34205E-05 4.64
3.92 6.15907E-05 5.43
4.4 6.91324E-05 6.16
1.005 5 7.85596E-05 6.88
1 1.57119E-05 1.17
1.4 2.19967E-05 1.72
1.88 2.95384E-05 2.31
2.16 3.39377E-05 2.72
2.56 4.02225E-05 3.26
3.16 4.96496E-05 4.04
3.88 6.09622E-05 5.04
4.56 7.16463E-05 5.93
2 4.96 7.79311E-05 6.54
1 1.57119E-05 1.05
1.36 2.13682E-05 1.5
1.8 2.82814E-05 2.03
2.24 3.51947E-05 2.55
2.88 4.52503E-05 3.33
3.4 5.34205E-05 4.02
3.92 6.15907E-05 4.63
4.44 6.97609E-05 5.35
4.92 7.73026E-05 5.94
3 5.2 8.17019E-05 6.29
1 1.57119E-05 0.93
1.52 2.38821E-05 1.5
1.88 2.95384E-05 1.88
2.16 3.39377E-05 2.22
2.72 4.27364E-05 2.84
3.08 4.83927E-05 3.21
4 3.56 5.59344E-05 3.79
 4.12 6.47331E-05 4.38
4.56 7.16463E-05 4.94
5.2 8.17019E-05 5.67
1 1.57119E-05 0.81
1.36 2.13682E-05 1.2
1.92 3.01669E-05 1.71
2.36 3.70801E-05 2.19
2.8 4.39934E-05 2.61
3.4 5.34205E-05 3.22
3.92 6.15907E-05 3.71
4.2 6.599E-05 4.04
5.051 5 7.85596E-05 4.83

Locki-n output vs. signal voltage

1.005KHz
6 2.000KHz
3.000KHz
Output voltage of lock-in (V)

4.000KHz
5.051KHz
5

4
Equation y = a + b*x
Weight No Weighting

3 Residual Sum of
Squares
0.01304 0.00533 0.00703 0.00581 0.0029

Pearson's r 0.99978 0.99991 0.99989 0.99987 0.9999

Adj. R-Square 0.9995 0.99978 0.99975 0.9997 0.99977
Value Standard Error

2 D (1)
Intercept
Slope
-0.14178
90170.85545
0.03572
711.53616
Intercept -0.19466 0.02189
D (2)
Slope 85862.17712 445.25848
Intercept -0.22337 0.02258
D (3)
1 Slope
Intercept
79503.76171
-0.22346
419.72337
0.02122
D (4)
Slope 71750.46564 415.08178
Intercept -0.188 0.01677
D (5)
Slope 63773.37666 338.48662
0
0.00001 0.00002 0.00003 0.00004 0.00005 0.00006 0.00007 0.00008 0.00009
Signal Voltage (V)

Note, that the amplification factor or gain of the lock-in is dependent on the frequency of
the signal. The respective gains with error for each given frequency are shown below.
.

Table. 4. Least square fit data obtained from Origin Plot.

Frequency Standard
(KHz) Value Error
1.005 Intercept -0.14178 0.03572
Slope 90170.86 711.5362
2.000 Intercept -0.19466 0.02189
Slope 85862.18 445.2585
 3.000 Intercept -0.22337 0.02258
Slope 79503.76 419.7234
4.000 Intercept -0.22346 0.02122
Slope 71750.47 415.0818
5.051 Intercept -0.188 0.01677
Slope 63773.38 338.4866

Measurement of low resistance

The Lock-in amplifier built in this experiment can be used to measure extremely low
resistances with ease. This is demonstrated in the following experiment.

Fig. 16. Voltage divider for measuring unknown resistance.

We follow the same procedure as in the previous section to obtain the unknown resistance.
But, now we calculate the signal voltage by dividing the lock-in output with the gain
obtained for respective frequencies. Then the unknown resistance is obtained by back
calculating the signal voltage from the lock-in output.

Table. 5. Measurement of unknown resistance

Frequency Unknown
(kHz) Vin p-p (V) Vout (V) Vsig (V) resistance
1.005 1.04 1.27 1.41E-05 0.183861454
1.32 1.71 1.9E-05 0.195048443
1.76 2.31 2.56E-05 0.19761487
2.04 2.71 3.01E-05 0.200013556
2.72 3.57 3.96E-05 0.19761487
3.2 4.26 4.72E-05 0.200437939
3.92 5.25 5.82E-05 0.201647826
4.24 5.61 6.22E-05 0.199212834
4.88 6.43 7.13E-05 0.1983862
2 1 1.14 1.33E-05 0.180255775
1.24 1.48 1.72E-05 0.188722797
 1.84 2.23 2.6E-05 0.191633475
2.24 2.84 3.31E-05 0.200472431
2.84 3.53 4.11E-05 0.196535361
3.48 4.4 5.12E-05 0.199920702
3.92 4.93 5.74E-05 0.198858971
4.4 4.54 5.29E-05 0.163150163
4.88 6.12 7.13E-05 0.198296905
5.24 6.54 7.62E-05 0.197347122
3 1 1.03 1.3E-05 0.175887826
1.28 1.35 1.7E-05 0.180103584
1.96 2.19 2.75E-05 0.190803616
2.32 2.6 3.27E-05 0.191374434
2.72 3.09 3.89E-05 0.193993926
3.16 3.48 4.38E-05 0.188057526
3.64 4.18 5.26E-05 0.196098131
4.08 4.69 5.9E-05 0.196295904
4.72 5.48 6.89E-05 0.19826092
5 5.81 7.31E-05 0.19842879
4 1 0.9 1.41E-05 0.191597277
1.32 1.26 1.98E-05 0.203209233
1.88 1.82 2.85E-05 0.206091634
2.24 2.27 3.56E-05 0.215737013
2.72 2.77 4.34E-05 0.216799206
3.24 3.36 5.27E-05 0.220770525
3.88 4.05 6.35E-05 0.222213337
4.36 4.56 7.15E-05 0.22265127
5.04 5.28 8.28E-05 0.223023285
5 1 0.78 1.22E-05 0.166050973
1.24 1.03 1.62E-05 0.176832612
1.64 1.39 2.18E-05 0.18043375
2.04 1.82 2.85E-05 0.189927584
2.68 2.4 3.76E-05 0.190644057
3.12 2.89 4.53E-05 0.197192354
3.56 3.29 5.16E-05 0.196740025
4.04 3.74 5.86E-05 0.197077507
4.56 4.26 6.68E-05 0.198880214
5.04 4.74 7.43E-05 0.200214086

By taking the errors in measuring resistances to be 0.1 and 10 and measurement in

voltages through oscilloscope to be 0.01V and substituting the values of error in slope for
each frequency in the propagation error equation we get,

3 1 2 2 2 2 2 2

= ( ) +( ) +( ) +( ) +( )
3 1 2
 Frequency Unknown
(Hz) resistance
R3 ()
1.005 0.197093
2 0.191519
3 0.19093
4 0.213566
5 0.189399

Sources of error
1. The wires and oscilloscope probes act as antenna and pickup signal from the mains
or even worse, from the parts of the lock-in amplifier. This can be avoided by using
shielding like an earthed metal box to contain the lock-in.
2. Multiple core wire should be used for connections in the circuit as single core would
cause more noise to be picked up from the surroundings.
3. The pre-amplifier gain must be set low as at gain above 1000, it begins deviate
significantly.
4. The offset adjustment should always be taken care of to obtain reliable outputs.
5. Perform calibrations for various frequencies as the gain varies with frequency. And
perform measurements by considering respective gain for each frequency.
6. After testing transfer the circuit to a pcb as there is a chance of loose connections
in the breadboard.

Conclusion
Principle of phase sensitive detection has been learned and understood. Lock-in
amplifier has been successfully constructed and calibrated. An unknown resistance
was also found using the lock-in. A small Ac component was found in the output which
couldnt be eliminated due to lack of time. This shall be done in the next classes and a
better version will be created. More experiments will also be designed to test the
reliability of lock-in.

References
1. AD630 data sheet.
2. A Simple Low-Cost Lock-In Amplifier for the Laboratory, Sengupta
3. Design and Implementation of the Phase-locked Amplifier, Song and Liu
4. Princeton applied research paper
APPENDIX

Fig. 17. OP07 pin diagram