GETTING STARTED WITH MAGIC

A TUTORIAL

Reza Nekovei
Electrical Engineering and Computer Science Department
Texas A&M University-Kingsville

Startup commands

Start magic by:

Unix prompt> magic Ttech_file_name File_name

Where:

File_name is a new file to be created or your previously saved layout file, the file type
(.mag) should not be included.

Tech_file_name is the name of your technology file, for example SCNA.80 for 1.5
Micron technology with lambda scale set to 0.8 Micron. You need to give full path to the
file without its type (.tech27) i.e. /usr1/tutorials/1.5u-AMI/SCNA.80

For example: magic -T/usr1/tutorials/1.5u-AMI/SCNA.80 myinverter

Here is a list of useful command followed by their description:

:help command Get help information about a command

:load file_name Load a circuit into the layout editor
:save file_name Save a circuit to a file
:grid Put a grid on the layout screen
:macro Display all the macros
:undo Undo the last command (can be repeated)
:redo Redo what was undone
:drc why Check the design rule for the cause of an error
:label label_name Label a node (use Vdd! and GND! for global nodes)
:zoom size Zoom by the given size
:extract Extract the circuit for simulation
:quit Exit
Basic drawing and CMOS layers

Following figure shows typical layers used in a CMOS process, each layer can be added
or removed from the selected areas using the Paint and Erase commands:

:paint layer_name
:erase layer_name

e.g. :paint poly or :paint ndiff or :erase metal1

Commands used to create A CMOS inverter layout
:grid 2 Turn on the grid
:paint pdiff Draw the p+ diffusion area
:paint ndiff Draw the n+ diffusion area
:paint metal1 Draw the power and ground lines
:paint pdc Connect Vdd line to p+ diffusion area
:paint ndc Connect ground line to n+ diffusion area

:paint nwell Set the n-well around the PMOS

:paint nnc Connect the n-well to Vdd (PMOS bulk connection)

:paint ppc Connect the substrate to ground (NMOS bulk)
:paint metal1 Connect the drains of two transistors together (Vout)
:paint pdc Metal1 (Vout) and p+ (PMOS drain) connection
:paint ndc Metal1 (Vout) and n+ (NMOS drain) connection

:paint poly Draw the poly to create and connect transistors gates

:grid Turn off the grid

:label vin Label Vin
:label vout Label Vout
:label Vdd! Label Vdd as global node (! Means global)
:label GND! Label ground as a global node

Which is:

Where sizes are based on the unit of grid size.