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# Chapter 2

## Top level view of computer

2.1 Computer Components
Programming in hardware Vs Programming in software
Programming in hardware.
There is a small set of basic logic components that can be combined in various ways to store binary data and
to perform arithmetic and logical operations on that data. If there is a particular computation to be
performed, a configuration of logic components designed specifically for that computation could be
constructed.
We can think of the process of connecting the various components in the desired configuration as a form of
programming. The resulting program is in the form of hardware and is termed a hardwired program.
Requires rewiring the hardware for each new program.
Programming in software
Suppose we construct a general-purpose configuration of arithmetic and logic functions. This set of
hardware will perform various functions on data depending on control signals applied to the hardware.
In the original case of customized hardware, the system accepts data and produces results. With general-
purpose hardware, the system accepts data and control signals and produces results. Thus, instead of
rewiring the hardware for each new program, the programmer merely needs to supply a new set of control
signals.
Provide a unique code for each possible set of control signals, and let us add to the general-purpose
hardware a segment that can accept a code and generate control signals.
Programming is now much easier. Instead of rewiring the hardware for each new program, all we need to
do is provide a new sequence of codes. Each code is, in effect, an instruction, and part of the hardware
interprets each instruction and generates control signals.
To distinguish this new method of programming, a sequence of codes or instructions is called software.
Example
Assume you want to make a program that computes z = x2 + y2
Hardware approach
Make a dedicated circuit, by interconnecting the computational units designed specifically for this
computational problem.

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What if we want to compute z= X2/y2
Make another circuit and rewire the circuit,
This approach is not flexible.
Software Approach
Make a general- purpose arithmetic and logic unit with basic operations and compute.

## Use the above general-purpose ALU and compute automatically.

Put the sequence of operations (commands) and data in memory by coding them in some form
Make a circuit that reads the commands and generates the right control signals (s1s0), delivers data
to the ALU and put result (z) back to memory.
Let a command (instruction) has the following format

The ALU has four possible operations, so we can use 2 bits for the operation code
A memory location is accessed with a numerical address
Let the memory has 8 locations with addresses 0 to 7 (we can use 3 bits for memory address)
Let Operand 1, Operand 2 and Result be addresses of memory location (we need 3 bits for each )

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Such stored-program concept was introduced by von Neumann.
The design is referred to as the von Neumann architecture
Von Neumann Architecture
Virtually all contemporary computer designs are based on concepts developed by John von Neumann at the
The von Neumann architecture is based on three key concepts:
1. Data and instructions are stored in a single readwrite memory
2. The contents of this memory are addressable by location, without regard to the type of data
contained there
3. Execution occurs in a sequential fashion (unless explicitly modified) from one instruction to the
next

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Computer top-level components and the interactions among them

The Control Unit , the ALU and some registers constitute the Central Processing Unit (CPU)
Data and instructions need to get into the system and results out I/O components.
Temporary storage of code and results is needed Main Memory
These components communicate with each other using interconnection structure (system bus).
Some basic registers inside CPU some are used for the purpose of data exchange among this
components

## Program Counter (PC): Holds address of next instruction to fetch.

Instruction Register (IR): Temporarily holds fetched instruction while it is being read (decoded) by
CPU.
Memory Address Register (MAR): Specifies the address in memory of the word to be written from
Memory Buffer (data) register (MBR): Contains a word to be stored in memory or is used to
Input/output address register (I/O AR): specifies a particular I/O device.
Input/output buffer register (I/O BR): used for the exchange of data between an I/O module and
the CPU.

## 2.2 Computer Function execution of a program.

How do these components function together to execute programs?
Instruction cycle
The basic function performed by a computer is execution of a program.
Instruction cycle defines the steps followed to execute an instruction
consists of two major steps :

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o Fetch : Processor reads instruction from memory
o Execute: Processor performs actions specified by the instruction

Fetch Cycle

## Program Counter (PC) holds address of next instruction to fetch

Processor fetches instruction from memory location pointed to by PC
Unless told otherwise, the processor increments the PC
The fetched instruction is loaded into IR.
Execute cycle:

## Processor interprets fetched instruction and performs required actions

In general, these actions fall into four categories:
o Processor-memory: Data may be transferred from processor to memory or from memory to
processor.
o Processor-I/O: Data may be transferred to or from a peripheral device by transferring
between the processor and an I/O module.
o Data processing: The processor may perform some arithmetic or logic operation on data.
o Control instruction: An instruction may specify that the sequence of execution be altered. For
example, the processor may fetch an instruction from location 149, which specifies that the
next instruction be from location 182.
An instructions execution may involve a combination of these actions.

Let us do the example on the program execution given in your guide book, page 10.
Interrupt
Normally instruction is executed sequentially
This may be altered
o If an instruction (control instruction) specifies that the sequence be changed
o If an interrupt occurs
Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing
Interrupts are provided primarily as a way to improve processing efficiency. How?
When interrupt occurs control is transferred to the interrupt handler routine (program)

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Interrupts Cycle

Processor checks for interrupt - Indicated by an interrupt signal
If no interrupt, fetch next instruction
If interrupt pending:
Suspend execution of current program
Save context
Set PC to start address of interrupt handler routine
Process interrupt
Restore context and continue interrupted program

## Transfer of control via interupts instruction cycle with interupts

Interupt sources:

Program :
o e.g. overflow, division by zero
Timer :Generated by internal processor timer
I/O :From I/O controller
Hardware failure
o e.g. memory parity error

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2.3 Inter connection structures
A computer consists of a set of components or modules of three basic types (processor, memory, I/O) that
communicate with each other. In effect, a computer is a network of basic modules. Thus, there must be
paths for connecting the modules.

The collection of paths connecting the various modules is called the interconnection structure.
The design of this structure will depend on the exchanges that must be made among modules.
Figure shown below suggests the types of exchanges that are needed by indicating the major forms of input
and output for each module type:

## The interconnection structure must support the following types of transfers:

Memory to processor: The processor reads an instruction or a unit of data from memory.
Processor to memory: The processor writes a unit of data to memory.
I/O to processor: The processor reads data from an I/O device via an I/O module.
Processor to I/O: The processor sends data to the I/O device.
I/O to or from memory: For these two cases, an I/O module is allowed to exchange data directly with
memory, without going through the processor, using direct memory access (DMA).

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2.4 Bus Interconnection
A bus is a shared communication pathway connecting two or more devices.
It is one of the most common interconnection structures.
Multiple devices connect to the bus, and a signal transmitted by any one device is available for
reception by all other devices attached to the bus. [broadcast]
Only one device at a time can successfully transmit.
Computer systems contain a number of different buses that provide pathways between components
at various levels of the computer system hierarchy. A bus that connects major computer
components (processor, memory, I/O) is called a system bus.
Although there are many different bus designs, on any bus the lines can be classified into three
functional groups.
o Data lines
o Control lines.
Data lines

## Provide a path for moving data among system modules.

These lines, collectively, are called the data bus.
The width of the data bus (number of lines) is a key factor in determining overall system
performance.

Used to designate the source or destination of the data on the data bus.
The width of the address bus determines the maximum possible memory capacity of the system.
Control lines

Because the data and address lines are shared by all components, there must be a means of
controlling their use.
Control signals transmit both command and timing information among system modules.
Timing signals indicate the validity of data and address information.
Command signals specify operations to be performed.
Elements of Bus Design
Although a variety of different bus implementations exist, there are a few basic parameters or
design elements that serve to classify and differentiate buses.
BUS TYPES
Bus lines can be separated into two generic types:
o dedicated and
o Multiplexed.

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Dedicated Bus Type

## A dedicated bus line is permanently assigned to one function.

An example of functional dedication is the use of separate dedicated address and data lines, which is
common on many buses.
Multiplexed Bus Type

In this type of bus the same set of lines are used for multiple purposes.
For example, address and data information may be transmitted over the same set of lines using an
Uses Address valid or data valid control line to indicate the type of signal on the bus at the time.

## More complex circuitry is needed within each module.

Potential reduction in performance because certain events that share the same lines cannot take
place in parallel.
METHOD OF ARBITRATION
Because only one unit at a time can successfully transmit over the bus, some method of arbitration
is needed.
Arbitration methods can be roughly classified as:
o centralized or
o Distributed.
In a centralized scheme, a single hardware device, referred to as a bus controller or arbiter, is
responsible for allocating time on the bus. The device may be a separate module or part of the
processor.
In a distributed scheme, there is no central controller. Rather, each module contains access
control logic and the modules act together to share the bus.
BUS WIDTH
Number of lines on the bus (defines number of bits transferred at one time). E.g. 32, 64, 128
The width of the data bus has an impact on system performance:
o The wider the data bus, the greater the number of bits transferred at one time.
The width of the address bus has an impact on system capacity:
o The wider the address bus, the greater the range of locations that can be referenced.
Bus Bandwidth: Number of bits per second that can be transmitted over the bus.

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Buses Examples:

## PCI(Peripheral Component Interconnect) bus

o 32 or 64 bits bus width
o Bandwidth of up to 528 MB/sec
AGP(Accelerated Graphics Port) bus
o 32 bits bus width
o AGP 1.0 : 264MB/sec
o AGP 3.0 : 2.1GB/sec
o Dedicated to driving graphics card
USB(Universal Serial Bus)
o 1.5/12/480/5,000 Mbit/s
o Used to connect computer peripherals (mouse, keyboard)
o Serial
Interconnection Example:
Modern PCs use different types of busses because of the different speed requirements of components.

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