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[ECEg-3143 Computer Architecture & Organization - Syllabus]

Course Title Computer Architecture and Organization


Course Code ECEg-3143
Degree program B.Sc. in Electrical Engineering
Course Instructors Mr. Tesfaye Z. , Mr.Tibebu E.
Office Block 143 , office no 101
ECTS 5
Target Group III year(R)
Year/Semester III/I
Prerequisites ECEg-3141Digital Logic Design
Course Objective This course is intended for Electrical and Computer Engineering
students to:
Familiarize them with the fundamentals of Computer
Architecture & Organization.
Understanding the architecture and organizations of
computers.
Discuss issues related to computer storage and performance.
Build up confidence in the design of simple processor and
simulations.
Introduce the operations of individual components of
computer and the way in which components are connected.
Course learning outcomes By the end of this course the students are expected to:
Understand the fundamental concepts of Computer
Architecture and organization
Know how to improve speeds of computers by using different
techniques.
Understand organizations of computers
Understand how to interconnect peripheral device with
processors.
Comparisons of different computer architectures.
Assessment Continuous assessment 60 %
Summative assessment 40%
Final Exam 40%

1 DTU Faculty of Technology Department of Electrical & Computer Engineering


[ECEg-3143 Computer Architecture & Organization - Syllabus]

Unit objectives: At the end of this unit, Content Delive Domain & Delivery
students will be able to: ry Hierarchy week
Metho
d
CHAPTER ONE: Fundamental Concepts of Computer Architecture & Organization
Unit Description: This chapter provides an overview of computer organization & architecture and looks at how
computer design has evolved.
1.1. Introduction 1.1. Introduction Bs 1.1 KL1 (Wee
1.1.1. Identify the distinction between 1.1.1. Organization and GD 1.2 KL1 ks 1 )
computer organization and architecture IL
computer architecture. 1.1.2. Structure and function
1.1.2. Define the main functions & 1.2. Computer Evolution and
main structural components of a performance
computer. 1.2.1. A brief history of
1.2. Appreciate Computer evolution and computers
assess computer performance. 1.2.2. Measuring
performance
1.2.3. Performance
Improvement
Techniques
CHAPTER TWO: A Top Level View of Computer Function and Interconnection
Unit description: This Chapter provides a brief examination of the computers components and their input-output
requirements. And it looks at key issues that affect interconnection design, especially the need to support
interrupts.
2.1 Understand Computer Components 2.1. Computer Components Bs 2.1 KL1 (Wee
2.2 Explain Computer Function 2.2. Computer Function IL 2.2 KL1 ks 2 &
2.3 Describe Interconnection Structures 2.3. Interconnection GL 2.3 KL1 3)
2.4 Understand Bus Interconnection Structures GD 2.4 KL1
2.4. Bus Interconnection

CHAPTER THREE: COMPUTER ARTHIMETICS AND NUMBERING SYSTEMS


Unit Description: This chapter examines the functionality of the Arithmetic and Logic unit (ALU) and focuses on the
representation of numbers and techniques for implementing arithmetic operations.
3.1 Understand the functionality of the 3.1 Arithmetic & Logic unit Bs, 3.1 KL1 (Weeks 4
arithmetic and logic unit (ALU) (ALU) IL, 3.2 KL1 &5)
3.2 Understand how computer represent 3.2 Integer Representation GD
Integer numbers 3.3 Integer Arithmetic
Case
3.3 Understand integer arithmetic 3.4 Floating point
3.4 Understand how computer represent Representation study
Floating point numbers 3.5 Floating point Arithmetic
3.5 Understand Floating point arithmetic

2 DTU Faculty of Technology Department of Electrical & Computer Engineering


[ECEg-3143 Computer Architecture & Organization - Syllabus]

Unit objectives: At the end of this unit, Content Delive Domain & Delivery
students will be able to: ry Hierarchy week
Meth
od
CHAPTER FOUR: INSTRUCTION SETS
Unit description: From a programmer point of view, the best way to understand the operation of a processor is to
learn the machine instruction set that it executes. So in this chapter we will study this instruction sets. Architectural
issues such as instruction set design and data types are covered.
4.1 Understand characteristics and functions 4.1 Characteristics and Bs, 4.1 KL1 (Weeks 6
of instruction sets Functions IL, 4.2 KL1 & 7)
4.2 Explain the different addressing modes 4.2 Addressing modes GD
and formats. and formats

CHAPTER FIVE: Processor organization & Instruction Cycle


Unit Description: This chapter is devoted to a discussion of the internal structure and function of the processor.
The chapter describes the use of registers as the CPUs internal memory and then pulls together all of the material
covered so far to provide an overview of CPU structure and function. The overall organization (ALU, register file,
control unit) is reviewed. Then the organization of the register file is discussed. The instruction cycle is examined to
show the function and interrelationship of fetch, indirect, execute, and interrupt cycles. Finally, the use of
pipelining to improve performance is explored in depth.
5.1 Processor Organization 5.1 Processor Bs, 5.1 KL1 (Weeks 8
5.2 Register Organizations organization IL, 5.2 KL1 & 9)
5.3 Instruction cycle and pipeline 5.2 Register GD 5.3 KL1
5.4 RISC Organizations 5.4 KL1
5.3 Instruction cycle
and Pipeline
5.4 RISC

CHAPTER SIX: COMPUTER MEMORY


Chapter description: Memory is one of the top level components of a computer system. The typical computer
system is equipped with a hierarchy of memory subsystems. This chapter deals with this memory hierarchy and
design issues related to internal and external memory.

6.1 Computer Memory system Overview 6.1 Computer Memory Bs 3.1 KL1 (Weeks
6.2 Cache Memory System Overview IL 3.2 KL2 9-10)
6.2 Cache Memory 3.3 KL2
3.4 KL3

3 DTU Faculty of Technology Department of Electrical & Computer Engineering


[ECEg-3143 Computer Architecture & Organization - Syllabus]

Unit objectives: At the end of this unit, Content Delive Domain & Delivery
students will be able to: ry Hierarchy week
Metho
d

CHAPTER SEVEN: Input Output (I/O)


Unit description: In addition to the processor and a set of memory modules the third key element of a computer
system is a set of I/O modules. Each module interfaces to the system bus & controls one or more peripheral
devices. This chapter discuss the mechanisms by which an I/O module interacts with rest of the computer system,
using the techniques of programmed I/O, Interrupt I/O and direct memory access (DMA).

7.1 External devices 7.1. External Devices Bs 7.1 KL1 (Weeks


7.2 I/O modules 7.2. I/O modules IL 7.2 KL2 11 & 12)
7.3 Understand the different I/O 7.3. I/O Techniques Case 7.3 KL2
techniques 7.3.1 Programmed I/O study
7.3.2 Interrupt driven I/O
7.3.3 Direct Memory
access(DMA)

Text: Computer Organization and Architecture Designing for Performance: William Stallings 8th
Edition
References:
1. D.A. Patterson & J.L. Hennessy - Computer Architecture

Approved by:

Mr. Tesfaye Zewdu ________________________

Name (Course Instructor) Signature

Mr. Tibebu Enyew ________________________

Name (Course Instructor) Signature

____________ ________________________

Name (Module Coordinator) Signature

4 DTU Faculty of Technology Department of Electrical & Computer Engineering