Debre Tabor University

Faculty of Technology
Department of Electrical & Computer Engineering
Computer Architecture & Organization Final Sup exam

Program: Regular 3rd Year Total time allowed: 2.5 hrs

Exam Date: 10/2/10 e.c. Max Mark: 40%
Instructors: Mr. Tesfaye Z., Mr. Tibebu E. Course Code: ECEg 3143
Name ________________________________Id no. ______________________________Sec_____
General Instructions
Write your name and ID number on the space provided.
There are 10 pages in this test, including this cover page. Please check that you
have them all.
Please write neatly. Illegible answers will be assumed to be incorrect.
Any kind of cheating leads you a penalty.

For Instructors use only

P-IV P-V Total
Part P-I (13%) P-II (4%) P-III (13%)
(5%) (5%) (40%)

Marks
Obtained

Good Luck!

Oct 20, 2017 1

 Part I: Conceptual Explanation (13%)
1. Compare and contrast direct and indirect Addressing modes?

2. What are the advantages and disadvantages of using a fixed-length

instruction format?

Oct 20, 2017 2

3. Explain what the processor is required to do and the main components
of processor?

4. What is instruction pipelining? Explain pipeline hazard?

Oct 20, 2017 3

5. Mention and explain in detail the common types of registers?

Oct 20, 2017 4

 Part II: Short answer (4%)
1. Assume an instruction set that uses a fixed 16-bit instruction
length.Operand specifiers are 6 bits in length. There are K two-operand
instructions and L zero-operand instructions.What is the maximum
number of one-operand instructions that can be supported?

2. If the last operation performed on a computer with an 8-bit word was

an addition in which the two operands were 00000010 and 11111110,
what would be the value of the following flags?
a. Carry flag __________________________________
b. Zero flag __________________________________
c. Overflow flag ___________________________________
d. Sign flag ___________________________________

3. Assume a CPU has 31 different operations. Only register addressing

mode is used, and CPU has 8 user visible registers. The maximum
number of operands allowed in the instruction is three. What should be
the length of the instruction, if fixed-length instruction format is
required?

Oct 20, 2017 5

 Part III: Pipeline Hazard (13%)
1. A computer has a ve-stage instruction pipeline of one cycle each. The
ve stages are: Instruction Fetch (IF), Instruction Decode (ID), Operand
Fetch (OF), Instruction Execution (IE), and Operand Store (OS).
Consider the following code sequence, which is to be run on a computer
with 1kHz clock rate.

MOV R1, 2
MOV R4, [100]
ADD R1, R2
ADD R3, R1

a. Calculate the time needed to execute the above code without

pipelining?

b. Calculate (using the Gantts chart below) the number of cycles

needed to execute the above code if the pipeline described above
is used. Assume the approach used to handle pipeline hazard is
Detect and Stall.
Clock cycle

Instructions 1 2 3 4 5 6 7 8 9 10 11 12 13

MOV R1, 2

MOV R4,[100]

ADD R1, R2

ADD R3, R1

Oct 20, 2017 6

c. Calculate the speedup factor.

d. Explain in detail the types of pipeline hazards that occur in the

above program? Explain how and when (at which clock cycle
number) the hazards occurred?

Oct 20, 2017 7

2. What kind of Data hazards are between the following instructions
(Circle one of four):
a. ADD R1, R2
ADD R3, R1

i) RAW ii) WAR iii) WAW iv) None

b. ADD R1, R2
ADD R2, R3

i) RAW ii) WAR iii) WAW iv) None

c. ADD R1, R2
ADD R4, R3

i) RAW ii) WAR iii) WAW iv) None

Oct 20, 2017 8

 Part IV: Assembly Program output (5%)
Instruction:
1. Consider the assembly program given below and answer the following
questions.
a. Determine the values of the registers and the memory after the
execution of the program.
b. Describe shortly what the program will do, or what is the application
of the program?

Memory
MOV R1 , 5 99 23

Loop: MOV R2 , [R1+100] 100 105

SUB R2, AC 101 91

JS skipupdating 102 5

MOV AC , [R1+100] 103 90

Skipupdating: DEC R1 104 20
JNZ Loop 105 50
MOV [106], AC 106 0

CPU registers
AC 0

R1 0

R2 0

JS = Jump sign, jump if the previous operation result is negative.

JNZ = Jump not zero, jump if the previous operation result is not zero.

Oct 20, 2017 9

 Part V: Writing an Assembly Program (5%)
Instruction:
1. Write an assembly program that calculates the average value of the
numbers located in memory location 11, 12,13,14 & 15, and store the
result in memory location 16.
Your program must use branch instruction and assume the processor
has only four user-visible registers (R1, R2, R3 and AC).
You can assume any machine instructions. But you must describe the
machine instructions you use in your program.

Oct 20, 2017 10