Memory

[KB = 1024 Bytes = 210 Bytes, MB = 1024 KB = 220 Bytes]

1. Virtual address space = ?
64KB
Physical address space = ?
32KB
Page size = ?
4KB
# of pages = ?
16
Frame size = ?
4KB
# of frames = ?
8

Converting logical addresses to physical address

What is the physical address for logical address of 36876?
1. First determine the page/frame size.
Here 4KB = 4 * 1024 = 4096B
2. Then divide the virtual address to the page size to find out the page number and the offset.
Let's say virtual address is 36876.
36876 / 4096 = 9.xx > 9 page number is 9 (starting from zero)
36876 - (9*4096) = 36876 - 36864 = 12 offset = 12
3. Look at the page table to find the frame number of the respective page.
Here page number is 9. The virtual address is between 36K and 40K. Page table says that the respective frame number is 5.
4. Convert frame number to physical address by multiplying the frame number with frame size.
5 * 4096 = 20480
5. Add the offset from step 2.
Physical address = 20480 + 12 = 20492

Find the physical addresses of virtual addresses: 0, 8192, 20, 4100, 22300
0: 8192 8192: 24576
20: 8212 4100: 4100
8300: 24684

2. Consider a swapping system in which memory consists of the following hole sizes in memory order: 10 MB, 4 MB, 20 MB, 18
MB, 7 MB, 9 MB, 12 MB, and 15 MB. Which hole is taken for successive segment requests of (note: for simplicity, assume that
these holes are fixed, but variable sized)
(a) 12 MB
(b) 10 MB
(c) 9 MB
for first fit? Now repeat the question for best fit, worst fit, and next fit.

First Fit Best Fit Worst Fit Next Fit

12 MB

10 MB

9 MB

Solution: First fit takes 20 MB, 10 MB, 18 MB. Best fit takes 12 MB, 10 MB, and 9 MB. Worst fit takes 20 MB, 18 MB, and 15
MB. Next fit takes 20 MB, 18 MB, and 9 MB.
3. Assume page size = 2KB, a process of 101.5 KB. How many pages do we need?
[101.5 2] = 51 pages
2 (101.5 mod 2) = 0.5KB
We need 51 pages with 0.5 KB free space on the last page.



4. Assume frame size = 4KB, page table with 4-byte entries. What is the maximum size of physical memory?

4KB = 212 bytes per frame

A page table with 4-byte (32 bits) entries can hold 232 entries, i.e., the table can support up to 232 frames.
Therefore, the physical memory is 212 * 232 = 244 = 16 TB.

Effective Access Time

The performance of demand paging is commonly evaluated by the effective access time for a demand-paged memory
Let:
ma = memory access time
p = probability of a page fault (0 <= p <= 1)
Then:
Effective access time = (1-p) * ma + p * page fault time

5. Consider a paging system with the page table stored in memory. A memory reference takes 200 nanoseconds to access a
page in memory, and a page fault takes 400 nanoseconds. If 75% of all page-table references are found in the physical
memory, what is the effective address translation time?

Effective access time = 0.75 200 + 0.25 400 = 250 nanoseconds.

6. A machine has a 32-bit address space and an 8-KB page. The page table is entirely in hardware, with one 32-bit word per
entry. When a process starts, the page table is copied to the hardware from memory, at one word every 100 nsec. If each


process runs for 100 msec (including the time to load the page table), what fraction of the CPU time is devoted to loading the
page tables?

The page table contains 2^32 / 2^13 = 2^19 entries, which is 524,288. Loading the page table takes 52 msec. If a process
gets 100 msec, this consists of 52 msec for loading the page table and 48 msec for running. Thus 52% of the time is spent
loading page tables.

7. You are given the following data about a virtual memory system:
a) The TLB can hold 1024 entries and can be accessed in 1 nsec.
b) A page table entry can be found in 100 nsec.
c) The average time process page fault is 6 msec.
If page references are handled by the TLB 99% of the time, and only 0.01% lead to a page fault, what is the effective address-
translation time?

The chance of a hit is 0.99 for the TLB, 0.0099 for the page table, and 0.0001 for a page fault (i.e., only 1 in 10,000
references will cause a page fault). The effective address translation time in nsec is then:
0. 99 1 + 0. 0099 100 + 0. 0001 6 10^6 602 nsec.

Frame Allocation
For a single-process system, the OS takes some frames and leaves the rest to the running process.
For a multiprogramming system: (m frames and n processes)
Equal allocation: each process has an equal share of the memory, i.e.,
m/n frames per process
Proportional allocation: each process Pi is allocated with
ai = si/S * m

frames, where si = # of pages of process Pi and S = si

8. Consider a system with a 1-KB frame size. Process A needs 25KB and Process B needs 169KB of memory. There are 72 free
frames. How many frames will be allocated to each process if the following algorithm is used?
a) Equal allocation
36 frames per process

b) Proportional allocation
Process A: 9.27 ~ 9 frames
Process B: 62.73 ~ 63 frames

Page Replacement Algorithms

9. Reference string: 7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2, 1, 2, 0, 1, 7, 0, 1
Three frames in memory. How many page faults?

FIFO Page Replacement

7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1

Optimal Page Replacement
7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1

LRU Page Replacement
7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1

Page Table

10. A process with 32-bit logical address space and page size of 4KB. If such as process is running on a computer with 128MB
physical memory, what is the size of the page table? (Assume that each entry of the page table consists of a frame # and a
present bit.)

Since the page size is 4KB (2^12 B), we need the last 12-bit for the page offset.
The actual page table has 2^32 / 2^12 = 2^20 entries.
Frame size is 4KB and memory size is 128MB, so we have 2^27 / 2^12 = 2^15 frames. Therefore, each table entry (frame # +
present bit) consists of 16 bits or 2B.
So the actual page table size will is 2^20 * 2 = 2^21 bytes = 2MB.

11. For the same settings as question 10, in the two-level page table scheme, why the logical address is split into 9-bit page
number in the outer page table, 11-bit page number, and 12-bit page offset?

If we want to divide the entire page table into pages of size 4KB, we will have 2^21 / 2^12 = 2^9 pages, and each page has
2^12 / 2^1 = 2^11 entries.
Therefore, we will have 9 bits for the outer page table, 11 bits for individual pages of a page table, and 12 bits for page
offset.