Unit 1- 8086 Processors

Historical Background.

Microprocessor based PC systems.

8086 CPU Architecture.

Machine Language Instructions.

Instruction execution timing.

 Historical background
Historical age:
1) Abacus.
2) Babbage analytical model.
Electronic age:
1) Von Neumann machine
Microprocessor age:
1) Motorola
2) ARM
3) Intel
 Von Neumann machine

Memory Unit

Input Unit Control Unit Output Unit

ALU
 Microprocessor based PC system

Memory Input /
Microprocessor
output

Bus
Advantages:

Processing speed.
Increasing memory.
Expandable memory.
Versatility.
Decreasing cost.
Decreasing size.
 Features of 8086
Refer Software demo
 Register Organisation
General Purpose Registers

Segment Registers

Flag Registers

Pointer and Index register

 General Purpose Registers

ax ah al
bx bh bl
cx ch cl
dx dh dl
 Segment Registers

CS: Code Segment

DS: Data Segment
ES: Extra Segment
SS: Stack Segment
 Flag Registers
Refer software demo
Pointers and Index Registers
SP: Stack Pointer
BP: Base Pointer
SI: Source Index
DI: Destination Index
IP: Instruction Pointer
 One byte instruction

Opcode

Example:

1) End
One byte instruction register mode

Opcode Register

Example:

1) Mov ax,bx
Register to/from memory with no
displacement

Opcode Mod Register R/M

Example:

1) Mov al,[10008 H]
 Register to/from memory with
displacement 8 bit

Opcode Mod Register R/M Disp

Example:

1) Mov bx, [sI + 03H]

 Register to/from memory with
displacement 16 bit

Opcode Mod Register R/M

Low Disp High Disp

Example:

1) Mov ax,[SI + 1000 H]

Immediate operand to register 8 bit

Opcode 11 opcode R/M operand

Example:

1) Mov al,10 h
Immediate operand to register 16 bit

Opcode 11 opcode R/M

Low High
operand operand
Example:

1) Mov ax,1000 h
Immediate operand to memory with
16 bit displacement

Opcode Mod Opcode R/M

Low High
Low Disp High Disp
operand operand

Example:

1) Mov [Si + 8004 H] , 6000 h

 Mode
Mode Displacement

00 No displacement

01 Low order displacement

10 Both low order and high oder displacement

11 Register field
 Register field assignment
Reg Segment Reg
000 Ax 000 Al 00 ES
001 Cx 001 Cl 01 CS
010 Dx 010 Dl 10 SS
011 Bx 011 Bl 11 DS
100 Sp 100 Ah
101 Bp 101 Ch
110 Si 110 Dh
111 Di 111 Bh
 R/M field
R/M Operand address

000 EA=[BX]+[SI]+Displacement (optional)

001 EA=[BX]+[DI]+Displacement (optional)

010 EA=[BP]+[SI]+Displacement (optional)

011 EA=[BP]+[DI]+Displacement (optional)

100 EA=[SI]+Displacement (optional)

101 EA=[DI]+Displacement (optional)

110 EA=[BP]+Displacement (optional)

111 EA=[BX]+Displacement (optional)

 PUSH Bx

0 1 0 1 0 0 1 1

Opcd Opcd Opcd Opcd Opcd Reg Reg Reg

= Bx = Bx = Bx
 Mov Ax, Cx
1 0 0 0 1 0 1 1

Opcd Opcd Opcd Opcd Opcd Opcd To Mov

Reg word

1 1 0 0 0 0 0 1
Reg Reg
to to Reg Reg Reg Reg Reg Reg
Reg Reg = Ax = Ax = Ax = Cx = Cx = Cx
 Mov [Bx], dl
1 0 0 0 1 0 1 0

Opcd Opcd Opcd Opcd Opcd Opcd To Mov

Reg byte

0 0 0 1 0 0 1 1
mem mem
Reg Reg Reg Reg Reg Reg
= Dl = Dl = Dl = Bx = Bx = Bx
 Mov 56 H [SI], Bh
1 0 0 0 1 0 0 0

Opcd Opcd Opcd Opcd Opcd Opcd From Mov

Reg byte

0 1 1 1 1 1 1 0
Mem, Mem,
1 byte 1 byte Reg = Reg = Reg = Reg = Reg = Reg =
disp disp Bh Bh Bh SI SI SI

0 1 0 1 0 1 1 0

Disp Disp Disp Disp Disp Disp Disp Disp

 Mov Bx, [1234 H]
1 0 0 0 1 0 1 1

Opcd Opcd Opcd Opcd Opcd Opcd To Reg Mov

word

0 0 0 1 1 1 1 0

Direct Direct Reg = Bx Reg = Bx Reg = Bx Direct Direct Direct

0 0 1 1 0 1 0 0

Memory Memory Memory Memory Memory Memory Memory Memory

0 0 0 1 0 0 1 0

Memory Memory Memory Memory Memory Memory Memory Memory

 Mov CS : [Bx], Cl
0 0 1 0 1 1 1 0

CS Reg CS Reg

1 0 0 0 1 0 0 0

Opcd Opcd Opcd Opcd Opcd Opcd From Mov

Reg byte

0 0 0 0 1 1 1 1

mem mem Reg = Reg = Reg = [Bx] [Bx] [Bx]

Cl Cl Cl
 Mov al, bl
opco Opo opco opco opco opco to Movi
de de de de de de reg 1 ng
byte
0

reg 1 Al Al Al bl bl bl
to
reg 1
 Mov Ax, DS : [Bp+SI]
DS 1 DS

OPCODE Opcode Opcode opcode opcode opcode to reg 1 Move

word 1

0 0 ax ax ax 0 1 0

bp bp bp si si si