This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2017.2762622, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
Current-Ripple Compensation Control
Technique for Switching Power Converters
Weiguo Lu, Member, IEEE, Shaoling Li, and Weiming Chen
AbstractAs for ripple-current mode control, it cannot
achieve average current tracking, resulting in poor current
accuracy and even current waveform distortion. Meanwhile,
fast-scale instability may occur in some operating
condition. To solve these problems effectively, a
current-ripple compensation (CRC) control technique is
proposed in this paper. The error between the average of
the controlled current and the reference current is
compensated by certain compensation signal, achieving
average current tracking while suppressing fast-scale
instability. On this basis, the compensator in the
outer-voltage loop is further simplified to a proportional
part by introducing a rebuilt average reference current. The
idea and design procedure of the proposed CRC control
technique are discussed in detail. Accordingly, two
available implementation schemes for the proposed CRC
are presented, including slope compensated and parabolic
compensated schemes. Finally, two application cases
respectively to DC-DC Buck converter and Boost PFC
converter are presented to verify the proposed CRC control
technique.
Index TermsAverage current tracking, current-ripple
compensation (CRC) control technique, fast-scale
instability, ripple-current mode control
I. INTRODUCTION
I N AC-DC converters, such as PFC converter and PWM
rectifier, it is needed to precisely control the current
waveform and the output voltage simultaneously. To this end,
double-loop control scheme is always adopted [1][4], in which
the outer-voltage loop provides the reference current signal and
the inner-current loop realizes accurate current tracking. In
addition, since the introduction of the inner-current loop
enhances the dynamic performance of the system, double-loop
control scheme is often applied to DC-DC converter as well
[5][6].
Generally, the realization forms of the inner-current loop can
be broadly divided into two categories. One is average-current
mode control, in which the output modulation signal of the PI
Manuscript received April 25, 2017; revised July 27, 2017 and August
26, 2017; accepted September 26, 2017. This work was supported by
the National Natural Science Foundation of China under Grant
51377185.
The authors are with the State Key Laboratory of Power
Transmission Equipment & System Security and New Technology,
Chongqing University, Chongqing 400044, China (e-mail:
luweiguo@cqu.edu.cn; lishaoling@cqu.edu.cn; chenwm92@
gmail.com).
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compensator is compared with a carrier signal to generate the
PWM control signal. The average of the controlled current is
able to track the reference current accurately [7][9]. The other
category is ripple-current mode control, including peak-current
mode control [10][14], valley-current mode control [15][17],
V2 control [18][19] and so on. In these methods, the ripple
component of the current signal is introduced into the control
loop. The instantaneous current value at switching instant, i.e.,
the peak value or valley value, is controlled to track the
reference current provided by the outer-voltage loop. Under
this circumstance, there is a steady-state error of a current ripple
amplitude between the average of the controlled current and the
reference current, i.e., non-average current tracking [20]. Since
no PI compensator exists in the inner-current loop, the dynamic
performance is better, not limited by its bandwidth. Therefore,
ripple-current mode control gets much attention in the fields of
microelectronics, computer, communication power supplies,
etc., where it is very necessary for the power supplies to have a
good dynamic performance [21][22].
Remarkably, in practical applications of ripple-current mode
control, there is still a problem of fast-scale instability, i.e.,
subharmonic oscillation [23][27]. Conventional solution is to
apply slope compensation (SC) to the reference current signal
[28][29]. However, the peak value of the current is reduced, or
the valley value is increased, to maintain the system fast-scale
stability. The steady-state error between the average of the
controlled current and the reference current is further increased,
resulting in worse current accuracy and smaller working range
of the reference current [20]. In most of existing compensation
schemes of ripple-current mode control, such as variable slope
compensation [30][31] and dynamic slope compensation [12],
[32], the main attention is on suppressing fast-scale instability.
The current ripple compensation scheme in [33] improves the
current tracking accuracy. The hybrid compensation scheme
proposed in reference [20] achieves average current tracking
while suppressing fast-scale instability. However, only the
steady-state current accuracy is improved.
In this paper, we propose a current-ripple compensation
(CRC) control technique, in which current-ripple compensation
is applied to the inner-current loop, to achieve average current
tracking while suppressing fast-scale instability. On this basis
of inner-current design, the outer-voltage loop is simplified to a
proportional part via rebuilding the average of the reference
current. In this way zero steady-state error can still be kept in
the output voltage. And without the bandwidth limitation of the
integral part of the PI compensator, the dynamic performance
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of the system could be further improved. Furthermore, with the since the charging and discharging of the capacitor in integral
proposed CRC scheme current tracking accuracy can also be circuit must take some time, the dynamic response of the
improved in the application to AC-DC converter, where integral part is slow.
accurate current tracking is always needed. To improve the dynamic performance of the system, the
The proposed CRC control technique will be elaborated in integral part of the PI compensator in the outer-voltage loop is
detail in this paper, and the main contents are as follows. In intended to be removed, leaving only the proportional part. In
Section II, the idea, design and two feasible implementation the proposed control, as shown in Fig. 1(b), according to the
schemes of the proposed CRC control technique are presented. power balance relationship between the input and the output of
In Section III, the proposed CRC is verified by two specific the system, the average reference current iref-av is rebuilt to
application cases, including a Buck converter experimental replace iref2.
platform and a Boost PFC converter experimental platform.
Section IV is the conclusion. I iref =iref
I iref =iref mc mod ( t /Ts ,1)
ierr=i ierr=i+mcD
iref iref
II. DESIGN, ANALYSIS AND IMPLEMENTATION OF THE iav
PROPOSED CRC CONTROL TECHNIQUE i
i iav
m2 m1 i
i m2 m1
A. Idea of the Proposed Control
0 0
The block diagram of traditional ripple-current mode control Tn Tdn Tn+1 Tdn+1 t Tn Tdn Tn+1 Tdn+1 t
is exhibited with solid line in Fig. 1(a), where peak-current (a) (b)
mode control is taken as an example, and i represents the sensed ( d nTs ) iref =iref + iref
iref
I
current. It should be noted that the reference current iref is A C
assumed to be a DC variable here. In AC-DC converter iref
varies with line frequency, which is generally much lower than iref
(iav ) m2 i
switching frequency. Therefore, iref can be regarded as a i B m1
constant in a switching cycle and the analysis here also applies
0
to AC-DC converter. Tn Tdn Tn+1 Tdn+1 t
PI compensator iref (c)
vo p k CLK Fig. 2. Current waveforms. (a) The case without compensation. (b) The
+ + S PWM
+ iref1 + iref Q case with traditional slope compensation (SC). (c) The case with the
Vref R proposed current-ripple compensation (CRC).
iref2 iref +
+ i

+
Comparator RS flip-flop For the case without compensation in the reference current,
iref-av i.e., iref=0, the steady-state error ierr=i between the average
(a) current iav and the reference current iref, as shown in Fig. 2(a),
iref will cause steady-state error in the output voltage. Here, i is
vo p CLK
+ S PWM the ripple amplitude of i, Tn=nTs, Tn+1=(n+1)Ts, Tdn=Tn+dnTs,
+ + iref Q
Vref k Tdn+1=Tn+1+dn+1Ts, Ts is the switching cycle, dn and dn+1 are the
R
+ + duty cycles of the nth and n+1th switching cycle respectively.
i
iref-av Comparator RS flip-flop The two inputs of the comparator at the steady-state switching
(b) instant TDn are respectively
Fig. 1. Block diagram of ripple-current mode control (Taking i (TDn ) =iav + i (1a)
peak-current mode control as an example here). (a) Traditional control
scheme with PI compensator. (b) Proposed CRC control scheme. TDn ) k (Vref p1vo (TDn ) ) + iref (TDn ) +iref-av .
iref (= (1b)
Here, TDn=Tn+DTs, and D is the steady-state duty cycle. By
The PI compensator in the outer-voltage loop can be split combining (1a) and (1b), the steady-state error in the output
into a proportional part and an integral part in parallel. The voltage can be got as Vo=Vref/pVoi/(kp). Here, Vo is the
input is the error between the reference voltage Vref and the steady-state output voltage, k is the proportional coefficient in
sampled output voltage pvo. The outputs are defined as iref1 and the outer-voltage loop, and the rebuilt iref-av according to power
iref2 respectively, and iref1+iref2=iref. In steady state, the output of balance is approximately equal to iav.
the integral part is basically a DC variable, which can be For the case with traditional slope compensation (SC), which
regarded as the average of iref, defined as iref-av. That is, is often adopted to suppress subharmonic oscillation that may
iref2iref-av. Actually, a tiny high-frequency component exists in occur, the steady-state error between iav and iref further
iref2, which can be ignored. increases to ierr=i+mcD. Here, mc is the intensity of SC. The
In the inner-current loop, only a comparator and a RS steady-state error in the output voltage increases to
flip-flop exist. The controlled current i is able to immediately Vo(i+mcD)/(kp).
respond to the change of the reference current during the In our control, we attempt to design a current-ripple
dynamic process of the system. In the outer-voltage loop, the compensation (CRC) scheme which is able to achieve average
current tracking while suppressing subharmonic oscillation, as
dynamic response of the proportional part is pretty fast. While,
shown in Fig. 2(c). Under this circumstance, the steady-state

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2017.2762622, IEEE
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output voltage can be got as Vovo(TDn)=Vref/p according to (1). C. Implementation Schemes of CRC Compensation
Therefore, zero steady-state error can be achieved in the output Signal
voltage with the proposed CRC. To realize average current tracking and effective suppression
B. Design of CRC Compensation Signal of fast-scale instability simultaneously, two constraints of the
To realize average current tracking, CRC compensation proposed CRC compensation signal have been derived above.
signal is needed to satisfy iref(Tdn)=i. The original error Furthermore, the waveform of the proposed CRC
ierr=i is compensated, so we have iav=iref. compensation signal during the whole switching cycle can be
To suppress fast-scale instability that may occur, the tangent freely designed, and a variety of implementation schemes can
slope of the compensation signal at the steady-state switching be adopted. Among them, one of the easiest is based on integral
reset circuit, which will be introduced in this subsection,
( DTs ) , is needed to be properly designed.
instant, i.e., iref including slope compensated implementation and parabolic
Here an iterative criterion is adopted to determine the fast-scale compensated implementation. Through other methods, CRC
stability of the system, which is much simple, intuitive and compensation signal with different waveforms can also be
effective. As shown in Fig. 2(c), points A, B and C are selected constructed, without expatiation here.
as the iteration points. According to the geometric relations in 1) Slope Compensated Implementation (Integrating
Fig. 2(c), we have Once)
iref ( d nTs ) m2 (1 d n ) Ts + m1d n +1Ts =
iref ( d n +1Ts ) . (2)
I
A small-signal disturbance analysis can be performed for the
m = ( DTs )
iref-1 iref-1
duty cycles, so we have
i ( d T ) + m2 iref-1-cri
dn +1 = ref n s d . (3) mcri
( d n +1Ts ) m1 n
iref i
M
is the derivative of iref, i.e., the tangent slope of
Where, iref
0
the compensation signal, d and d are respectively the
n n +1 Tn TDn Tn+1 t
disturbance components of dn and dn+1. Fig. 3. Slope compensated implementation (Integrating once).
If the disturbance components of the duty cycle in any two
consecutive switching cycles are diminishing, expressed as Slope compensated implementation, shown with blue line in
d < d , the disturbance components will converge Fig. 3, can be got by integrating a DC input once through
n +1 n
integral reset circuit. The coordinate of point M is (TDn, i). The
gradually to zero, and the system is asymptotically stable. So compensation signal is needed to pass through point M to meet
according to (3) we have constraint (i). Therefore, its time domain expression can be
( d nTs ) + m2
iref derived as (6) according to the geometric relations in Fig. 3.
<1. (4) m (1 D ) Ts
( d n +1Ts ) m1
iref 1 mod (t ,Ts )
iref-1 ( t ) = mTs dt + mDTs + 2 (6)
In addition, in the small-signal disturbance analysis of the Ts 0 2
Here, the first-order integral term is implemented by integrating
duty cycles, the disturbance components dn and dn +1 are
a DC input once through integral reset circuit, other items are
( d nTs )
supposed quite small. Therefore, the tangent slopes iref DC variables. Therefore, (6) can be implemented with several
( d n +1Ts ) can be approximated to their steady-state
and iref DC inputs, an integral reset circuit, and several simple
arithmetic circuits. It should be noted that in the construction of
( DTs ) , i.e., iref
value iref ( d nTs ) iref
( d n +1Ts ) iref
( DTs ) . the proposed CRC compensation signal all the system variables
Substituting it into (3) yields are considered as DC variables, because the switching
( DTs ) < ( m2 m1 ) 2 = mcri .
iref (5) frequency is much higher than the variation of the system
variables.
So if the tangent slope of the compensation signal at the In this case, the tangent slope of the compensation signal
steady-state switching instant satisfies (5), fast-scale stability of is always equal to m. To meet constraint (ii), it is needed
iref-1
the system can be maintained. And mcri=(m2m1)/2 is the
critical value. =m<(m2m1)/2=mcri. iref-1-cri, shown with red line in
iref-1
In summary, the constraints of the compensation signal can Fig. 3, is the critical compensation signal, whose slope is mcri.
be concluded as: Slope compensated implementation that satisfies constraint (i)
(i) Average current tracking constraint: iref(TDn)=i. and constraint (ii) simultaneously can be seen as the result of
( DTs ) < (m2m1)/2=
(ii) Fast-scale stability constraint: iref rotating iref-1-cri clockwise around point M.
2) Parabolic Compensated Implementation (Integrating
mcri. Twice)
Based on integral reset circuit, we can also get parabolic
compensated implementation by integrating a DC input twice.

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A feasible scheme is shown with blue line in Fig. 4. Where, t=n A. Case of DC-DC Buck Converter
is the symmetry axis of the compensation signal waveform in 1) Evolution of the Proposed Control
the nth switching cycle, n=Tn+. This compensation signal is The schematic diagram of peak-current mode control
also needed to pass through point M to meet constraint (i). DC-DC Buck converter is exhibited in Fig. 5. In Buck
Therefore, its time domain expression can be derived as (7) converter the average reference current can be rebuilt as
according to the geometric relations in Fig. 4. iref-av=io according to power balance, where io is the load current.
Based on KCL, we have iL=iC+io, where iC is the capacitor
I current. So iC=iLio=iLiref-av can be involved into the control, as
iref-2 shown in Fig. 5(b).
( DTs )
iref-2
mcri iref-2-cri
Q L iL vo io

+
i Driver
M vin D C R vo
PWM
0 -
Tn n n-cri TDn Tn+1 t iC
Fig. 4. Parabolic compensated implementation (Integrating twice). (a)
iref
1 mod ( t ,Ts ) 1 mod ( t ,Ts ) m2Ts2 vo p1 CLK
iref-2 ( t ) = dtdt + + S PWM
Ts 0 Ts 0
( D + 1) Ts 2 + + iref Q
Vref k R
1 mod ( t ,Ts ) m2Ts m2Ts (Ts 2 ) iC=iLiref-av +
dt + (7)
Ts 0
( D + 1) Ts 2 2 ( D + 1) Ts 4 Comparator RS flip-flop
(b)
Here, the second-order integral term is implemented by
Fig. 5. Schematic diagram of peak-current mode control DC-DC Buck
integrating a DC input twice. Therefore, (7) can be converter. (a) Main circuit. (b) Proposed CRC control scheme.
implemented with several DC inputs, a first-order integral reset
circuit, a second-order integral reset circuit and several simple To simplify the circuit design, for slope compensated
arithmetic circuits. implementation of CRC, the slope of the compensation signal is
To meet constraint (ii), the tangential slope of the =
set to iref-1 m = m2 2 , which satisfies constraint (ii).
compensation signal at the steady-state switching instant Substituting it into (5) yields
should satisfy (5), that is
1 mod (t ,Ts ) m2Ts mT
m m1 iref-1 ( t ) = dt + 2 s
( DTs ) < 2
iref-2 . (8) Ts 0 2 2
2
So we have voTs 1 mod (t ,Ts )
1 0
= dt . (10)
T 2 L Ts
< s = cri . (9)
2 Here, m2=vo/L in Buck converter. For parabolic compensated
Here, cri=Ts/2 is the critical value of . The corresponding implementation of CRC, is set to 0. Substituting it into (6)
critical compensation signal is shown with red line in Fig. 5, yields
where t=n-cri=Tn+cri is the symmetry axis. To meet constraint voTs 2 mod ( t ,Ts ) 1 mod ( t ,Ts )
(ii) the symmetry axis of the compensation signal waveform iref-2
= (t ) 1
dtdt . (11)
2 ( D + 1) L Ts
0 0
Ts
should lie on the left of it.
As can be seen from the presentation above in this subsection, The tangent slope of the compensation signal at the steady-state
parabolic compensated implementation is more complex than ( DTs ) =
switching instant is iref-1 Dm2 ( D + 1) , which
slope compensated implementation. Similarly, higher order satisfies constraint (ii).
compensated implementation, integrating more than twice, can In addition, the proportional coefficient k in the outer-voltage
also be got based on integral reset circuit. The principle isloop is determined based on the small signal model of the
completely similar, but much more complex, without system, which is got as (12) for the Buck converter with the
expatiation here. proposed control.
D ( LC ) sC
III. TWO CASES OF APPLICATION = vo ( s ) 2 in ( )
v s 2 io ( s ) (12)
s + 2n s + n
2
s + 2n s + n2
In this section, two cases of application respectively to
Here, 2n=1/(RC)+2/(DTs), 2n =2kp1/(DTsC)+(2D1)/(DLC),
DC-DC converter and AC-DC converter are presented, and two
corresponding experimental platforms are built to verify the v , v and io are respectively the disturbance components of
o in
feasibility and priority of the proposed CRC control technique. vo, vin and io, and n are respectively the damping ratio and the
natural angular frequency. Therefore, in the case of k>0 the
stability of the system can always be ensured. In practical

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application the value of k can be selected to make the damping as can be seen from the experimental results in Fig. 7, slope
ratio be around 0.707 or 1. compensated implementation and parabolic compensated
2) Experimental Verification implementation of CRC have exactly the same control effect.
The circuit diagram of the Buck converter experimental Therefore, only the case of slope compensated implementation
platform is shown in Fig. 6, and the parameters are exhibited in is presented in all the following applications.
TABLE I.

iL 12 V Steady-state error vo (CH3: 5 V/div)

IRFP460 L vo
55 H
iC io 10 nF
Q CRC works ire f (CH2: 1 A/div)
+ 200 k 3.3 k
RHRP3060

C 33 F 10 k
PWM1
vin D R vo +15 V
vo/3 16 2 8 1 10 k +15 V
6 8
6.7 m 3 AD823 7
ESR 100 k 4 vd1 5 AD823
15 V
4 d C v (i )
15 V iL (CH4: 1 A/div)

Main circuit Capacitor current detection

Clock +15 V 0.1 F +15 V 0.1 F Driver PWM1
100 k
+15 V 0.1 F +15 V
8 1 0.1 F
4 8 14 7 5 3 3 11
15
7 2 14
NE 3
330 5
CD 7 13
555P 4049 CD IR
100
2 4 6 4013
6
2110S 8 2 (a)
6 5 1
10 F
12
4
1
1 nF PWM 1N4148
0.01 F
CLK 12 V Steady-state error vo (CH3: 5 V/div)

10 k 200 k 10 k
1 k +15 V 1 15 V CRC works
10 k ire f (CH2: 1 A/div)
LM393

+15 V 8 4
vo1 10 k 2 8
+15 V 10 k +15 V 8 10 k
10 k 6 8 2 +15 V
7 1 2 3
1 AD823
10 k 3
AD823 5
AD823 3
4 4
Vref 15 V
4
S vd(iC)
10 k 15 V 10 k 15 V 10 k iref-1 iL (CH4: 1 A/div)
10 k iref iref-2 Control circuit
vo1 10 k CD4016 CLK 10 k
+15 V
8 +15 V 1 nF +15 V
6
7
10 k 2 +15 V 10 k 8
10 k AD823 8
1 10 k 2 8
6
5 7
4 3 AD823
3 AD823
1
10 k 5
AD823 iref-1
vo/3 15 V 10 k
4
4 4
15 V 10 k
Slope compensated implementation 15 V vslope 10 k 15 V (b)
Parabolic compensated implementation 10 k 20 k
Fig. 7. Experimental waveforms of the proposed control before and after
10 k CD4016 CLK
vslope 10 k +15 V
1 nF
10 k +15 V
8
CRC works (The load here is a resistor of 10 ). (a) The case of slope
2 8
1 +15 V +15 V
6
compensated implementation. (b) The case of parabolic compensated
3 AD823 10 k vo1 10 k 10 k AD823
7

4
2 8
1
2 8
1
5
iref-2 implementation.
10 k 3 AD823 3 AD823 10 k
4
15 V 4 4 15 V
15 V
CRC circuit 10 k 10 k 15 V
In addition, to further verify the dynamic performance of the
Fig. 6. Circuit diagram of the Buck converter experimental platform.
proposed control, a comparison of load dynamic response
TABLE I between the traditional control with PI compensator and the
PARAMETERS OF THE BUCK CONVERTER EXPERIMENTAL PLATFORM proposed CRC control scheme is given in Fig. 8. The
Parameters Values Parameters Values experimental waveforms of the traditional control with PI
compensator when the load steps up and down are shown in Fig.
Input voltage Vin 24 V Capacitor C 33 F 8(a) and (b) respectively. Limited by the bandwidth of the PI
Output voltage 4V Output voltage 1/3
reference Vref sampling gain p1 compensator in the outer-voltage loop, it takes a few hundred
Rated output 12 V Proportional 12 microseconds of the system to reach a new steady state after the
voltage Vo coefficient k load steps. The experimental waveforms of the proposed CRC
Switching 100 kHz Load R 10 , 2.5
frequency fs control scheme when the load steps up and down are shown in
Inductor L 55 H -- -- Fig. 8(c) and (d) respectively. It takes only several switching
cycles of the system to reach a new steady state after the load
The experimental waveforms of the proposed control before steps, which is much reduced. Therefore, the dynamic
and after CRC works are shown in Fig. 7(a) and (b) for the performance of the system is significantly improved with the
cases of slope compensated implementation and parabolic proposed control.
compensated implementation respectively. Before CRC works
steady-state error in the output voltage and fast scale instability B. Case of Boost PFC Converter
both appear. However, they both disappear quickly after CRC To verify the effectiveness of the proposed CRC control
works for both these two cases. Therefore, the proposed CRC is technique applied to AC-DC converter, peak-current mode
able to realize average current tracking and effective control Boost PFC converter is investigated here as an example.
suppression of fast-scale instability simultaneously. In addition,

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1) Evolution of the Proposed Control

vo (CH3: 5 V/div) The schematic diagram of peak-current mode control Boost
PFC converter is shown in Fig. 9. The input is an ideal
sinusoidal AC voltage, i.e., vac=Vmsint, here Vm is the
amplitude, is the angular frequency which satisfy
=2f=2/T, f and T are the line frequency and the
corresponding cycle respectively. The input voltage is firstly
iL (CH4: 2 A/div)
rectified into vs=|vac| to feed the Boost circuit. The inductor
current iL is controlled to track the waveform of vs as accurately
as possible to get a high power factor input. Meanwhile, the
ts361 s
output voltage is controlled constant.
(a) vs L D vo

iac
vo (CH3: 5 V/div) +
vac Q C R vo
Driver

ts291 s PWM
iL (CH4: 2 A/div)
iL io
(a)
vo vs
iref
p3 p2 CLK
+ S
PWM
Vref + + iref Q
PI LPF R
iref +
(b) Multiplier iL
Comparator RS flip-flop
vo (CH3: 5 V/div) (b)
Reference current rebuilding
vo vs
io iref
p3 p2 CLK
S
iref-av + iref Q
PWM

+ R
+
Vref + + iL
iL (CH4: 2 A/div) k Comparator RS flip-flop
(c)
Fig. 9. Schematic diagram of peak-current mode control Boost PFC
ts65 s
converter. (a) Main circuit. (b) Traditional control scheme with PI
compensator. (c) Proposed CRC control scheme.
(c)
The average reference current can be rebuilt as
vo (CH3: 5 V/div)
iref-av = 2vo io vs Vm2 according to power balance. Completely
similar to the case of DC-DC Buck converter, the PI
compensator in the outer-voltage loop of Boost PFC converter
iL (CH4: 2 A/div)
ts68 s
can also be removed by introducing the rebuilt iref-av according
to the analysis in part A of section II, as shown in Fig. 9(c),
( )
where = 2 p2 p3Vm2 and k is the proportional coefficient.
Similar to the Buck converter experimental platform, for
slope compensated implementation of CRC, the slope of the
compensation signal is set to m=m2/2, which satisfies constraint
(d) (ii). Substituting it into (5) yields
Fig. 8. Load dynamic response comparison of the Buck converter. (a) 1 mod (t ,Ts ) m2Ts mT
The case of the traditional control with PI compensator when the load iref ( t ) = dt + 2 s
steps from 10 to 2.5 . (b) The case of the traditional control with PI Ts 0 2 2
compensator when the load steps from 2.5 to 10 . (c) The case of the
( vo vs ) Ts
1 mod (t ,Ts )
proposed CRC control scheme when the load steps from 10 to 2.5 .
1 0
= dt . (13)
(d) The case of the proposed CRC control scheme when the load steps 2L Ts
from 2.5 to 10 .
Here, m2=(vovs)/L in Boost PFC converter.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2017.2762622, IEEE
Transactions on Industrial Electronics
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Similar to the case of DC-DC Buck converter, the
proportional coefficient k in the outer-voltage loop is also
determined based on the small signal model of the system, and
not repeated here.
2) Analysis of the Steady-State Current Waveform
As we all know, for peak-current mode control Boost PFC
converter fast-scale instability exists inevitably near the
zero-crossing points of the inductor current, at which time the
duty cycle of the switch is close to 1. With traditional SC this
instability can be suppressed. As can be seen from Fig. 2(b), the
error between the average inductor current and the reference is
ierr=iL+mcd, here iL is the ripple amplitude of the inductor
current, the duty cycle d and the reference current iref both vary
with line frequency, and can be regarded as constants during a
switching cycle. Due to the existence of ierr, the inductor
points. The 25 kHz component can be clearly observed in the
FFT result. With tradition SC, fast-scale instability is
suppressed effectively, without 25 kHz component in the FFT
result. While, dead-zones exist around the zero-crossing points
of the input current, consistent with the analysis in (15). In
contrast, in the case with the proposed CRC, due to the
achievement of average current tracking the input current
waveform is a perfect sine wave, without zero-crossing
dead-zones, consistent with the analysis in (16). Moreover,
fast-scale instability is also suppressed effectively with the
proposed CRC, without 25 kHz component in the FFT result.
Therefore, the current waveform quality of the Boost PFC
converter is much improved with the proposed CRC.
vs L
2 mH
D vo

current waveform distorts. According to the current waveform iac

490 k
RHRP3060

490 k
in Fig. 2(b), the average inductor current during the period of [0, vac vs/50
15 V PWM1 IRFP460 C
vo/50
15 V
R
T/2] can be expressed as 10 k 0.005iL
Q
470 F
10 k 0.005io

iL1-av =iref mc d iL 6
LA25-NP
1 6
LA25-NP
1

vs Re1 mc (1 vs vo ) vsTs (1 vs vo ) ( 2 L ) Main Circuit

KBPC2510 +15 V +15 V

Clock +15 V 0.1 F +15 V 0.1 F Driver

0.1 F +15 V 0.1 F

K1Vm sin (t ) + K 2 (1 cos ( 2t ) ) mc 0.

+15 V

(14)
8 1
100 k
CLK1 4 8 14 7 5 3
2
3 11
15
7 14
NE 3
330 5
CD 7 13 PWM1
100 IR
Where, Re1 is the equivalent input resistance,
555P 4049 CD 6
2110S 8 2
2 4 6 4013 10 F
1N4148 10 k 1 nF 6 5 1 12
4

K1=1/Re1T/(2L)+mcp3/Vref, K 2 = Vm2 p3T ( 4Vref L ) [20].

1
1 nF PWM 1N4148
0.01 F
CLK
CLK

Because of the unilateral conductivity of the diode D, iL cant be CRC circuit

10 k CD4016 CLK1
10 k
Comparing unit
+15 V

negative, i.e., iL1-av0. Equation (14) can be rewritten as

10 k +15 V
+15 V 1 nF 3 k
vs1 10 k +15 V 10 k 13 4 S 330 2 3 k
2 8
4 10 k 14 1

t [ 0, t0 ] [T 2 t0 , T 2]
vo2 10 k 1 6 4 +15 V 12 LF347 iref 3 LM393

0,
3 LF347 7 20 k 9 4
11 5 LF347 10 k 11 4 1 k
8 330 15 V

iL1- av ( t )
10 k 11 10 LF347
15 V 11 10 k 15 V 40 k
10 k

K1Vm sin t + K 2 (1 cos ( 2t ) ) mc , t ( t0 , T 2 t0 ) .

15 V 20 k
+15 V 15 V +15 V +15 V 0.005iL +15 V
6 13 4
2 4 vo2 4
7
9 4
8 200 10 k 12 14
vo/50 10 k LF347
1
vs/50 10 k 5 LF347 10 k 10 LF347 LF347
3
vs2 11

(15)
11 11 11
vs1 10 k
15 V 15 V 15 V 15 V

Where, t0 is the critical time of iL1-av(t0)0. Dead-zones exist 0.005io +15 V

vo2 7
+15 V
14
50 k
100 k
+15 V 100 k
+15 V
around the zero-crossing points of the inductor current, during vs2 7
2 4
10 k 1 12 11
15 V 50 k
3 LF347 AD 1 6
14 15 V +15 V
9 4 11
11 532-JD 2 7 12
AD 10 k
10 k
which iL1-av0.
10 5 LF347 1 9 4
200 9
15 V 13 3 15 V 11 532-JD 2 8 10 k
10 10 LF347
10 k 50 k 10 k 15 V 13 3 15 V i
11 ref-av
+15 V
While, in the case with the proposed CRC, the average 10 k 10 k
+15 V 10 k 10 k 15 V
vo2 10 k +15 V 13 4
14
2 4 10 k +15 V
inductor current is able to track the reference current accurately,
10 k 12 LF347
10 k 3 LF347
1 6 4
7
10 k
9
iref +15 V 11
11 5 LF347
4
8
10 k 13 10 k
4
Vref 11 10 LF347 15 V
that is
14
10 k 10 k 11 10 k 12 LF347
15 V
15 V 10 k 11
15 V iref-av 10 k

iL 2- av iref vs Re 2 = (Vm Re 2 ) sin t .

15 V

(16) Outer voltage loop

Fig. 10. Circuit diagram of the Boost PFC converter experimental
Here, Re2 is the equivalent input resistance. platform.
Obviously, the average inductor current in the case with
TABLE II
traditional SC distorts seriously because of the zero-crossing PARAMETERS OF THE BOOST PFC CONVERTER EXPERIMENTAL PLATFORM
dead-zones and the non-fundamental components in (15).
While, the average inductor current in the case with the Parameters Values Parameters Values
proposed CRC only contains a fundamental component, which Line voltage 70 2 V Capacitor C 470 F
is much improved, as shown in (16). magnitude Vm
3) Experimental Verification Output voltage 3V Input voltage 0.1
reference Vref sampling gain p2
The circuit diagram of the Boost PFC experimental platform Rated output 150 V Output voltage 0.02
is shown in Fig. 10, and the parameters are exhibited in TABLE voltage Vo sampling gain p3
II. Switching 50 kHz Proportional 1
frequency fs coefficient k
The steady-state experimental waveforms of the input Line frequency f 50 Hz Intensity of SC mc 0.6
voltage vac, the input current iac and its FFT result are shown in Inductor L 2 mH Load R 120 ,
Fig. 11(a), (b) and (c) for the cases without compensation, with 200 , 100
traditional SC and with the proposed CRC respectively. For all
these three cases, the input current iac tracks the waveform of The dominant harmonic components of the input current are
the input voltage vac very well, and a high power factor is compared in TABLE III, combined with THD. Although
obtained. But in the case without compensation, fast-scale fast-scale instability is suppressed with traditional SC, the
instability appears in the input current around the zero-crossing harmonic components even increase because of the waveform

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2017.2762622, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

distortion. With the proposed CRC, the harmonic components

decrease significantly. vo (CH3: 50 V/div)

vac (CH3: 50 V/div) iac (CH4: 5 A/div) Fast scale instability

ts46 ms

iav (CH4: 5 A/div)

FFT of iac
25 kHz 50 kHz
(a)

vo (CH3: 50 V/div)
(a)

vac (CH3: 50 V/div) iac (CH4: 5 A/div) Zero-crossing dead-zone

ts69 ms

iav (CH4: 5 A/div)

FFT of iac
25 kHz 50 kHz
(b)

vo (CH3: 50 V/div)
(b)

vac (CH3: 50 V/div) iac (CH4: 5 A/div) Without zero-crossing dead-zone

iav (CH4: 5 A/div)

FFT of iac
25 kHz 50 kHz
(c)

vo (CH3: 50 V/div)
(c)
Fig. 11. Steady-state experimental waveforms of the Boost PFC
converter experimental platform. (a) The case without compensation. (b)
The case with traditional SC. (c) The case with the proposed CRC.
iav (CH4: 5 A/div)
TABLE III
DOMINANT HARMONIC COMPONENTS AND THD
Without With With the
compensation traditional SC proposed CRC
Fundamental 4.00 A 4.00 A 4.00 A
amplitude (50Hz)
3rd harmonic 0.30 A 0.39 A 0.04 A (d)
amplitude (150Hz) Fig. 12. Load dynamic response comparison of the Boost PFC
5th harmonic 0.06 A 0.14 A 0.02 A converter. (a) The case of the traditional control with PI compensator
amplitude (250Hz) when the load steps from 200 to 100 . (b) The case of the traditional
7th harmonic 0.02 A 0.10 A 0.01 A control with PI compensator when the load steps from 100 to 200 . (c)
amplitude (350Hz) The case of the proposed CRC control scheme when the load steps
THD 11.47% 12.03% 4.95% from 200 to 100 . (d) The case of the proposed CRC control scheme
when the load steps from 100 to 200 .

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2017.2762622, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
In addition, to further verify the dynamic performance of the
proposed control, Figure 12 gives a comparison of the dynamic
experimental results between the traditional control with PI
compensator and the proposed CRC control scheme when the
load steps up and down. The dynamic experimental waveforms
of the traditional control with PI compensator are shown in Fig.
12(a) and (b). Limited by the bandwidth of the PI compensator
and the low pass filter (LPF) in the outer-voltage loop, it takes a
few line cycles of the system to reach a new steady state after
the load steps. The dynamic experimental waveforms of the
proposed CRC control scheme are shown in Fig. 12(c) and (d).
It takes only several switching cycles of the system to reach a
new steady state after the load steps, which is greatly reduced.
Therefore, the dynamic performance of the system is
significantly improved with the proposed control.
IV. CONCLUSION
For ripple-current mode control switching power converters,
there is an inherent error between the average of the controlled
current and the reference current. In addition, fast-scale
instability may occur in some operating condition. To solve
these two problems effectively, a current-ripple compensation
(CRC) control technique is proposed in this paper. On this basis,
the dynamic performance of the system is further improved by
removing the integral part of the PI compensator in the
outer-voltage loop. As analyzed and verified in the sections
above, conclusions can be got as:
1) For ripple-current mode control switching power
converters, the proposed CRC is able to realize average
current tracking and effective suppression of fast-scale
instability simultaneously.
2) With the proposed CRC, the integral part of the PI
compensator in the outer-voltage loop can be removed by
introducing the rebuilt average reference current, and the
dynamic performance of the system is further improved.
3) Current tracking accuracy can be improved with the
application of proposed CRC to AC-DC converter, where
accurate current tracking is always needed.
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Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

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Weiguo Lu (M14) received the B.S., M.S., and

Ph.D. degrees in electrical engineering from
Chongqing University, Chongqing, China, in
2000, 2003, and 2008, respectively.
He is currently a Professor in School of
Electrical Engineering, Chongqing University,
Chongqing, China. He is the author or coauthor
of more than 20 papers in journal or conference
proceedings. His current research interests
include the stability analysis and control
strategies of switching power converters, magnetic-resonance wireless
power transfer.

Shaoling Li was born in Henan Province, China,

in 1990. He received the B.S. degree in electrical
engineering from Luoyang Institute of Science
and Technology, Luoyang, China, in 2012, and
M.S. degree in electrical engineering from
Henan Polytechnic University, Jiaozuo, China, in
2015.
He is currently working toward the Ph.D.
degree in School of Electrical Engineering,
Chongqing University, Chongqing, China. His
research interests include power electronic system and its control.

Weiming Chen received the B.S. degree in

electrical engineering from Chongqing University,
Chongqing, China, in 2014.
He is currently working toward the Ph.D.
degree in School of Electrical Engineering,
Chongqing University, Chongqing, China. His
research interests include magnetic-resonance
wireless power transfer.

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