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Department of Electronics and communication Engineering VLSI Lab 10EC77

1. CMOS Inverter
AIM:
Design a CMOS Inverter with following specifications:
For PMOS Wp = 3m and Lp = 180nm.
For NMOS Wn = 1m and Ln = 180nm
Perform Transient and DC analysis on Designed inverter Schematic with given specifications.
Draw the layout of the inverter; Perform DRC, LVS and QRC on the layout. Simulate the inverter with
extracted parasitics.
Compare the results of Inverter schematic and layout.

SOFTWARE TOOLS USED:

a) Schematic: Virtuoso Schematic


b) Simulation: Spectre
c) Layout: Virtuoso Layout
d) DRC, LVS and QRC: Assura

SCHEMATIC DIAGRAM:

1 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

SYMBOL VIEW:

TEST ENVIRONMENT:

2 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

ADEL VIEW:

SIMULATION RESULTS:

Transient Analysis:

TpLH TpHL

PROPAGATION DELAYS MEASUREMENTS:


TpLH: 76.38 ps
(Measured using delay function in calculator)
TpHL: 36.61ps

3 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

DC Analysis:

SWITCHING THRESHOLD:
Vinv: 865.102mV

LAYOUT:

4 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

DRC Passed Successfully


LVS Passed Successfully

Layout Area:
8.225m x 7.16m = 58.891m2

RCX Extracted:

SIMULATION RESULTS WITH RCX EXTRACTED:

Transient Analysis:

TpLH TpHL

PROPAGATION DELAYS MEASUREMENTS:

TpLH: 83.88 ps
(Measured using delay function in calculator)
TpHL: 42.54 ps

DC Analysis:

SWITCHING THRESHOLD:
Vinv: 865.322mV

5 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

SUMMARY COMPARISON:

Sl. No Parameter Schematic Layout


1. TpLH 76.38 ps 83.88 ps
2. TpHL 36.61 ps 42.54 ps
3. Vinv 865.102mV 865.322mV

6 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

2. CS Amplifier
AIM:
Design a CMOS CS Amplifier with following specifications:
For Active PMOS transistor Wp = 50m and Lp = 1m.
For Load NMOS transistor Wn = 10m and Ln = 1m
Perform Transient, DC and AC analysis on Designed C Amplifier Schematic with given specifications.
Draw the layout of the CS Amplifier; Perform DRC, LVS and RCX on the layout. Simulate the CS
Amplifier with extracted parasitics.
Compare the results of CS Amplifier schematic and layout.

SOFTWARE TOOLS USED:

a) Schematic: Virtuoso Schematic


b) Simulation: Spectre
c) Layout: Virtuoso Layout
d) DRC, LVS and QRC: Assura

SCHEMATIC DIAGRAM:

7 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

SYMBOL VIEW:

TEST ENVIRONMENT:

8 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

ADEL VIEW:

SIMULATION RESULTS:
Transient Analysis:

Vin p-p = 9.979 mV


(Using Calculator function PeaktoPeak)
Vout p-p = 39.56 mV
Voltage Gain =Av= Vout p-p/ Vin p-p= 3.964 V/V
Av in dB = 20 log (Vout p-p/ Vin p-p) = 11.96dB.

9 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

DC Analysis:

SWITCHING THRESHOLD:
Vinv: -60.8mV

AC Analysis:

Voltage Gain =Av= 3.9628 V/V


Bandwidth = 1.328GHz (Using Calculator function bandwidth)

Ac Analysis Plot in Magnitude and Phase:

Go to ADEL, Results ---> Direct Plot ---> Magnitude and Phase


Select Vout from your CS amplifier Test Environment
Press ESC

10 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

Gain in dB = 11.96 dB.


Phase = 180o

To Measure Bandwidth and Phase Shift manually:

Insert a horizontal Line at (11.96 - 3) = 8.96dB

On Y axis you will get Bandwidth as 1.3269GHz.

To Find the Phase shift, insert a vertical Line at 1.3296 GHz

You will get Phase Shift as 132.19o at cut off frequency of 1.3296 GHz.

11 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

LAYOUT:

DRC Passed Successfully


LVS Passed Successfully

Layout Area:
61.7m x 15.06m = 929.02m2

RCX Extracted:

12 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

SIMULATION RESULTS WITH RCX EXTRACTED:

Transient Analysis:

Vin p-p = 9.967 mV (Using Calculator function PeaktoPeak)


Vout p-p = 32.18 mV
Voltage Gain =Av= Vout p-p/ Vin p-p= 3.228 V/V
Av in dB = 20 log (Vout p-p/ Vin p-p) = 10.178dB.

DC Analysis:

SWITCHING THRESHOLD:
Vinv: -103.8mV

13 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

AC Analysis:

Voltage Gain =Av= 3.224 V/V


Bandwidth = 1.133GHz (Using Calculator function bandwidth)

Ac Analysis Plot in Magnitude and Phase:

Gain in dB = 10.168 dB.


Phase = 180o

To Measure Bandwidth and Phase Shift manually:

Bandwidth as 1.3266GHz at (10.168-3) = 7.168dB.

14 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

Phase Shift = 120.184o at cut off Bandwidth 1.13266GHz

SUMMARY COMPARISON:

Sl. No Parameter Schematic Layout


1. Vin 9.979mV 9.976mV
2. Vout 39.56mV 32.18mv
3. Gain 3.96V/V 3.224V/V
4. Gain in dB 11.96dB 10.168dB
5. Vinv -60.8mV -103.8mV
6. Bandwidth 1.328GHz 1.1326GHz
7. Phase 180o 180o
8. Phase Shift 132.19o 120.285o

15 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

3. CD Amplifier
AIM:
Design a CD Amplifier with following specifications:
For Active NMOS transistor Wp = 50m and Lp = 1m.
For Load NMOS transistor Wn = 10m and Ln = 1m
Perform Transient, DC and AC analysis on Designed CD Amplifier Schematic with given specifications.
Draw the layout of the CD Amplifier; Perform DRC, LVS and RCX on the layout. Simulate the CD
Amplifier with extracted parasitics.
Compare the results of CD Amplifier schematic and layout. Try to improve the gain of CD amplifier with
changing above mentioned specifications, such that gain is closer to that of a unity gain amplifier.

SOFTWARE TOOLS USED:

a) Schematic: Virtuoso Schematic


b) Simulation: Spectre
c) Layout: Virtuoso Layout
d) DRC, LVS and QRC: Assura

SCHEMATIC DIAGRAM:

16 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

SYMBOL VIEW:

TEST ENVIRONMENT:

17 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

ADEL VIEW:

SIMULATION RESULTS:
Transient Analysis:

Vin p-p = 9.973 mV

Vout p-p = 8.070 mV

Voltage Gain =Av= Vout p-p/ Vin p-p= 0.809 V/V

Av in dB = 20 log (0.809) = -1.83dB.

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Department of Electronics and communication Engineering VLSI Lab 10EC77

AC Analysis:

Voltage Gain =Av= 0.809 V/V


Bandwidth =

Ac Analysis Plot in Magnitude and Phase:

Gain in dB = -1.839 dB.


Phase = 0o

19 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

LAYOUT:

DRC Passed Successfully


LVS Passed Successfully

Layout Area:
12.72m x 56.715m = 721.41m2

RCX Extracted:

av_extracted View:

20 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

SIMULATION RESULTS WITH RCX EXTRACTED:

Transient Analysis:

Vin p-p = 9.973 mV


Vout p-p = 8.066 mV
Voltage Gain =Av= Vout p-p/ Vin p-p= 0.808 V/V
Av in dB = 20 log (0.809) = -1.843dB.

AC Analysis:

Voltage Gain =Av= 0.800 V/V


Bandwidth =

21 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

Ac Analysis Plot in Magnitude and Phase:

Gain in dB = -1.843 dB.


Phase = 0o

SUMMARY COMPARISON:

Sl. No Parameter Schematic Layout


1. Vin 9.973mV 9.973mV
2. Vout 8.070mV 8.066mv
3. Gain 0.809V/V 0.808V/V
4. Gain in dB -1.83dB -1.843dB
5. Bandwidth
6. Phase 0o 0o

22 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

4. Differential Amplifier
AIM:
Design a Differential Amplifier with following specifications:
For Active NMOS transistors Wp = 3m and Lp = 1m.
For Load PMOS transistors Wn = 15m and Ln = 1m.
For Current Source NMOS transistors Wn = 4.5m and Ln = 1m.
Idc: 30A, Vdd: 2.5V Vss: -2.5V.
Perform Transient, DC and AC analysis on Designed Differential Amplifier Schematic with given
specifications.
Draw the layout of the Differential Amplifier; Perform DRC, LVS and RCX on the layout. Simulate the
Differential Amplifier with extracted parasitics.
Compare the results of Differential Amplifier schematic and layout.

SOFTWARE TOOLS USED:

a) Schematic: Virtuoso Schematic


b) Simulation: Spectre
c) Layout: Virtuoso Layout
d) DRC, LVS and QRC: Assura

SCHEMATIC DIAGRAM:

23 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

SYMBOL VIEW:

TEST ENVIRONMENT:

24 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

ADEL VIEW:

SIMULATION RESULTS:

Transient Analysis:

Vin p-p = 9.998 mV


Vout p-p = 953.6 mV
Voltage Gain =Av= Vout p-p/ Vin p-p= 95.37 V/V
Av in dB = 20 log (0.809) = -39.58 dB.

25 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

DC Analysis:

SWITCHING THRESHOLD:
Vinv: -68.59mV

AC Analysis:

Voltage Gain =Av= 101.954 V/V


Bandwidth = 8.132MHz

Ac Analysis Plot in Magnitude and Phase:

Go to ADEL, Results ---> Direct Plot ---> Magnitude and Phase


Select Vout from your CS amplifier Test Environment
Press ESC

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Department of Electronics and communication Engineering VLSI Lab 10EC77

Gain in dB = 40.168 dB.


Phase = 0o

To Measure Bandwidth and Phase Shift manually:

Phase Shift: -46.37o

27 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

LAYOUT:

DRC Passed Successfully


LVS Passed Successfully
Layout Area:
35.85m x 17.235m = 617.874m2

RCX Extracted:

28 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

SIMULATION RESULTS WITH RCX EXTRACTED:

Transient Analysis:

Vin p-p = 9.998 mV


Vout p-p = 953 mV
Voltage Gain =Av= Vout p-p/ Vin p-p= 95.31 V/V
Av in dB = 20 log (0.809) = -39.58 dB.

DC Analysis:

SWITCHING THRESHOLD:
Vinv: -68.59mV

29 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

AC Analysis:

Voltage Gain =Av= 101.902 V/V


Bandwidth = 7.604MHz

Ac Analysis Plot in Magnitude and Phase:

Gain in dB = 40.163 dB.


Phase = 0o

30 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

Phase Shift: -46.34o

SUMMARY COMPARISON:

Sl. No Parameter Schematic Layout


1. Vin 9.998mV 9.998mV
2. Vout 953.6mV 953mv
3. Gain 101.954V/V 101.902V/V
4. Gain in dB 40.168dB 40.163dB
5. Vinv -68.59mV -68.59mV
6. Bandwidth 8.132MHz 7.604MHz
7. Phase 0o 0o
8. Phase Shift -46.37o -46.34o

31 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

5. Operational Amplifier
AIM:
Design an Operational Amplifier with following specifications:
Differential Amplifier:
For Active NMOS transistors Wp = 3m and Lp = 1m.
For Load PMOS transistors Wn = 15m and Ln = 1m.
For Current Source NMOS transistors Wn = 4.5m and Ln = 1m.
Common Source Amplifier:
For Active PMOS transistor Wp = 50m and Lp = 1m.
For Load NMOS transistor Wn = 10m and Ln = 1m
Idc: 30A, Vdd: 2.5V Vss: -2.5V.
Perform Transient, DC and AC analysis on Designed Operational Amplifier Schematic with given
specifications.
Draw the layout of the Operational Amplifier; Perform DRC, LVS and RCX on the layout. Simulate
the Operational Amplifier with extracted parasitics.
Compare the results of Operational Amplifier schematic and layout.

SOFTWARE TOOLS USED:

a) Schematic: Virtuoso Schematic


b) Simulation: Spectre
c) Layout: Virtuoso Layout
d) DRC, LVS and QRC: Assura

SCHEMATIC DIAGRAM:

32 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

SYMBOL VIEW:

TEST ENVIRONMENT:

33 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

ADEL VIEW:

SIMULATION RESULTS:

Transient Analysis:

Vin p-p = 9.98 V


Vout p-p = 42.34 mV
Voltage Gain =Av= Vout p-p/ Vin p-p= 4.242k V/V
Av in dB = 20 log (0.809) = -72.55 dB.

34 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

DC Analysis:

SWITCHING THRESHOLD:
Vinv: -44.81mV

AC Analysis:

Voltage Gain =Av= 4.25k V/V


Bandwidth = 218.9kHz

35 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

Ac Analysis Plot in Magnitude and Phase:

Gain in dB = 72.566 dB.


Phase = 180o

Phase Shift: 134.902o

36 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

LAYOUT:

DRC Passed Successfully


LVS Passed Successfully
Layout Area:
54.235m x 24.7m = 1339.6045m2

RCX Extracted:

37 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

SIMULATION RESULTS WITH RCX EXTRACTED:

Transient Analysis:

Vin p-p = 9.979 V


Vout p-p = 37.76 mV
Voltage Gain =Av= Vout p-p/ Vin p-p= 3.783k V/V
Av in dB = 20 log (0.809) = -71.55 dB.

DC Analysis:

SWITCHING THRESHOLD:
Vinv: -45.23mV

38 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

AC Analysis:

Voltage Gain =Av= 3.78k V/V


Bandwidth = 233.33kHz

Ac Analysis Plot in Magnitude and Phase:

Gain in dB = 71.563 dB.


Phase = 180o

39 St. Joseph Engineering College, Mangaluru


Department of Electronics and communication Engineering VLSI Lab 10EC77

Phase Shift: 134.895o

SUMMARY COMPARISON:

Sl. No Parameter Schematic Layout


1. Vin 9.98V 9.979V
2. Vout 42.34mV 37.76mv
3. Gain 4.25kV/V 3.78kV/V
4. Gain in dB 72.566dB 71.56dB
5. Vinv -44.81mV -45.23mV
6. Bandwidth 218.9kHz 233.33Hz
7. Phase 180o 180o
8. Phase Shift 134.902o 134.895o

Prepared by:

Keith R Fernandes.
Asst. Professor, Dept of ECE
SJEC, Mangaluru

40 St. Joseph Engineering College, Mangaluru