#!

/usr/bin/perl
##############################################################################
## Description # This script generates a template vhdl file form a port list
##############################################################################
## Date # Who # Version # Details
##############################################################################
## 10/06/08 # Avi # 1 # Initial Revision
##############################################################################

#-$Author: amittal $
#-$Date: Thu Jun 26 15:57:29 2008 $
#-$Revision: 1.3 $
#-$Log: genEntity.pl.rca $
#-
#- Revision: 1.3 Thu Jun 26 15:57:29 2008 amittal
#- Removed comment bug
#-$Revision: 1.3 $
#-$KeysEnd$

use File::Find;
use Cwd;

$iter = 0;
if($#ARGV < 0) {
print "ERROR: insufficient fields\n";
print "Usage:\nlinux_prompt> genEntity.pl <port list file>\n";
print "\n";
print "Example Port list file is given below,# is a comment character\n";
pHelp();
exit;
}

if(!(-f @ARGV[0]))
{
print "ERROR! Input file @ARGV[0] does not exists. . . Exiting\n";
exit;
}

$cwd = getcwd();
@paths = split(/\//,$cwd);
$block_dir = pop(@paths);

$user_dir = pop(@paths);

$user = `echo \$USER`;

chomp($user);

$ff = "$ARGV[0]";
#t#@ffs = split(/\//, $ff);
#t#$out_file_name = pop(@ffs);
#f#print "file name minus path = $out_file_name,array = @ffs,orig argv0 = $ff\n";
#t#$line_number = 0;
open(infile0,"<$ff") || die "Couldnft open infile0. $ff\n ";
#system("awk f/module/,/endmodule/f @ARGV[0]>@ARGV[0].module")
$found_entity = 0;
$found_arch = 0;
while ($line0 = <infile0>)
 {
chomp($line0);
$line_number ++;
$line0 =~ s/^/ /g; #add a space at start
$line0 =~ s/$/ /g; #add a space at end
$line0 =~ s/\-\-.*//g; #remove comments
$line0 =~ s/#.*//g; #remove comments
#print "line0 comment removed = $line0\n";
next if(!($line0 =~ /(\w+)/)); #Revmoved Empty lines

if($line0 =~ /( entity)(\s+)(\w+)(\s+)(\w+)/)
{
print "ERROR! T0: At $line_number:($line0): Expected Input is of the form
\n";
print "entity entity_name\n";
exit;
}
elsif($line0 =~ /(architecture)(\s+)(\w+)(\s+)(\w+)/)
{
print "ERROR! T1: At $line_number:($line0): Expected Input is of the form
\n";
print "architecture architecture_name\n";
exit;
}
elsif($line0 =~ /(port)(\s+)(\w+)(\s+)(\w+)(\s+)(\w+)(\s+)(\w+)/)
{
print "ERROR! T2: At $line_number:($line0): Expected Input is of the form
\n";
print "port port_name port_direction port_type_or_size\n";
exit;
}
elsif($line0 =~ /( entity)(\s+)(\w+)/)
{
#print "Found entity = $3\n";
$entity_name = $3;
$found_entity = $found_entity + 1;
}
elsif($line0 =~ /( architecture)(\s+)(\w+)/)
{
#print "Found architecture = $3\n";
$arch_name = $3;
$found_arch = $found_arch + 1;
}
elsif($line0 =~ /( port)(\s+)(\w+)(\s+)(\w+)(\s+)(\w+)/)
{
#print "Found port = $3\n";
push(@ports_dir,$5);
push(@ports_type,$7);
push(@ports,$3);
if($7 =~ /\D/)
{
push(@generics, $7); #Non Digits
}
}# elsif($line0 =~ /( port)(\s+)(\w+)(\s+)(\w+)(\s+)(\w+)/)
else
{
print "ERROR! T3: At $line_number:($line0): Expected Input is of the form
\n";
pHelp();
 }

} #while ($line0 = <infile0>)

open(out,">$entity_name.vhd") || die "Could not open $entity_name.vhd\n" ;

if($found_entity == 1 && $found_arch == 1)

{
#print "ports = @ports\n";
#print "ports_dir = @ports_dir\n";
#print "ports_type = @ports_type\n";
print out "\-\-Generated by genEntity.pl Report Problems to
aviral.mittal\@intel.com\n";
print out "LIBRARY IEEE;\n";
print out "USE IEEE.std_logic_1164.ALL;\n";
print out "\n";
print out "ENTITY $entity_name IS\n";
print out " PORT (\n";
foreach $port (@ports)
{
$direction = shift(@ports_dir);
$type = shift(@ports_type);
if($type =~ /\D/) #Non Digits
{
$type_mod = $type;
}
else
{
$type_mod = "std_logic" if $type == 1;
$type_mod = "std_logic_vector($type-1 downto 0)" if $type > 1;
}
print out " $port : $direction $type_mod";
print out ";\n" if(@ports_dir);
}# foreach port (@ports)
print out "\n";
print out " );\n";
print out "END $entity_name;\n";
print out "\n";
print out "ARCHITECTURE $arch_name OF $entity_name IS\n";
print out "\-\-SIGNAL Declaration Section Starts\n";
print out " \-\-SIGNAL data_out_sig std_logic_vector(1 downto 0);\n";
print out "\-\-SIGNAL Declaration Section Ends\n";
print out " BEGIN\n";
print out "\-\-sync_reset_p : PROCESS(clk)\n";
print out "\-\- BEGIN\n";
print out "\-\- IF(rising_edge(clk)) then\n";
print out "\-\- IF(rstn = '0') THEN\n";
print out "\-\- data_out_sig <= (others => '0');\n";
print out "\-\- ELSE\n";
print out "\-\- data_out_sig <= data_in;\n";
print out "\-\- END IF;\n";
print out "\-\- END IF;\n";
print out "\-\-END sync_reset_p;\n";
print out "\n";
print out " END $arch_name;\n";
print "INFO! Generated $entity_name.vhd\n";
}# if($found_entity == 1 && $found_arch == 1)
else
{
 print "ERROR! T4: Multiple Entities found\n" if($found_entity > 1);
print "ERROR! T4: Multiple Architectures found\n" if($found_arch > 1);
}

sub pHelp
{
print "------------------\n";
print "#port_name direction size_type\n";
print "entity state_machine \n";
print "port clk in 1\n";
print "port rstn in 1\n";
print "port datain IN width1\n";
print "port dataout OUT width2\n";
print "port ready out 1\n";
print "port sync_out out mydatatype\n";
print "port fft_out out 8\n";
print "architecture rtl\n";
print "-----------------------\n";
exit;
}