Analog Integr Circ Sig Process
DOI 10.1007/s10470-016-0845-7
A new fast settling low power CMOS gain stage architecture
Shamin Sadrafshari1 Mina Hassanzadazar1 Khayrollah Hadidi1
Abdollah Khoei1
Received: 27 February 2016 / Revised: 13 August 2016 / Accepted: 19 August 2016
Springer Science+Business Media New York 2016
Abstract This paper presents a new gain stage for high
accuracy and fast settling applications. In the proposed
structure a novel combination of closed loop and open loop
amplifiers is employed to achieve high accuracy and
enhanced settling behavior while adding only negligible
power to the main circuit power constraint. To evaluate the
functionality of the proposed idea, a zero cross based cir-
cuit and a switch capacitor amplifier are designed to
implement the open loop and the closed loop stages,
respectively. Though, other topologies for implementation
of open loop and closed loop amplifiers are applicable in
the presented gain stage. The proposed structure is imple-
mented in 0.18 lm CMOS technology. HSPICE simulation
results, using level 49 models, demonstrate that the new
configuration improves the power efficiency and the set-
tling behavior as well as the system accuracy. The pro-
posed scheme shows very fast settling times of 0.8, 1.01,
1.41 ns for the gain accuracies of 6, 8 and 10 bits,
respectively, while loaded with 1 pF capacitance and the
output swing is 1.6 V. In comparison with a conventional
switched capacitor closed loop amplifier, the proposed
architecture improves the settling performance by a factor
of 3 for 6 bit resolution, while it adds only 0.63 mW power
to the total power consumption that is 8.68 mW.
Keywords Closed loop amplifier  Gain stage  Open loop
amplifier  Zero cross based circuit
& Shamin Sadrafshari
sh.sadrafshari@urmia.ac.ir
1
Microelectronics Research Laboratory, Urmia University,
Urmia, Iran
1 Introduction
High gain and high-speed amplifiers are the key compo-
nents that determine the overall resolution and speed of
modern analog systems. The ongoing miniaturization of
CMOS transistors, in advanced fabrication processes,
improves the device switching speed and reduces the area
of digital circuits. However, the device transconductance
and its unity-gain bandwidth decreases in this trend that
translates to severe constraints on the settling behavior of
amplifiers. Hence every advanced process set a more
stringent limit on the achievable gain and speed in CMOS
analog circuits. In addition, increasing the bandwidth even
in the process-dependent margins leads to increased power
consumption. Another issue in modern process technolo-
gies is the drop in supply voltages, which causes the loss in
the dynamic range. Specifically higher current and larger
load capacitance have to be used to reduce the circuit noise
and enhance the signal to noise ratio (SNR) that in turn
degrades the bandwidth of the amplifier. As a result,
designing an amplifier with high gain, high frequency
range and low power consumption is a major challenge.
The wide variety of tradeoffs imposed by the advanced
fabrication processes has encouraged integrated circuit (IC)
designers to investigate new amplifier structures depending
on the required specifications.
In this paper, a new structure is proposed that take the
advantage of both open loop and closed loop amplifiers to
achieve high speed and accuracy, simultaneously.
The proposed structure is implemented in 0.18 lm
CMOS technology as a proof of concept. However, the
design procedure can be applied in other modern processes
for achieving power efficiency as well as high accuracy and
fast settling behavior. The amplifier slewing efficiency is
also improved in comparison with conventional closed
123

loop amplifiers. A switched capacitor (SC) amplifier [1]
and a zero cross based circuit (ZCBC) [2] are used as
closed loop and open loop amplifiers, respectively, in order
to introduce the new structure.
The rest of the paper is organized as follows. Section 2
describes the contradicting tradeoffs and technology con-
straints in gain stage design. The new method is introduced
in Sect. 3. Section 4 introduces building blocks of the
proposed circuit including a ZCBC and a conventional SC
topology. Settling time and power consumption have been
discussed in Sects. 5 and 6, respectively. The simulation
results are discussed in Sect. 7 and finally the conclusion is
given in Sect. 8.
2 Amplifier design trade-offs in CMOS
Different circuit approaches have been reported to increase
the speed and accuracy of gain stages. The most commonly-
used structure is closed loop switched capacitor gain stages.
That needs high gain and bandwidth amplifiers for high
resolution, high speed gain stages. Several types of ampli-
fiers have been presented to increase the DC gain of an
amplifier without degrading its high frequency performance
[36]. Telescopic and folded cascode structures feature high
unity gain bandwidth and DC gain. Although telescopic
amplifiers are fast and have high gain but they need large
voltage headroom whereas folded cascode structures dis-
play large output swing but they generally have medium DC
gain. High gain can also be achieved by cascading multiple
gain stages although it might lead to stability issues [7].
However, the methods still fail to suggest a high gain
amplifier without trading other desirable properties such as
high linearity, output swing, phase margin and bandwidth.
An alternative for achieving desired specifications in a
gain-stage is open loop structures [8, 9]. For instance,
Comparator-based switched-capacitor (CBSC) circuits can
overcome some design challenges of switched capacitor
gain stages [10]. A ZCBC [2] was introduced later in which
dynamic zero-crossing detectors are used instead of com-
parators, provides higher power efficiency and speed.
However, these techniques achieve medium accuracy.
Correlated double sampling (CDS) gain-stage proposed
in [11] is another technique optimizes gain at the cost of
three-phase complex clocking and noise power. Subse-
quently, a parallel correlated double sampling (PCDS)
method was presented in [12] that does not meet the noise
power problem like CDS approach. Both CDS and PCDS
techniques suffer from low output voltage swing since they
are constrained by headroom considerations. To offer a
solution for both gain and swing limitations, the correlated
level shifting (CLS) [13] technique was proposed while
three-phase clocking remains as a major problem.
123
Analog Integr Circ Sig Process
As a whole, gain stages can have either a closed-loop or
open-loop configuration. The open-loop structures such as
ZCBC is generally suffer from poor accuracy, especially
where significant tolerance to process, internal and external
transient variations and total integrated noise are important.
Hence, open loop approaches are useful for lower to
medium resolution. They require calibration and are not
suitable for high resolution applications.
Therefore, most operational amplifiers are used with
feedback (closed-loop operation). A closed loop amplifier
such as switched capacitor, CDS, PCDS and CLS topolo-
gies reduces the gain of the operational amplifier but
greatly increases the stability of the circuit. This method
offers high accuracy in comparison with the open-loop
structure but it exhibits low speed performance.
Another crucial limiting parameter of the closed loop
amplifiers is the slew rate that plays an important role in
the settling behavior of amplifiers. Slew rate of closed loop
amplifiers cause the settling time to increase for large input
variations.
3 Proposed structure
In order to achieve high speed and accuracy, we operate a
closed loop amplifier (CLA) together with an open loop
amplifier (OLA) in the proposed architecture. Concurrent
operation of the two amplifiers is illustrated schematically
in Fig. 1(a). The input signal is simultaneously amplified
by both CLA and OLA until the output voltage reaches its
final value. At the instance, a control signal disconnects
OLA from the output while CLA improves the accuracy of
the output voltage. The control signal is generated by a
comparator that receives input signals from the amplifier
input and its output voltage divided by the amplifier gain
(Vout/n). Figure 1(b) illustrates the timing diagram of the
gain stage. When control switch is on, output voltage set-
tles to its final value with an error that is mainly caused by
the open loop amplifier. CLA diminishes the voltage error
while OLA is switched off. It should be noted that OLA has
to operate faster than the CLA to improve the settling time.
CLA is a switched capacitor gain stage that consists of a
p-type folded cascode amplifier and the switching network.
A ZCBC is employed to implement OLA in the proposed
structure. The open loop nature of ZCBC makes it a suit-
able option for open loop configuration. Figure 2 shows the
proposed gain stage for the total gain of n.
In order to clarify the operation of gain stage, lets
assume that input voltage is positive. For positive values,
output of the second comparator (Comp2) is set to low state
that turns off the related current sources (In) until the next
amplification phase. Therefore, the dashed section of Fig. 2
does not contribute in amplification process for positive
Analog Integr Circ Sig Process

signals. As it is demonstrated in Fig. 1(b), amplifier oper-

+
ates in two phases, sampling phase (u1) and amplification
Vin CLA
-
phase (u2). Input signal is sampled by capacitor Ci in u1.
Vout
At the beginning of the amplification phase (u2) output of
the first comparator (Comp1) is set to high. Hence, the
+ CL
OLA
current source of ZCBC and CLA begin to charge the
- output capacitance to the final value (Vfinal = n 9 Vin),
simultaneously. Since ZCB comparator compares the input
voltage with output voltage divided by the amplifier gain
Vout/n Comparator (Vout/n), as soon as the value reaches nVin, the output state
(a) of comparator changes. Consequently, the current sources
(Ip) switch off. Afterward CLA continues to improve the
CLA
&
accuracy of output as illustrated in Fig. 1(b).
Vout Input OLA CLA For negative inputs, ZCBC should discharge the output
sampling amplification amplification
capacitors as it charges them for positive outputs. Hence
another comparator and pair of current sources (Ip) are
Vfinal
designed in this topology to improve the speed for both
positive and negative output values.
It is worth to note that ZCBC does not impose any
constraints on the gain stage stability due to its open loop
t
nature and only the stability of SC amplifier has to be
Sampling Amplification considered in design process.
Phase 1 Phase 2
Output capacitor of the amplifier is implemented as
(b)  
series combination of n  1Cx and Cx Cout n1 n

Cx
Fig. 1 a Basic concept of the proposed structure, b timing diagram of
the gain stage to generate Vout/n for applying to the comparator input. In

Vdd

In VC1

1
CM Vin1
Cf VC2 Cx 1+
2 Ip
1 2+
CM VC1
1 Ci Vout/n Comp1
(n-1)Cx 2-
Vin1
Out+ Vin2 1-
1 Amplifier CM
1
Vin2
Out- 1+
Vin2 Vdd
(n-1)Cx 2+
2 Ci VC2
VC2 Vout/n Comp2
CM 1 Ip 2-

Cf Cx Vin1 1-
CM
1 VC1
In
V1 V2 0 Vc 1
In comparators:
V1 V2 0 Vc 0
C LA O LA
Fig. 2 The proposed gain stage for the total gain of n

123
 Analog Integr Circ Sig Process

fact division is done by output capacitor. To set the DC

bias, capacitors are paralleled with large resistors.

4 Building blocks

4.1 CLA

The closed loop configuration consists of a folded cascode

amplifier with a small positive feedback [14] as shown in
Fig. 3 (common mode feedback (CMF) [15] and bias cir-
cuit [16] are not shown for simplicity).
Fig. 4 Comparator circuit used in the ZCBC
A PMOS differential pair at the input stage is designed
to achieve high gain with maximum linearity. Design
However, using ZCBC as an OLA does not have a
parameters including common mode range, output swing
considerable loading effect on the output capacitance and
and relative low power consumption are taken into con-
resistance of CLA when it turns off.
sideration for the folded cascode amplifier.
The comparator used in the proposed ZCBC is depicted
in Fig. 4. It is specifically designed for the presented
4.2 OLA
architecture. The current source of ZCBC is disconnected
when the output voltage reaches the vicinity of its final
A ZCBC is suggested as an open loop amplifier due to its
value. Since the ZCBC could degrade the accuracy of the
superior power and area efficiency [2].
gain stage, it should not be activated again in each build up
ZCBC suffers from the finite delay in zero cross detector
cycle after it is disabled. The comparator used in ZCBC
that causes an overshoot in the output which degrades the
should not change its output logic after the output becomes
accuracy of amplification. Increasing the current source
zero. Hence, this paper describes a particular design of
values leads to faster output capacitance charge and dis-
comparator in which a simple differential preamplifier
charge, which increases the speed of ZCBC. However,
stage is followed by a dynamic threshold detector latch. In
raised current values enlarge the amount of overshoot,
each cycle, output of the dynamic threshold detector latch
assuming a constant delay for comparator. Hence, achiev-
is set to 1, prior to the beginning of charge transfer phase
ing high resolution amplification at high speed is the major
by a short preset signal, Ckr.  The ramp input voltage
design challenge of ZCBCs. Moreover, the overall accu-
racy is degraded by all signal-dependent effects in com- reaches the threshold voltage of NMOS transistors in the
parator time-delay and current source. latch structure and Vc drops rapidly. It remains zero until
the next cycle. Output signal is used to turn off the current
sources and the PMOS transistor (M1) to reduce power
consumption.

MCMF1 Mf0 M0 MCMF2 5 Settling time consideration

M3 M4

Vctrl
Amplifier settling time is a crucial factor in data acquisition
M5 M6
from CMF systems, particularly for high precision applications. To
Block
have an accurate data acquisition, the output of an amplifier
Out+ Out-
Mf1 Vi+ M1 M2 Vi- Mf2 must settle within a certain error level in a certain time
Cl Cl interval, which is defined by the system sampling rate.
Therefore, it is the main factor that specifies the data
transfer rate of the A/D for a given accuracy.
In closed loop amplifiers, two distinctive settling regions
M7 M8
cas1 cas2 appear in response to large signal input voltages. The first
M9 M10
region is called slew time in which the amplifier operates in
its non-linear mode. The slewing period is generally
defined by the available input stage current to charge the
Fig. 3 Folded cacode amplifier used in the CLA
load capacitor. The second part starts after the slew limited

123
Analog Integr Circ Sig Process

period when the output of amplifier is within a close range
of its final value. During this time the circuit operates in a
quasi-linear mode.
Slew rate limitation due to the non-linear behavior of
differential stage for large input voltages is the main speed
degrading factor. Although increasing the tail current of
input differential stage reduces the slew time but it
increases power consumption and occupied area.
In the proposed scheme, OLA charges the output
capacitance with a relatively large current during the
slewing time of closed loop amplifier. Consequently,
slewing does not appear when the output settles to its final
value.
Figure 5 illustrates a simplified model of conventional
closed loop amplifiers that we use to elaborate on settling
behavior of the proposed circuit. gm represents the
transconductance of amplifier.
Assuming that the output value changes from 0 to Vref,
the settling time of the output for N bit resolution is
obtained as:
tsettling;cl tslew texp
where tslew is the slewing time and texp is the time interval
that output voltage is exponentially achieves its final value.
Hence, tsettling, cl can be calculated as [8]:
Vfinal  Vslew
tsettling;cl tslew s  ln
Vref =2N
where Vslew is the output voltage at tslew. While tslew and s
are [8]:

CI CP CF
tslew Vi;i  Vi;lin 
CF
CL CF kCI CP
 (In,p), decreases the settling time of ZCB. However, it
Isource
1 cI cP cF
s   cL cF kcI cP  4
gm cF
where Vi,i is the initial voltage of Vi and Vi,lin corresponds
to the input voltage in which the MOS amplifier operates in
its linear region and the maximum output current is limited
to Isource.
In the simplified form, Eq. 1 can be determined as:
 
Vref
tsettling;cl s:N: ln 2 tslew  s  ln 5
Vfinal  Vslew
Now, lets consider the settling behavior of the proposed
structure. The time needed for output signal to settle to its
final value with N bit resolution, tsettling, consists of two
parts, following the timing diagram shown in Fig. 1(b):
tsettling tZCB tcl 6
where tZCB is the time interval that ZCBC and the closed
loop amplifier operate simultaneously and tcl is the time in
which the closed loop structure improves the accuracy of
the output voltage. The open loop amplifier, ZCBC, pro-
vides the main part of load capacitance (CL) charge during
tZCB, using the current sources (In,p). Throughout this per-
iod, the load capacitance is approximately charged in a
linear mode [2].
1 Vfinal
tZCB In;p 7
CL
After this period, output signal reaches to its final value
with an error introduced by ZCB comparators finite delay.
The voltage error can be determined by:
2
In;p
VeZCB tDcomp  8
CL
where tD-comp is the time delay of comparator. Equation 8
suggests that Ve-ZCB is proportional to tD-comp, which can be
mitigated by adjusting the comparator design parameters.
3 According to Eqs. 7 and 8, increasing the current value
causes an increase in the voltage error that can be cancelled
by the closed loop of the proposed architecture. Hence,
although increasing In,p improves tZCB, it degrades tcl.
Therefore, to minimize the total settling time, an optimum
In,p should be obtained.
After ZCB circuit is disconnected, the output voltage is:

Vout t Vfinal VeZCB  et  tZCB =s 9

CF where s is the time constant of the first pole in the closed
loop. In order to achieve N bit accuracy, the minimum
CI settling time needed for the closed loop to cancel the
Vi
Vinput introduced error is obtained as:
CP Vfinal
g mVi Vout VeZCB  etcl=s 10
2N
CL
Vfinal
tcl s  N  ln 2  s  ln 11
VeZCB
Equations 6 and 11 lead to:
Fig. 5 A simple model for the closed loop amplifier

123

Fig. 6 Step response of the proposed amplifier for a 6 bit, b 8 bit, c 10 bit resolution in comparison with the conventional closed loop amplifier
Fig. 7 Maximum settling time of proposed and conventional gain
stage for different resolutions in process corners
 
Vfinal
tsettling s  N  ln 2  s  ln  tZCB
VeZCB
From Eqs. 5 and 12, settling time improvement of the
proposed amplifier can be studied. According to Eq. 5
settling time of a closed loop amplifier is expressed in two
terms. For low swing inputs, the second term is zero
because output voltage achieves its final value exponen-
tially and there is no slewing. Though for large input
swings the second term is a positive value and increasing
the input swing translates to increasing the second term and
consequently the settling time. In Eq. 12 settling time is
lower than exponential settling by proper designed circuits
explained beforechoosing a proper value for In,p and a
well-designed comparator for ZCBC. It should be consid-
ered that as the input swing reduces the second term
123
Analog Integr Circ Sig Process
decreases and consequently the improvement is less for
small signals. In total, a good design of the proposed gain
stage leads to a considerable improvement in the settling
time.
6 Power consumption consideration
As mentioned earlier, total power consumption of an ana-
log circuit is another significant design issue. The majority
of circuit design techniques employed in amplifiers to
decrease the settling time, suffer from large amount of
power consumption. For instance, to reduce the settling
time of conventional closed loop by the factor of two, the
drawing current has to be doubled. This improvement
could be achieved in the presented method, by only adding
a current source which consumes power during only a
small fraction of settling time. Hence, the corresponding
settling time is improved with the same ratio by a negli-
gible increase in the power consumption. Therefore, for a
12
desired settling time, the proposed technique has high
power efficiency compared to the conventional closed loop
amplifier.
7 Simulation results
To verify the functionality of the proposed technique, the
gain stage is designed and simulated in a standard 1.8 V
0.18 lm CMOS technology process by HSPICE software
using level 49 parameters (BSIM3v3) at 25 C (room
temperature). The single ended load of amplifier is a 1 pF
capacitor. The gain is set to 4 by selecting Ci = 1 and
Cf = 4 pF. Figure 6 shows the step response of a gain
Analog Integr Circ Sig Process

Table 1 Performance
Parameters This work [15] [17] [18] [19] [20] [21]
specifications comparison of the
proposed gain stage Technology 0.18 lm 0.35 lm 0.18 lm 0.18 lm 90 nm 0.18 lm 65 nm
Power supply (V) 1.8 3.3 1.8 1.8 1.2 1.8 1
Cload (pF) 1 0.3 0.5 2 0.3 1 1
Power (mW) 9.3 6.4 12.5 88 20 5 1.6
Normalized power (mW)a 9.3 1.79 12.5 88 60 5 7.98
GBW (GHz) 0.48 1.1 1.44 2.56 1.2 0.45
Settling time (ns)b 1.65 5.52 2.43 1.86 1.04 2.22 5.94
Normalized settling time (ns)c 1.65 18.4 4.86 0.93 3.48 2.22 5.94
a
Normalized to the 0.18 lm process with a 1.8 V supply as the following equation:
0:18 lm
PN Power1:8
VDD Process minimum gate length
b
For the references that the settling time is not reported, it is calculated according to the following
equation: t = sNln2 where N is the resolution and s is the time constant of the amplifier and is equal to
Gain
UGBW
c
Normalized to a 2 pF load capacitance as the following equation: ts;N ts  C1pF
load

stage based on the proposed method in comparison with a
simple closed loop structure with folded cascode amplifier
for a high (800 mV) and a low (200 mV) output amplitude.
Simulation results exhibit that the settling time of the
presented method is considerably shorter than the settling
time of conventional closed loop amplifier. From Fig. 6(a),
the settling time has been reduced by about 3 ns compared
with that of the simple closed loop with 6 bit gain accuracy.
The open loop amplifier, added to the conventional closed
loop amplifier, consumes only 0.63 mW while the power
consumption of CLA is 8.68 mW for 6 bit gain accuracy.
Since OLA draws no static current to charge the output
capacitor, its power consumption is negligible compared to
the total power of the amplifier. The similar comparative
simulation results have been illustrated in Fig. 6(b, c) for the
gain accuracy of 8 and 10 bit, respectively.
In the proposed gain stage, the improvement is basically
due to the fact that the output signal is not limited by the
slewing matter and the exponential settling of the system
when it is far from its final value. It gets near to its final
value in a linear mode with a rate much higher than
exponential and slewing form. In the next phase, when the
output of amplifier is within close range of its final value, it
settles exponentially by CLA with a high accuracy.
Moreover, the effects of process and device variations
are studied through corner analysis to characterize the gain
stage performance in Fig. 7. The circuit is simulated in
slow, typical and fast parameters for the given process.
Figure 7 illustrates the maximum settling time of the pro-
posed gain stage and the conventional CLA for the gain
accuracy of 6, 8 and 10 bits in various process corners.
Finally, the performance specifications of the designed
gain stage are compared with the similar previous works in
Table 1. In order to better show the advantages of the
proposed approach, the power consumption and the settling
time of all the studies are normalized to the 0.18 lm pro-
cess with a 1.8 V supply and the load capacitance of 1 pF.
8 Conclusions
A new structure for the gain stage is presented based on a
unique combination of closed loop and open loop ampli-
fiers in which the settling time, accuracy and power con-
sumption are significantly improved. The improvement is
predominantly due to the fact that the output gets near to its
final value linearly with a rate much higher than expo-
nential and slewing form. In addition, the structure
achieves high accuracy since the voltage error is reduced
by the closed loop amplifier.
The estimated improvements are confirmed by rigorous
HSPICE simulations using a switched capacitor structure
based on a p-type folded cascode and a zero cross based
circuit as corresponding open loop and closed loop ampli-
fiers. Since output capacitance is charged directly by a
current source, the settling behavior of presented structure is
enhanced while the accuracy of the output signal is deter-
mined by the closed loop amplifier. All the results are also
compared with a single conventional closed loop amplifier
which reveals the efficiency of the presented gain stage.
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and folded cascode used in ADC. World Academy of Science band integrated filter design,
Engineering and Technology, 6(7), 284286. and nonlinearity analysis and
19. Berntsen, ., Wulff, C., & Ytterdal, T. (2005). High speed, high improvement in analog circuits.
gain OTA in a digital 90 nm CMOS technology. In Proceedings He is currently with Electrical
of the 23th NORCHIP conference (pp. 99102). Oulu. Engineering Department and Microelectronics Research Laboratory
20. Kouzehkanan, M. K., Dadashi, A., Teymouri, M., Masoumi, S. in Urmia University, Urmia, Iran. He holds several US and Japanese
(2012). Fast-settling gain stage using replica amplification for patents.
high performance pipeline ADCs. In Proceedings of the 19th

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Analog Integr Circ Sig Process

Abdollah Khoei was born in

Urmia, Iran. He received B.Sc.,
M.Sc. and Ph.D. degrees in
Electrical Engineering from
North Dakota State University,
USA, in 1982, 1985, 1989,
respectively. His research inter-
ests are analog and digital inte-
grated circuit design for fuzzy
and neural network applications,
fuzzy based industrial electron-
ics, and DCDC converters for
portable applications. He is
currently with Electrical Engi-
neering Department and Micro-
electronics Research Laboratory in Urmia University, Urmia, Iran.

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