Robust Phase Locked Loops Optimized for DSP
Implementation in Power Quality Applications
Francisco D. Freijedo, Jesus Doval-Gandoy, Oscar Lopez and Jacobo Cabaleiro
Department of Electronic Technology, University of Vigo,
ETSEI, Campus Universitario de Vigo, 36200, Spain.
Email:{fdfrei,jdoval,olopez}@uvigo.es
AbstractPhase locked loop (PLL) algorithms for grid syn-
chronization are a very important part of the control in most
of the grid-connected power converters applications. The perfor-
mance of the PLL should not be much affected under distorted
grid conditions: the presence of harmonics, unbalance, noise, etc
in the inputs should not distort PLL measurements. This paper
presents an optimized design approach of PLLs, both for single-
phase and three-phase systems.
The loop lter of the PLL sets its dynamic response; the
loop lter should be tuned in order to achieve a correct trade-
off between transient response and harmonics/noise cancellation.
This paper proposes the use of notch lters inside the loop in
order to optimize the PLL performance; this approach is suitable
both for single-phase and three-phase PLLs.
Another novel interesting proposal of this paper is the im-
plementation of the Digitally Controlled Oscillator (DCO): the
digital model of a sinusoidal oscillator is implemented, instead
trigonometric functions. This reduces the needed digital resources
without reducing the performance. This approach is specially
useful for DSP-based control of power converters.
The proposed PLLs have been implemented and tested in a
xed point DSP (TI TMS320LF2407) and also in a oating point
microprocessor (PowerPC of the dSpace DS1103). The systems
have been tested with different distorted inputs in order to check
the validity of the design approaches and good results have been
obtained.
I. I NTRODUCTION
Synchronization is one of the most important issues in
the control of power electronics equipment connected to the
grid. Most of the power converters control algorithms use the
phase measurement of the grid fundamental component. The
quicker and more accurate this measurement is, the better the
generation of reference signals results, and therefore a more
efcient the control is achieved. Examples of applications
where synchronization is essential are found in the elds of
active power lters [1], [2], power factor control [3], [4],
wind power generation [5], Flexible AC transmission systems
(FACTS) [6], etc.
Phase Locked Loops (PLLs) tracking the phase of the fun-
damental component of grid voltages are the most widespread
synchronization algorithms both for single-phase and three-
phase systems [7][12]. PLLs are implemented inside a higher
level control; they should be designed with the goals of having
a good performance and not being excessively resource-
consuming. This paper presents a PLL design method for an
optimized digital implementation; the approach is made both
for single-phase and three-phase systems.
k,((( 
PLLs with good tradeoff between transient response and
harmonics/noise cancellation are presented. An interesting
novelty of this paper, is the use of notch lters inside the loop
to cancel second harmonic components. As shown below, this
proposal is very useful both for single-phase and three-phase
PLLs. Single-phase PLLs generate a high second harmonic
in the phase-detector output (multiplier) [9], [10]; the notch
lter cancels it in an effective way. The problem of second
harmonic generation in three-phase PLLs appears when the
input voltages are unbalanced [8]. The notch lter frequency
response should be taken into account; the open loop fre-
quency response should have a cut-off frequency smaller than
the notch frequency. The use of a notch lter inside the loop
is compared with the use of moving average FIR lters inside
the loop proposed in different works [9], [10], [13].
Another interesting proposal of this paper is the implemen-
tation of the digital oscillator without implementing explicitly
trigonometric functions: the input of the Digitally Controlled
Oscillator (DCO) the PLL output frequency; a digital oscillator
derived from an analog RC one is used [14]. The oscillation
conditions are imposed by means of the Barkhausen criteria.
Under the point of view of xed point digital implementation
(DSP, FPGA, ...) this is a good solution in terms of resource
consumption and design simplicity.
The performance of the proposed PLLs is proved with
experimental results. The systems have been implemented into
a xed point DSP and in oating point microprocessor. For
the experimental tests, some different input waves have been
programed in the inputs. Tests include input waves with noise,
unbalance, high harmonics and notching.
II. PLL BASICS : T HE LPLL
A PLL is a non-linear circuit which synchronizes its output
signal (vo ) with a reference or input signal (vi ) in frequency
as well as in phase.
The PLL scheme is composed by the three basic functional
blocks shown in Fig. 1(a): the phase detector (PD), the loop
lter (LF) and the voltage controlled oscillator (VCO). Fig
1(b) shows the model of the linear PLL (LPLL) avalaible as
a purely analog device since 1965 [15]. The VCO generates a
signal of frequency o , from its nominal frequency (n ) and
the correction voltage (vc ). When a PI lter is used as LF,
the LPLL achieves zero steady-state error even after a phase
step or a frequency step in the reference input [15].
 The input signal of equation (1) is considered to analyze vi ve
Phase Loop
the LPLL dynamics: Detector Filter
vo
Voltage
vi = 1 sin(i t + i ) + f (3i , 5i , 7i , ...) p.u. (1) Controlled
vc
Oscillator
As shown, p.u. units are employed; the fundamental Zo Zn  Kvc 
component amplitude should be normalized to 1 p.u. and odd
harmonic components are also considered. The wave at the (a) Block diagram of a PLL.
PD output is:
PD VCO
vi ( p.u.) Loop Filter
PI
X + + Zn
1 Filter
vi cos(o t + o ) = sin(i t + i o t o )+

  2
F eedback wave (2) Zo t  T o S
1
cos(u) Zo
+ sin(i t + i + o t + o ) + f (2i , 4i , 6i , ...)
2 sin(u) 
S
The LPLL can be linearized, assuming that the PLL is
(b) Linear PLL (LPLL).
locked in steady-state ; under such a situation i = o and
i 1 [15], so: PD Te
VCO (DCO)
Zi t  T i
+-
Loop + + Zn
Filter
1
vi cos(o t + o ) sin(i o ) +

2   Zo t  T o S
Zo
1
i o =e
(3) S

+ sin(2i t + 2i ) + f (2i , 4i , 6i , ...)

2  
 
Other harmonics (c) Linear model of a PLL.
Generated second harmonic

Equation (3) shows that in steady-state the wave has a small
dc signal with the phase error information (e ), a high second
harmonic and other even harmonic components. The LF is a
low pass lter, which should be tuned to control e and cancel
harmonic components so the LPLL is equivalent to the linear
system depicted in Fig. 1(c).
The open loop transfer function of the PLL linear model
should be analyzed in order to study its dynamics. The
frequency response gives information about the attenuation
at harmonic components. The stability margins should also
be checked. It is clear from Fig. 1(c) that the LPLL dynamics
depends on the LF; the main feature of the LF is its bandwidth
(BW). High BW lters give rise to faster PLLs, but their
outputs are more affected by noise and harmonics. Low BW
PLLs are slower but its outputs are better ltered. However, as
proved in [15], a very low BW PLL behaves badly in the case
of noisy signals because the PLL gets unlocked. Therefore,
there is a tradeoff between speed and harmonics/noise ltering.
As said, the PLL should be tuned in p.u. units being 1 p.u.
the nominal amplitude. PLLs are non-linear systems and, when
the input amplitude is shifted from nominal (sag/swell) the
system works in a different point from the one what it has been
tuned [9], [10]. Therefore, it is recommended to congure the
PLL with wide stability margins, specially on systems working
with grid faults.
III. D IGITAL D ESIGN OF PLL S
As said, PLLs have been widely implemented with analog
ICs. However, the nowadays trend is the use of modern digital
devices such as DSPs, FPGAs, Micros, etc, since digital
Fig. 1. Basic conceptual models of PLLs.
devices offer more exibility in the design of the control
of power converters. In the next subsections, some different
techniques for taking advantage of digital implementation
are presented. The approach is presented both for a single-
phase PLL and for the most popular three-phase PLL, the
dq-PLL rstly proposed in [16]. The study is presented for a
sampling frequency (fs ) of 10 kHz; the extension to other fs
is immediate. The employed n has been 250 rad/s.
A. Notch Filters inside the Loop
Fig. 2 shows the proposed single-phase PLL; as the system
is digital, a DCO block replaces the VCO one.
As seen in eqs. (2) and (3) a very high second harmonic is
generated in the multiplier of the PD. On the other hand, it is
important to note that the nominal grid frequency is very small
compared with typical frequencies of other PLL applications
such as radio communications. This complicates the design of
single-phase PLL because, if only a PI lter is used, the BW
should be reduced very much to have a good second harmonic
cancellation. This has led to develop more complex structures,
e.g. [9], [10], [17]. A simpler technique is proposed in this
paper: the use of a notch lter whose notch frequency is twice
the nominal grid frequency; this notch lter is not be very
selective to work correctly for a wide range of frequencies.
The linearized process of this PLL is the same that the LPLL
one; the open loop transfer function of the equivalent linear
PLL is:

k,((( 
 PD DCO PD
vi ( p.u.) Loop Filter
va ( p.u.)
X Notch 2nd
PI + + Zn vd
Filter
vb ( p.u.)
DCO
cos(u) Zo t  T o S
Zo [Tdq] vq Loop
Zn
vc ( p.u.) + +

sin(u)
S

Filter

Zo t  T o S
Zo
Fig. 2. Block diagram of the proposed single-phase PLL. S


GM = 15.1 dB (at 86.2 Hz) , PM = 45 deg (at 47.1 Hz)

50
Fig. 4. Block diagram of the dq-PLL.
0
Magnitude (dB)

-50
1

0.8
-100

0.6

Gain
-150
0.4
-200
0
0.2
-45
0 1
Phase (deg)

2
-90 10 10
Frequency (Hz) Notch filter.
-135
FIR filter.

-180
50

Phase (deg)
-225
0 1 2 3 4 0
10 10 10 10 10
Frequency (Hz) -50

-100
Fig. 3. Open loop bode diagram of H(z) (in Hz).
-150
1 2
10 10
Frequency (Hz)

Fig. 5. Frequency response of notch lter (fnotch = 100 Hz) and moving
250z 247.8 0.972z 2 1.9402z + 0.972 0.0001 average FIR lter (f1F IR = 100 Hz).
H(z) = 2

z1 z 1.9402z + 0.944 z1

 
 
 
P I f ilter N otch f ilter DCO
(4) Again, if the system is considered locked in steady-state the
Fig. 3 shows the open loop frequency response of the linear model is suitable for studying the dynamics [7].
single-phase PLL. As shown, the tradeoff between BW and The dq-PLL does not generate a second harmonic when
harmonics/noise cancellation is very optimized: the problem- the input signals are balanced; this is the main reason of the
atic second harmonic is totally canceled with a high BW dq-PLL success [9]. However, when the set of input voltages
LF. Furthermore, the stability margins, gain margin (GM) and is unbalanced, and therefore negative-sequence component is
phase margin (PM), are wide enough. present, a second harmonic ripple appears in vd and vq [8].
On the other hand, the dq-PLL algorithm is the most popular The presence of other distortion factors such as harmonics,
synchronization algorithm for three-phase systems. The main noise, notching, etc should be taken into account [7], [11].
aim of the dq-PLL is to synchronize with the fundamental Therefore, the LF of equation (4) is also a good choice for
positive-sequence of the input voltages. Fig. 4 shows the block the dq-PLL, specially when the utility voltages are unbalanced
diagram of the dq-PLL; the Park transformation (eqs. (5) and and distorted.
(6)) is obtained from the DCO signals and acts as phase The main advantage of the notch lter with respect to
detector. moving average FIR lters inside the loop [9], [10], [13] lies
in the comparative of their phase versus frequency response:
  va
vd even though the FIR lter has better harmonic cancellation, at
= Tdq vb (5) its fundamental frequency (f1F IR ) is 180 deg so the PLL BW
vq
vc must be quite smaller than f1F IR . However, with the notch
lter a cut-off frequency near fnotch can be obtained (Fig. 3).
sin(o t + o ) cos(o t + o )
2 B. DCO implementation by means of an Oscillator Model
Tdq
T
= sin(o t + o 2 3 ) cos(o t + o 2 3 )
3
sin(o t + o + 2 3 )
2
cos(o t + o + 3 ) As shown, the single-phase PLL implement trigonometric
(6) functions to generate the feedback wave (cos(o t + o )) and
The quadrature component (vq ) is controlled within a closed the in-phase wave (sin(o t + o )).
loop so its mean value in steady-state is zero; the direct com- Under the point of view of implementation in a digital
ponent (vd ) average value is the positive-sequence amplitude. device, specially xed point DSPs, this process is quite costly.

k,((( 

0.99
Zo
 0.99
0.99
 0.99
- Zo
Zo
Fig. 6. Block diagram of the digital oscillator.
Pole-Zero Map
400
300
200
Imaginary Axis
100
0 trigonometric functions are not explicitly present. It is impor-
-100
-200
-300
-400
-1 -0.5
Real Axis
Fig. 7. Poles/Zeros map of the oscillator ( in rad/s, continuous model ).
In this paper, a more efcient algorithm is proposed by
means of digitally implementing the model of a RC electronic
oscillator. Fig. 6 depicts the model of the proposed digital
oscillator which generates two unitary orthogonal waves.
Fig.7 shows the closed loop poles of the digital oscillator
for o = n ; of course, in real time operation, the oscil-
lation frequency o is updated in each sample. Following
Barkhausen criteria, this system oscillates at o : from control
theory, this system tends to instability since its poles are on
the imaginary axis; however, as the integrators are saturated,
the signal amplitude can be controlled [14]. The initial values
sin(o t+o ) = 0, cos(o t+o ) = 0.99) are chosen to quickly
achieve the oscillation steady-state.
The output phase (o t + o ) is calculated by means of
integrating o between [, ]. When sin(o t + o ) crosses
zero in the falling edge o t+o is reset to . Another option
is to use the range [0, 2] and reset on the rising edge.
As seen, this diagram is very low resource-consuming. A
small drawback of the oscillator is that the generated waves
sin(n t), cos(n t) are not pure sinusoidal waveforms, due
to the non-linear behavior of the saturation in the integra-
tors. However, the total harmonic distortion (THD) of these
waves is negligible (0.70% when implemented at a sampling
frequency (fs ) of 10 kHz).
The dq-PLL also implements trigonometric functions (Tdq ).
k,(((
cos(Zot  T o ) Vb Vc Va
cos(w1ot+q1o)
Vd
sin(Zot  T o )
sin(w1ot+q1o)
Vq
Reset
S
Zo t  T o
S

Fig. 8. Park transformation from the oscillator signals.
Fig. 8 shows the Tdq matrix calculation from the signals of
Fig. 6.
IV. S IMULATION R ESULTS
Pole : 0 + 314i
Fig. 9 shows a Matlab script which simulates the single-
phase PLL start-up tracking. This script also proves the
simplicity and signicance of the oscillator implementation:
tant to mention that the output of the LF should be saturated
(|o n |max = 128 rad/s). This is implicit in a DSP xed
point implementation.
Pole : 0 - 314i This script is used to show the feasibility of the notch lter
0 0.5 1
to cancel the second harmonic (Fig. IV). To remove the notch
lter from the PLL is only needed to change lines 19 and 20
for ynotch(n+1)=ypd(n+1);.
V. E XPERIMENTAL R ESULTS
A. Single-phase PLL
The single-phase PLL has been implemented in the Tech-
nosoft MSK2407 board containing a TMS320LF2407 xed
point DSP of Texas Instruments; the word length of this DSP
is 16 bits. In the script of Fig. 9 is shown the representation
for each variable in Q format. It is important to comment that
there is a tradeoff in the choice of the ylf pipeline format.
A smaller pipeline (e.g. Q9) gives rise to a system slower
since it saturates easily. However, a bigger pipeline (e.g. Q7)
would give rise to a noticeable lose of performance due to
the truncation after the LF multipliers. Q8 resulted to be the
optimum choice.
Fig. 11(a) shows the steady state phase measurement of the
single-phase PLL when a clean sinusoidal of 51 Hz is at the
input. Fig. 11(b) shows the phase tracking when the real grid
signal is at the input. Fig. 11(c) shows the excellent transient
response of the PLL: after a strong fault such as a voltage sag
from 1 p.u. to 0.5 p.u. and +45 deg phase-jump the PLL re-
tracks in less than a cycle. These results conrm the expected
performance of the system.
B. dq-PLL
The dq-PLL have been implemented in the oating point
PowerPC inside the dSpace DS1103 prototyping platform.
This platform contains a oating point micro PowerPC and
an I/O interface.

 1 clear all;
3
2 Ts=1e-4; % Sampling time (= 1/fs).

Amplitude (p.u.), Phase-angle (rad/s)

3 Tfinal=0.1; % Time for the simulation. 2

4 t=0:Ts:Tfinal; % time vector.

1
5 wn=2*pi*50; % Nominal frequency.
6 Mysin=[0;0]; % Initialize Mysin. 0

7 Mycos=[0;0.99]; % Initialize Mycos.

-1
8 ypd=[0;0]; % Initialize PD output.
9 ylf=[0;0]; % Initialize LF output. -2
Input signal
10 ynotch=[0;0]; % Initialize notch filter output. Mysin
-3
Phase-angle
11 theta=[0;0]; % Initialize phase angle
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
12 % Create INPUT WAVE for SIMULATION Time (s)

13 wu=2*pi*50.3; % Input wave frequency

(a) Single-phase PLL start-up simulation without notch lter (ideal
14 u=sin(wu*t+pi);% Input wave definition input signal).
15 % SIMULATE THE PROCESS
16 for n = 2:Tfinal/Ts % Number ot iterations 3

Amplitude (p.u.), Phase-angle (rad/s)

17 ypd(n+1)=u(n)*Mycos(n); % Phase Detector (Q15)
2
18 % Notch Filter (Q15)
19 ynotch(n+1)=1.94*ynotch(n)-0.944*ynotch(n-1)+... 1
20 0.972*ypd(n+1)-1.94*ypd(n)+0.972*ypd(n-1);
0
21 % Loop Filter Q(8)
22 ylf(n+1)=1*ylf(n)+250*ynotch(n+1)-247.8*ynotch(n); -1
23 % Limit LF according to its Q8 size pipeline
-2
24 ylf(n+1)=max([ylf(n+1) -128]); Input signal
25 ylf(n+1)=min([ylf(n+1) 128]); Mysin
-3 Phase-angle
26 % Update Output frequency (Q6) 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
27 wo=wn+ylf(n+1); Time (s)

28 % Integration process (digital oscillation) (b) Single-phase PLL start-up simulation with notch lter (ideal
29 Mysin(n+1)=Mysin(n)+wo*Ts*(Mycos(n)); %(Q15) input signal).
30 Mycos(n+1)=Mycos(n)-wo*Ts*(Mysin(n)); %(Q15)
31 % Limit the oscillator integrators 3
Amplitude (p.u.), Phase-angle (rad/s)

32 Mysin(n+1)=max([Mysin(n+1) -0.99]); 2
33 Mysin(n+1)=min([Mysin(n+1) 0.99]);
34 Mycos(n+1)=max([Mycos(n+1) -0.99]); 1

35 Mycos(n+1)=min([Mycos(n+1) 0.99]); 0
36 % Update the output phase (Q12)
37 theta(n+1)=theta(n)+wo*Ts; -1

38 % Output phase reset condition

-2 Input signal
39 if Mysin(n)>=0 && Mysin(n+1)<=0 Mysin
Phase-angle
40 theta(n+1)=-pi; -3

41 end 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time (s)
42 end
43 plot(t,u,t,Mysin,t,theta); % Plot experimental results (c) Single-phase PLL start-up simulation with notch lter (highly
harmonic contaminated input signal).
Fig. 9. Matlab Script of the single-phase PLL.
Fig. 10. Simulation results for single-phase PLL (i = 250.3 rad/s).

Fig. 11(d) shows the steady-state phase measurement for

a highly unbalanced (both in amplitude and phase) voltage
system at the inputs of dq-PLL. As expected, the second
harmonic is canceled. Fig. 11(e) shows the good tracking of
the dq-PLL when there is superimposed white noise of 10 kHz
BW and a power spectral density (PSD) of 106 p.u. to the
previous test wave. Fig. 11(f) shows the initial transient of the
dq-PLL under a highly distorted (harmonics and unbalance)
input voltage. The tracking time is about half a cycle. Fig.
11(g) shows the excellent performance of the dq-PLL tracking
an unbalanced voltage system with notches.
VI. C ONCLUSIONS
A novel design approach for PLL implementation has
been presented. This approach is specially suitable for DSP
implementation. The loop lter approach give rise to PLLs
very robust which work very even when the voltage con-
ditions are distorted (harmonics, noise, unbalance, etc). The
implementation of a digital oscillator also allows to made an
optimized DSP implementation without spending very much
resources.
VII. ACKNOWLEDGMENT
This work was supported by the Spanish Ministry of Science
and Technology under project number ENE2006-02930.
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k,((( 
 Zoom
(a) Phase measurement for sinusoidal input (b) Phase measurement for real grid voltage.
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