03-Amplifiers (Mode de Compatibilité)

Master 2nd year Applied Micro & Nano-technologies ESIEE
Master 2nd year Micro-technologies UPEM
Shermila Mostarshedi
Assistant professor Universit Paris-Est Marne-la-Valle
Two-port network
Reflection coefficients :
seen looking toward the load
Z L Z0
L =
Z L + Z0
seen looking toward the source
Z S Z0
S =
Z S + Z0
seen looking toward the port 1
V1
in = +
V1
S 21V1+
V2 = S21V1+ + S 22V2+ = S 21V1+ + S 22LV2 V2 =
1 S 22L
V1 = S11V1+ + S12V2+ = S11V1+ + S12LV2 S 21V1+
V1 = S11V1+ + S12L ( )
1 S 22L
S12 S 21L
in = S11 +
1 S 22L
S12 S 21S
seen looking toward the port 2 out = S 22 +
1 S11S
Chapter 3: Amplifiers 2
PIN PL
Average power delivered to the network:

+ 2
{ }
+
V1 * 1 V1
1
PIN = e V1I1
2
1
2
{ + + *
}
1 + V1
= e (V1 + V1 )( I1 + I1 ) = e(V1 + V1 )(
2
) =
Z0 Z0 2 Z0
2
(1 in )
Z in
V1 = VS
Z in + Z S
V1 = V1+ + V1 = V1+ (1 + in )
VS (1 S )
V1+ =
ZS Z0 1 S 2 (1 S in )
S = Z S = Z0
Z S + Z0 1 + S
Z in Z 0 1 + in
in = Z in = Z 0
Z in + Z 0 1 in
( )
2 2
V 1 S 2
PIN = S 1 in
8Z 0 1 S in 2
Average power delivered to the load:
2 2 2 2
V S 21 (1 L ) 1 S
2
1
PL = e(V2 I 2 ) =
2 2 Z0
1 V2
1 L
2
( ) PL = S
8Z 0 1 S 22L 2 1 S in 2
PAVS PAVN
Power available from source:

The maximum power that can be delivered to the network.
2 2
V 1 S
PAVS = PIN in =S *
= S
8Z 0 (1 S 2 )
Power available from network:

The maximum power that can be delivered to the load.
2 2 2
V S 21 1 S
PAVN = PL * = S
out =L 8Z 0 1 S11S 2 (1 out 2 )
Power gain
PL
Operating power gain: The ratio of power dissipated in the load G=
ZL to the power delivered to the input of the two-port network. PIN
Independent of ZS
PAVN
Available gain: The ratio of the power available from the two-port GA =
network to the power available from the source. PAVS
Independent of ZL
Transducer gain: The ratio of the power delivered to the load to PL

GT =
the power available from the source. PAVS
Power gain expressions
Operating power gain Special case: S=L=0
2
in = S11 S 21
2
1 2 1 L G=
G= S 21 2
1 in
2
1 S 22 L
2
1 S11
out = S 22
2
Available gain S 21
GA = 2
2
1 S 22
1 S 2 1
GA = 2
S 21 2 GT = S 21
2
1 S11S 1 out
Transducer gain Special case: S12=0 (unilateral)

2
1 1 L
2 2 in = S11 GU =
2
S 21
1 S 2 1 L 1 S11
2
1 S 22L
2
GT = S 21
1 S in
2
1 S 22L
2 out = S 22
2
1 S 2 1
or : G AU = S
2 21 2
1 S11S 1 S 22
2 2
1 S 2 1 L 1 S
2
1 L
2
GT = 2
S 21 2 GTU = S 21
2
1 S11S 1 L out 2 2
1 S11S 1 S 22L
Two-port network with matching circuits
A general single-stage amplifier with two matching networks in the input and in
the output to transform the input and output impedance Z0 to the source and
load impedance ZS and ZL.
The over all transducer gain: GT = GS G0GL
2 2
1 S 1 L
GS = 2 G0 = S 21
2
GL = 2
1 S in 1 S 22 L
And in case of a unilateral transistor:

2 2
1 S 1 L
GS = 2 G0 = S 21
2
GL = 2
1 S11S 1 S 22 L
Example
An RF amplifier has the following S parameters. The input side of the amplifier is
connected to a voltage source with VS=5 V and source impedance ZS=40 . The output is
utilized to drive an antenna which has an impedance of ZL=73 . Assuming that the S
parameters of the amplifier are measured with reference to a Z0=50 characteristic
impedance, find different power and gain values.
S11=0.370 S12=0.2 10
S21=3.585 S22=0.4 45
Stability
Oscillations happen if the input or output impedance has a negative real part.
Z in / out Z 0 R + jX Z 0 ( R + Z 0 )2 + X 2
in / out = = = >1
Z in / out + Z 0 R + jX + Z 0 (R Z0 ) + X
2 2
Two types of stability:
Unconditional: in < 1 and out < 1 for all passive source and load impedances
Conditional: in < 1 and out < 1 for a certain range of source and load impedances
Stability conditions
General A Unilateral (S12=0)
S12 S 21L
in = S11 + <1 in = S11 < 1
1 S 22L
S12 S 21S
out = S 22 + <1 out = S 22 < 1
1 S11S
Stability circles (1)
S12 S 21L
in = S11 + =1 S11 (1 S 22L ) + S12 S 21L = 1 S 22L
1 S 22L
We define: = S11S 22 S12 S 21 S11 L = 1 S 22L
( S 22 S11
* *
) S12 S 21 Circle for
L 2 2
= 2 2
S 22 S 22 output (load) stability
center radius
Summary
Circle for Circle for
output (load) stability where |in|=1 input (source) stability where |out|=1
( S 22 S11
* *
) ( S11 S 22
* *
)
CL = 2 2
CS = 2 2
S 22 S11
S12 S 21 S12 S 21
RL= 2 2
RS = 2 2
S 22 S11
The circles designates the points where |in| or |out| are equal 1.
One side of the circle contains points for which |in| or |out| >1 and so is the
unstable region.
Another side of the circle contains points for which |in| or |out|<1 and so is the
stable region.
If the device is unconditionally stable, If the device is conditionally stable, there

the stability circles would be completely would be a limited intersection between the
outside the Smith chart, or enclose it circles and the Smith chart.
entirely.
A simple test point to find the stable region would be the center of the Smith.
For the output stability circle

Origin of the Smith chart zL = 1 L =0 |in|= |S11|
If |S11|<1, the center is part of the stable region.
If |S11|>1, the center is external to the stable region.
For the input stability circle

Origin of the Smith chart zS = 1 S =0 |out|= |S22|
If |S22|<1, the center is part of the stable region.
If |S22|>1, the center is external to the stable region.
Example: Find the stability domain for each configuration.

rL
|out|=1
rS |CL|
|in|=1
|CS|
Smith chart |S22|<1 Smith chart |S11|>1
Unconditional stability test
K- test
2 2 2
1 S11 S 22 +
K= >1 and = S11S22 S12 S 21 < 1
2 S12 S 21
If both conditions are simultaneously satisfied, the device is unconditionally stable

and the stability circles do not need to be traced.
If not, the stability circles must be used to determine the stable region.
The K- test cannot be used to compare the relative stability of two devices.
test
For L plane For S plane
2
1 S11
2 1 S 22
= >1 = >1
S 22 S11
*
+ S12 S 21 S11 S 22
*
+ S12 S 21
The physical meaning is the minimum distance from the origin of the Smith chart to
the stability circle.
The unique condition to verify unconditional stability.
Larger values of imply greater stability.
Design for maximum gain (1)
Maximum power transfer from the input matching network to the transistor:
S12 S21L
in = S* = S11 +
1 S22 L
Maximum power transfer from the transistor to the output matching network:
S12 S21S
out = L* = S22 +
1 S11S
2
B1 B12 4 C1
S =
2C1 2 2
B1 = 1 + S11 S 22
2
C1 = S11 S 22
*
2 where:
B2 B22 4 C2 2 2 2 C2 = S 22 S11
*
L = B2 = 1 + S 22 S11
2C2
Design for maximum gain (2)
There exists a solution if: 2
B12 4 C1 > 0
2
B22 4 C2 > 0
With some mathematics, we can prove that this is equivalent to K>1.
Unconditionally stable transistor can always be designed for maximum gain.

Potentially stable transistor can be conjugately matched if K>1 and ||<1.
Maximum transducer gain:

2
1 S 2 1
GT max = S 21
In general case (in = S* and out = L* ) 1 S11S
2
1 L
2
or : 2
1 2 1 L
GT max = 2
S 21 2
1 S 1 S 22 L
In unilateral case (in = S11 = S* and out = S 22 = L* )
1 2 1
GT max = 2
S 21 2
1 S11 1 S 22
Unilateral condition in practical cases
|S12| small Transistor is considered to be unilateral (|S12|=0).
The error introduced into transducer gain caused by this approximation is

GT/GTU. This error is bounded by:
1 GT 1
< <
(1 + U ) 2 GTU (1 U ) 2
S11 S12 S 21 S 22
where U is defined as the unilateral figure of merit: U = 2 2
(1 S11 )(1 S 22 )
This is considered to be a worst case error and practically the actual difference
often is much smaller.
Input and output reflection coefficients in a unilateral case:

S S S S
in = S11 + 12 21 L = S11 out = S 22 + 12 21 S = S 22
1 S 22L 1 S11S
Constant gain circles unilateral design (1)
Gain expressions in general case:
2 2
1 S 1 L
GS = 2
GL = 2
1 S in 1 S 22L
Gain expressions in unilateral case: ( in = S11 and out = S 22 )

2 2
1 S 1 L
GS = 2
GL = 2
1 S S11 1 S 22L
Maximum gain expression in unilateral case: ( S = S11
* and
L = S 22
* )
1 1
GSmax = 2
GLmax = 2
1 S11 1 S 22
Normalized gain factors in unilateral case:

2 2
GS 1 S 2 GL 1 L 2
gs = = (1 S11 ) gl = = (1 S 22 )
GSmax 1 S S11 2 GLmax 1 L S 22 2
Constant gain circles unilateral design (2)
For fixed values of gs and gl:
2 2
*
g s S11 1 g s (1 S11 ) *
gl S 22 1 gl (1 S 22 )
S 2
= 2
L 2
= 2
1 (1 g s ) S11 1 (1 g s ) S11 1 (1 gl ) S 22 1 (1 gl ) S 22
center radius center radius
Circle for Circle for

input (source) constant gain gs output (load) constant gain gl
* *
g s S11 gl S 22
CS = 2
CL = 2
1 (1 g s ) S11 1 (1 gl ) S 22
2 2
1 g s (1 S11 ) 1 gl (1 S 22 )
RS = 2
RL = 2
1 (1 g s ) S11 1 (1 gl ) S 22
For the maximum gain (gs = 1 or gl = 1), the radius of the circle would be zero
and the circle reduces to a point (S = S11* or L = S22*).
Example
A MESFET operated at 5.7 GHz has the following S parameters :
S11=0.560 S12=0.020
S21=6.5115 S22=0.635
Determine if the transistor is unconditionally stable. Using the constant gain circle
concept, design a 18 dB single stage amplifier which presents an optimal source reflection
coefficient.
Low-Noise Amplifier (LNA)
Generally it is not possible to have both minimum noise figure and maximum
power gain for an amplifier. Some compromises must be made.
Noise figure of a two-port amplifier:

RN 2
F = Fmin + YS Yopt
GS
Fmin: minimum noise figure of transistor obtained with YS = Yopt (Given or measured)
YS: source admittance YS = 1/ZS = GS + j BS
Yopt: optimum source admittance giving the minimum noise figure (Fmin) (Given or measured)
RN: equivalent noise resistant of transistor (Given or measured)
GS : real part of the source admittance (YS)
We note that the noise figure only involves the source impedance (or S) and is
totally independent from the load impedance (or L)
Noise figure circles (1)
Reflection coefficients related to YS and Yopt
2
1 1 S 2 4 S opt
YS = YS Yopt =
Z 0 1 + S Z 02 1 + S 2 1 + opt 2
1 1 opt 1 1 S
2
Yopt = G = e(YS ) =
Z 0 1 + opt 2
Z 0 1 + S
2
4 RN S opt
F = Fmin +
Z 0 (1 2 ) 1 + 2
S opt
2
S opt F Fmin 2
We define: N= 2
= 1 + opt Fixed for a given noise figure
1 S 4 RN / Z 0 and a set of noise parameters
Noise figure circles (2)
Constant noise figure circle
If a set of noise parameters is chosen, then the value of N is fixed. The source
reflection coefficient can be obtained by the following expression:
2 Circle for
opt N ( N + 1 opt )
S = input (source) constant noise figure
N +1 N +1
center radius opt

CF =
N +1
2
N ( N + 1 opt )
RF =
N +1
For the minimum noise figure (F=Fmin), the intermediate parameter N is equal
zero. The radius of the circle would be zero and the circle reduces to its center
(S = opt) as expected.
Example
A BJT with IC = 10 mA and VCE = 6 V is operated at a frequency of f = 2.4 GHz. The
corresponding S-parameters and noise parameters are given below:
S11 = 0.330 Fmin= 1.5 dB
S12 = 0.260 Rn = 4
S21 = 2.580 opt = 0.545
S22 = 0.215
Show that if the input load impedance is equal Zs=50+j50 , then the amplifier presents
a noise figure less than 1.6 dB.
DC biasing networks
The purpose of biasing is to provide the appropriate quiescent point for the
active devices under specified conditions and maintain a constant setting
irrespective of transistor parameter variations and temperature fluctuations.
A good DC bias is crucial for the robustness of the circuit. If the bias conditions
change, the RF performance will also shift.
Example: bipolar transistor
Passive biasing: using simple resistive networks

Drawback: dissipative, sensitive to changes in transistor parameters, poor
temperature stability
Active biasing: using transistors Higher stability
Drawback: additional space, layout complication, added power requirements
Bipolar transistor biasing networks (1)
2 possible passive biasing configurations:
CB
CB
RFC
RFC
RFC
RFC
CB CB
The RFC and CB isolate the RF signal from the DC power.

DC:
RFC short-circuited
CB open-circuited
AC:
RFC open-circuited
CB short-circuited
Bipolar transistor biasing networks (2)
Possible active biasing network:
CB
RFC
RFC
CB
Q1: A low frequency transistor to provide base current of the RF transistor Q2.
Field effect transistor biasing networks
2 possible passive biasing network (MESFET or depletion mode FET):
VD>0 VD>0
VG<0 VD>0
Bipolar power supply

VS>0 Negative feedback
Example
Design a biasing network for the BJT transistor in the following configuration. The
quiescent point is fixed to IC=10 mA and VCE=3 V while VCC=5 V. Assume that =100 and
VBE=0.8 V.
Broadband amplifier
Constant-gain amplifier over a broad frequency range
Difficulties:
Variations of |S21| and |S12| with frequency. Stability depends on |S21 S12|
Variations of S11 and S22 with frequency.
Degradation of noise figure in some frequencies.
Example
The S parameters of a BJT are given below. Design a broadband amplifier with
a transducer power gain of 10 dB in the frequency range 300 to 700 MHz.
f (MHz) S11 S21 S22

300 0.345 4.4740 0.865
450 0.2770 3.1635 0.85514
700 0.295 230 0.8522
Too small
1
|S21 |2 = 13 dB @ 300 MHz decrease by 3 dB GS max = 2
< 0.5 dB
1 S11
= 10 dB @ 450 MHz 1
= 6 dB @ 700 MHz increase by 4 dB GLmax = 2
5.6 dB
1 S 22
Only the output matching network has to be designed.
Trace different constant gain circles : 3 dB @300 MHz, 0 dB @450 MHz and 4 dB @700 MHz
The matching network has to bring the center of the Smith chart (50) to some point on the 3
different circles. Trial and error procedure
susceptance
1.2
reactance
reactance 1.7
0.5
@300 MHz:
jL2
z L 2 = j (1.7 0.5) =
Z
jZ 0 0
y L1 = j1.2 =
L1
L1 = 22.1 nH

L2 = 31.8 nH
Due to the small value of the input gain, the

input is left without matching but could be
matched for the maximum gain (S = S11* ).
Design techniques (1)
1. Compensated matching networks: introduce mismatching in the input and
output matching networks to compensate the variation of |S21| with frequency.
Drawback: The mismatch would degrade the input and output VSWR.
Balanced amplifier: Each amplifier can be more easily designed for flat gain and
noise figure.
Drawback: Larger circuit size and more DC power consumption due to the presence
of 2 amplifiers.
2. Negative feedback: can be used to have very wide bandwidths with small
gain variations.
Drawback: Noise figure and maximum power gain are degraded.
Transistor model Series and shunt feedback resistances
For FET with both negative feedback resistances:
1 1 1 g m Z 02 2Z 0
1
i1
Y matrix to S matrix
R2 R2 v1 D R2 (1 + g m R1 ) DR2
i = g 1

1 v2
2 m
1 2g Z 2Z 1 g m Z 02
1 + g m R1 R2 R2 m 0
+ 0 1
D 1 + g m R1 R2 D R2 (1 + g m R1 )
Admittance matrix
2Z 0 g m Z 02
Where: D =1+ +
R2 R2 (1 + g m R1 )
To have a perfect zero input and output reflection S11=S22=0
Z 02 1 Z 0 R2 Z0
R1 = S 21 = S12 =
R2 g m Z0 Z 0 + R2
S12 and S21 do not depend on the transistor parameters. The gain flatness can
be obtained by using feedback resistances.
R2 1 S 21
In order to have a positive R1 a limit has to be respected for gm: g m > 2
=
Z0 Z0
Power Amplifiers (PA)
Power amplifier are used in the last stage of the transmitters.
Output power example:
Cellular phone : 0.3-0.6 W
Base station: 10-100 W
For a linear device, the S parameters are well defined and do not depend on
the power level at the input. For a nonlinear device, the impedance seen at the
input and at the output closely depend on the power level presented at the
input of the device. The small-signal S parameters cannot be used, except for
the stability test.
If the input signal power to an amplifier is

large, the transistor can no more be
assumed to operate as a linear device. The
high power level means being around or
above the 1-dB compression point.
Amplifier efficiency and gain
Amplifier efficiency:
Pout
Pout: RF output power =
PDC
PDC: DC input power
Drawback: This definition does not take into account the RF input power.
Power added efficiency:
Pin: RF input power Pout Pin 1

PAE = = (1 )
G : Power gain PDC G
Power amplifiers DC power consuming
Maximum power transfer (complex conjugate match) + Low efficiency Useless
Power amplifiers Designed for the highest efficiency + acceptable amount of

power transfer and linearity Class of operation very important
Compression gain: G1 (dB) = G0 (dB) 1 G0: linear power gain
Operation classes of amplifiers
Amplifiers distinguished by bias conditions:
Class A
Class B
Class AB
Class C
Amplifiers using transistor as switch:
Class D
Class E
Class F
Classes of operation of amplifiers
: conduction angle
Class A: =360
Class B: =180
Class AB: 180<<360
Class C: 0<<180
: efficiency
PRF 0 sin 0
= = Inherently linear
PS 2[0 cos(0 / 2) 2 sin(0 / 2)] LNA
Class A, B, AB and C (1)
General model
RL: load
IDC iout
BFC and BFL: DC/AC separation
Parallel RLC: high Q tank to cut down out-of-band
iD
emissions in narrow band operation
Class A
The bias point is chosen so that the transistor operates linearly.
BJT: avoiding cut-off and saturation
FET: saturation
The linearity is provided at the expense of
efficiency. Even though there is no signal,
the bias current exists.
iD = I DC + iRF sin 0t
iout = iRF sin 0t vout = iRF R sin 0t
Class A, B, AB and C (2)
Class B
The bias is arranged to conduct only
half of the cycle.
Class AB
The bias is arranged to conduct more than
half of the cycle.
The efficiency and linearity are
intermediate between class A
and class B
Class C
The bias is arranged to conduct less
than half of the cycle.
Class D
The transistor is used as a switch.
The ideal switch dissipates no power, either V=0 or I=0.
M1 and M2: similar to push-pull in class B.

Series RLC
Nonzero saturation voltage guarantees static

dissipation while finite switching speeds imply
nonzero V-I product during transitions.
Transistor M1 T2
Class E
To prevent important losses, the switches must be fast relative to the working
frequency. At high frequencies, it is difficult to satisfy this requirement.
In class E, we use high order reactive network to shape the switch voltage to
have zero value and zero slope at switch turn-on.
C1: supplementary capacitance

The values of L, C1 and C2 are obtained using
the desired Q of the circuit.
Switch dissipation at turn-off Not sufficiently superior efficiency
Zero slope at turn-on

Non zero slope at turn-off turn-off turn-on
Class F
The concept of reactive elements used in class E is used further in class F.
Parallel RLC: tuned at carrier frequency
Quarter wave transmission line at carrier frequency
Transmission line properties:
/4 @ 0 Zin= Z0/ZL= Z0
/2 @ (2n)0 Zin= ZL= 0
/4 @ (2n+1)0 Zin= Z0/ZL=
Square wave with 50% duty ratio has only odd harmonics. The circuit guarantees
that all of drain voltage odd harmonics will see no load. The only current that flows in
the circuit is at fundamental frequency.
Large signal characterization Class A (1)
The large signal class A operation introduces some nonlinearities in the output.
If a high Q matching network is used in the output, the harmonics can be
suppressed.
Characterization methods:
1. Measure gain and output power as a function of source and load impedances at
different frequencies. The values are certainly different from the simultaneous
complex conjugate matched reflection coefficients obtained using small signal S
parameters.
Large signal characterization Class A (2)
2. Load-pull technique: Plot contours of constant power output as a function of the load
reflection coefficient with the transistor conjugately matched at the input. The
contours are not perfect circles.
f=10 GHz Load impedance (LP)

VDS=10V
ID=50%IDSS Optimum output power =19dBm
Input conjugately matched: at G1dB=6dB
in = *SP
3. Nonlinear equivalent circuit models.
Load-pull technique
The output tuning stubs are
adjusted until the power meter C For a given frequency and bias conditions:
measures a given power level.
3. Incident 2. Zero
The input tuning stubs are power reflected power
adjusted until the power meter B
shows zero reflected power. In this
case the input is conjugately
matched.
The power meter A reads the

incident power. The power gain
can thus be calculated.
1. Given
power level
The transistor can be separated
from the setup. The impedance at
level A and B can be measured by
a network analyzer. This gives the
value of SP and LP.
Example Quasi linear design
Design a power amplifier at 2 GHz using a BJT. The S parameters of the
transistor and power characteristics at this frequency are:
S11=0.64153 P1-dB=29 dBm
S21=2.3210 G1-dB=11.5dB
S12=0.07 8
S22=0.51119
Output power contours are shown below. The input was conjugately matched
at all time. The P1-dB point and the output conjugate match point were close.
P1-dB = 29 dBm
LP = 0.57 116
Single stage dynamic range
The region where amplifier has a linear power gain.
DR = Pout,1dB Pout,mds
Pout,mds = Pn,out + X
Pn,out = 10 log10 (KTBG0 F )
Pout,1dB: output power at 1dB compression gain

Pout,mds: output power of the minimum detectable signal
Pn,out: output noise power
X: often chosen to be 3 dB
K: Boltzmanns constant (1.3810-23 J/K )

B: Bandwidth in HZ
10 log10 ( KT ) = 173.8 dBm/Hz @ T = 300 K
Single stage harmonic distortion
Intermodulation distortion Fund.
f1 f2 IM3 IM3
2f1 + f2 2f2 + f1
IMD = Pout,1dB ( f 2 ) Pout (2 f 2 f1 )
It can be shown: Pout (2 f 2 f1 ) = 3Pout ( f 2 ) 2 IP3

2
Or: Pout ( f 2 ) Pout (2 f 2 f1 ) = (IP3 Pout (2 f 2 f1 ) )
3
The spurious free dynamic range is when Pout(2f2-f1)=Pout,mds
Df =
2
(IP3 Pout,mds )
3
IMD: Intermodulation distortion
IP3: Third order intercept point
Df: Spurious free dynamic range
Multistage amplifier
Dual stage BJT
Total gain: G tot (dB) = G1 (dB) + G2 (dB)
F2 1
Total noise figure (Friis formula): Ftot = F1 +
G1
1
Total intercept point: IP3tot = (proof in literature)
1 1
+
IP32 G2 IP31
Minimum detectable power: Pout, mds (dBm) = kTB (dBm) + 3dBm + Ftot (dBm) + Gtot (dBm)
Total spurious free dynamic range: D f (dBm) =

2
(IP3tot (dBm) Pout,mds (dBm))
3
References for this chapter
From the list of references:
Gonzalez, chapter 3, 4
Ludwig and Bogdanov, chapter 8, 9
Pozar, chapter 6
Gilmore and Besser, chapter 1, 2, 5
Lee, chapter 15
Villegas, chapter 8, 9, 11

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Master 2nd year Applied Micro & Nano-technologies ESIEE

Master 2nd year Micro-technologies UPEM

Average power delivered to the network:

Power available from source:

Power available from network:

Transducer gain: The ratio of the power delivered to the load to PL

Transducer gain Special case: S12=0 (unilateral)

The over all transducer gain: GT = GS G0GL

And in case of a unilateral transistor:

Two types of stability:

We define: = S11S 22 S12 S 21 S11 L = 1 S 22L

If the device is unconditionally stable, If the device is conditionally stable, there

For the output stability circle

For the input stability circle

Example: Find the stability domain for each configuration.

Smith chart |S22|<1 Smith chart |S11|>1

If both conditions are simultaneously satisfied, the device is unconditionally stable

Unconditionally stable transistor can always be designed for maximum gain.

Maximum transducer gain:

The error introduced into transducer gain caused by this approximation is

Input and output reflection coefficients in a unilateral case:

Gain expressions in unilateral case: ( in = S11 and out = S 22 )

Normalized gain factors in unilateral case:

center radius center radius

Circle for Circle for

Noise figure of a two-port amplifier:

center radius opt

Passive biasing: using simple resistive networks

The RFC and CB isolate the RF signal from the DC power.

Bipolar power supply

f (MHz) S11 S21 S22

Only the output matching network has to be designed.

Due to the small value of the input gain, the

Transistor model Series and shunt feedback resistances

If the input signal power to an amplifier is

Power added efficiency:

Pin: RF input power Pout Pin 1

Power amplifiers DC power consuming

Maximum power transfer (complex conjugate match) + Low efficiency Useless

Power amplifiers Designed for the highest efficiency + acceptable amount of

Compression gain: G1 (dB) = G0 (dB) 1 G0: linear power gain

Amplifiers using transistor as switch:

M1 and M2: similar to push-pull in class B.

Nonzero saturation voltage guarantees static

C1: supplementary capacitance

Switch dissipation at turn-off Not sufficiently superior efficiency

Zero slope at turn-on

Transmission line properties:

f=10 GHz Load impedance (LP)

3. Nonlinear equivalent circuit models.

The power meter A reads the

Pn,out = 10 log10 (KTBG0 F )

Pout,1dB: output power at 1dB compression gain

K: Boltzmanns constant (1.3810-23 J/K )

IMD = Pout,1dB ( f 2 ) Pout (2 f 2 f1 )

It can be shown: Pout (2 f 2 f1 ) = 3Pout ( f 2 ) 2 IP3

Total gain: G tot (dB) = G1 (dB) + G2 (dB)

Total spurious free dynamic range: D f (dBm) =

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