IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO.
7, JULY 2012
An Ultra Low Power Bandgap Operational at Supply
From 0.75 V
Vadim Ivanov, Member, IEEE, Ralf Brederlow, Senior Member, IEEE, and Johannes Gerber, Member, IEEE
Abstractwe present an ultra low power (200 nA current
consumption) reverse bandgap voltage reference operational from
supply voltages down to 0.75 V. The reference is a part of micro-
processor system on chip implemented in a digital 130 nm CMOS
process and has a total area of 0.07 mm . The reference accuracy
is 2.5% (5 sigma) over a temperature range of 20 to 85 C
without trimming. With trimming 0.5% accuracy is achieved.
Index TermsVoltage reference, low voltage, low power, reverse
bandgap, supply supervisor.
I. INTRODUCTION
A VOLTAGE reference is an important building block in
many of todays mixed-signal systems and especially
in battery powered applications. With a non-constant voltage
supply, the voltage generated from such reference is input to
power management, voltage supervision and many other analog
circuits.
In this paper we will discuss a new reference topology. The
reference is part of a larger system on chip containing a 16 bit
MCU with SRAM and ROM for data and code storage, timer
circuits for generating PWM signals, and an ADC to monitor
external voltage signals. The system operates from a single al-
kaline battery cell varying from 1.65 V down to 0.9 V over life-
time. Since the battery should not be discharged from the in-
tegrated circuit too fast (especially in stand-by), the reference
needs to have an average current consumption in sub- A range.
An accurate detection of the low voltage conditions is needed to
further maximize the battery lifetime. Together with a voltage
supervising comparator the reference provides the necessary
power-on-reset (POR) signal for the digital part in a supply
voltage low condition. The reference is also used in the on-chip
ADC block. In this use-case the reference accuracy directly re-
lates to maximum absolute resolution of ADC. Therefore an ac-
curacy of better than 1% in the 20 to 85 C temperature range
is set as system requirement.
Due to the min voltage requirement of 0.9 V, the classic
1.2 V bandgap architecture cannot be used here. There are sev-
eral approaches to overcome the problem of voltage reference
operational from sub-1 V supply. Most commonly used is a
current-mode reference which sums two different-TC current
branches as proposed in [1]. This concept suffers in accuracy
Manuscript received November 15, 2011; revised January 23, 2012; accepted
January 26, 2012. Date of publication April 27, 2012; date of current version
June 21, 2012. This paper was approved by Guest Editor Trond Ytterdal.
V. Ivanov is with Texas Instruments, Inc., Tucson, AZ 85711 USA.
R. Brederlow and J. Gerber are with Texas Instruments Deutschland Gmbh,
Freising, Germany.
Digital Object Identifier 10.1109/JSSC.2012.2191192
0018-9200/$31.00 2012 IEEE
1515
and noise from inherently deficient matching in the summing
current mirror because this mirror is outside of the bandgap
feedback loop.
A range of solutions make use of the standard bandgap cir-
cuit topology while using the of MOS diodes as the absolute
voltage reference source [2], [3]. Since MOS s are poorly
controlled in a manufacturing environment, an extensiveun-
realistic for high-volume productiontrimming is required to
achieve the accurate reference voltage.
Another class of circuits implements a reverse voltage
bandgap principle as shown in [4]. The accuracy of these
circuits is in par with traditional bandgap but it needs the high
gain PNP or NPN transistors which are rarely available in the
digital CMOS processes.
For the design discussed here significant limitation have been
imposed by the process used (130 nm low-cost CMOS). For
analog design purpose it offers only substrate low-gain
PNP transistors and low-density (70 Ohms/square) poly resis-
tors with very high temperature coefficient.
In Section II we present a voltage reference core based
on the reverse bandgap concept of [4], but instead using a
low-gain ( of 24) substrate PNP (available on any CMOS
process) in diode configuration. This diode is amended by a
new switch-capacitor voltage sampling scheme for obtaining
positive and negative temperature coefficient components of
the reverse bandgap voltage.
The core produces a low (186 mV) output voltage which
needs to be accurately scaled to required references (256 mV
for ADC and 900 mV for POR comparator). Any offset of the
scaling amplifier can significantly damage accuracy. Therefore
we use an auto-zeroed amplifier as described in Section III.
In Section IV we present a new sample/hold circuit allowing
very long hold times (100 ms in our case) without significant
leakage-introduced errors. With this circuit the discontinuous
operation of the reverse bandgap core and ultra-low average cur-
rent consumption of the reference becomes possible.
Discontinuous operation of the core also dictates an intricate
3-step startup procedure for reliable continuous-time POR func-
tion as is required for digital part of the system. The state ma-
chine for the startup sequence is described in Section V. Finally,
silicon and simulation results are presented in the Section VI.
II. SAMPLE-BASED REVERSE BANDGAP REFERENCE CORE
Fig. 1 shows the concept of the sampled reverse bandgap
core. A substrate PNP bipolar transistor in diode configuration
is biased during consecutive clock cycles, and , by the
two different currents with ratio of , thus generating both
(with negative temperature coefficient of approximately minus
2 mV/K) and proportional to absolute temperature (PTAT)
1516 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 7, JULY 2012

Fig. 1. Sampled reverse bandgap principle.

Fig. 2. Reference core.

voltage. These voltages are sampled and attenuated using a

capacitive voltage divider. In the first clock phase the diode
is biased by current and the voltage is charged to
.
During next phase transistor is biased by the current
. The voltage drop across increases by
, where is the temperature potential of
the pn junction ( -Boltzmann constant, -electron charge). The
voltage is now equal to
Fig. 3. Scaling up the reference with auto-zeroed amplifier.
(1)

and becomes independent of temperature when

(2)

The minimum supply voltage of the described circuit is lim-

ited to , where is the satura-
tion voltage of the current sources driving the bipolar transistor
in Fig. 1. Even at 20 C, can be as low as 0.75 V.
The reverse bandgap voltage value is based on physical
constants and has no significant variation from one wafer to an-
other or even from one process to another. Errors, noise, sen-
sitivity to the component mismatch, and stability of are Fig. 4. Schematic of the reference scaling amplifier.
equivalent to the accuracy parameters of the traditional bandgap
voltage [5].
The only drawback of the reverse bandgap is the low To create is mirrored by and during and
value, which is located, for realistic numbers below 100, in respectively. Area ratio of generates the
the 180200 mV range. Such a low reference voltage makes discussed in the previous section.
offset and noise of the after-reference amplifierwhich buffers Metal/metal capacitors and have parasitic fraction be-
and scales to the desired output valuemuch more signifi- tween bottom plate and underlying poly-Si layer. These para-
cant in the total error budget. sitic caps effectively change ratio during sampling
A simplified circuit of the reference core is shown in Fig. 2. It and, if connected to ground, attenuate the PTAT fraction of
contains the bias current generator , which (1). In order to prevent further decrease of the already small
creates . The voltage across resistor is equal to (186 mV) voltage, the poly-Si layers of and are con-
of the bipolar transistor and has a negative temperature nected to the emitter of .
coefficient. Due to the very high TC of polysilicon resistors in For a regular bandgap the magic value of the reference,
the used process the biasing current has positive TC. Positive when TC is close to zero, is about 1.2 V and varies just slightly
TC biasing of the reference-generating diode decreases, to between processes. The magic value of the reverse bandgap
some degree, the curvature [5] thus improving temperature depends not only on process, but also on the PTAT-generating
stability of the reference. ratio of currents and value of the biasing current . The trim
IVANOV et al.: AN ULTRA LOW POWER BANDGAP OPERATIONAL AT SUPPLY FROM 0.75 V 1517

Fig. 5. (a) Standard S/H. (b) Long-hold S/H.

Fig. 6. Sample/long hold for 256 mV output.

range of and the reference target value has been chosen based . During the non-inverting input is connected to
on simulations. Only slight adjustment have been done after (the proximity of and ensures that the offset shift
silicon bench testing (simulated magic value was 185 mV between and , caused by limited common-mode rejection
instead of measured 186 mV). of the amplifier is also small). The inverting input is connected
The trim capability was designed in for the absolute value of through capacitor to the resistive divider . The ampli-
the 256 mV and 900 mV outputs as well as for the temperature fier output voltage, , is equal to
coefficient by adjusting the . Since has excellent repeata- during sub-phase and
bility on the process used (less than 2 mV lot to lot variation), during sub-phase .
the absolute value trim is omitted and the reference magnitude The schematic of amplifier is shown in Fig. 4. Since the
is trimmed to 186 mV by 4-bit variation of N between 50 to 80 input voltage is always low, a simple two gain stage struc-
with nominal . This trim range is translating to approxi- ture (input PMOS differential pair and output device
mately V/K range of the reference temperature coefficient ) with folded cascode is used. A
with mV variation of the reference value at room temper- second gain stage is needed to increase gain and provide high
ature. We start with gain trimming of the amplifier which com- output voltage and current sourcing capability. provides the
pensates for changes (absolute value). This value is fixed cascoded Miller compensation of this 2-stage amplifier.
according to a measurement and compared with a golden Enough headroom is available for all transistor operation
value. Current trimming is used to correct the slope (changing even at 0.75 V supply due to the low of the devices used
the PTAT portion of ). All trimming is done at 25 C. (around 0.3 V for NMOS and 0.4 V for PMOS). All devices,
except , are sized for operation in weak inver-
III. SCALING AMPLIFIER sion, which improves offset, noise and gain of the amplifier.
For the chosen values and nA the mag- The absolute value of 256 mV and 900 mV output voltages
nitude of the temperature-stable is 186 mV and has to be can be trimmed in production by changing the scaling amplifier
accurately scaled up to 256 mV and 900 mV levels needed by feedback resistor ratio ( in Fig. 3).
the system. This is done via amplifier as shown in Fig. 3.
To eliminate the offset-induced error, is auto-zeroed. IV. SAMPLE/VERY LONG HOLD CIRCUIT
During the non-inverting amplifier input is connected to Ultra low energy consumption of the bandgap reference can
the biasing voltage approximately equal to while the be achieved in two ways:
amplifier output is connected to the non-inverting input. is By decreasing currents running in the core with use of the
generated in biasing part as fraction of by splitting resistor prohibitively large resistors in 100s of MOhms range.
by the ratio of capacitors (see Fig. 2). It operates in Even if these resistors were realistic they would increase
a follower configuration, averaging the offset on the capacitor the bandgap noise. We could not find any publications
1518
Fig. 7. 256 mV reference buffer.
Fig. 8. Inside-loop connection of the buffer during sampling.
Fig. 9. POR startup procedure.
on the noise in ultra low power bandgaps, but according
to simulations the peak-to-peak noise in the bandgap
with 100200 nA consumption becomes a dominant error
source.
By activating bandgap core for short periods of time and
sampling reference voltage on the capacitor. Low charge
leakage from this capacitor during long hold periods is
critical for accuracy of such a reference.
The reference value varies between every sampling de-
pending on the peak-to-peak noise and errors in the reference
core and scaling amplifier during the sampling process.
Throughout the hold period the reference voltage is virtually
noiseless as the hold capacitor does not generate noise. In such
a sampled operation mode it can be an advantage when refresh
timing of the reference is correlated with system events.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 7, JULY 2012
The generation in our circuit takes approximately
250 s. The total current consumption of the reference core and
scaling amplifier during this period is about 6 A. We chose
a 100 ms period between refreshlonger than most of system
events-so the average current consumption of the reference
core itself is around 1520 nA. The total consumption of the
circuit ( 200 nA) is dominated by service circuitry (start-up,
biasing, timing oscillator, etc.).
Charge leakage from the capacitor in the standard
sample/hold (S/H) circuit [Fig. 5(a)], is dominated by the junc-
tion leakage of the switch (drain-body plus drain-source
currents). Junction leakage is roughly proportional to the
voltage drop across junction. Therefore low leakage and long
hold time S/H can be realized by keeping zero voltage across
drain-source and drain-body of the switch.
IVANOV et al.: AN ULTRA LOW POWER BANDGAP OPERATIONAL AT SUPPLY FROM 0.75 V 1519

Fig. 10. Biasing core and power up checks.

Fig. 13. Ripple of 256 mV reference during refresh.

Fig. 11. Biasing core and resample timing.

Fig. 14. Simulated temperature dependence of the reverse bandgap voltage.

The circuit shown in Fig. 5(b) keeps the voltage across drain-
body and drain-source of equal to the offset of the fol-
lower . The output current of this follower is equal to
the total of junction leakages from . These leakages
do not exceed a few pA even at high temperature. A follower
tail current of 2 nA is more than sufficient to provide the output.
While consuming only 2 nA current, active control of the S/H
leakage proved to be quite efficient. Test chip measurements
Fig. 12. Layout of the reference. show that the voltage decay across (5 pF value) is well inside
1520 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 7, JULY 2012

Fig. 15. Temperature dependence of the 256 mV reference output.

Fig. 16. Supply dependence of the 256 mV reference output.

the reference error window during the 100 ms hold time even at that voltage from capacitor has to be buffered. This buffer
85 C. should:
Sampling of the voltage is done during part of each provide up to 1 mA output current;
of the (256 mV output) and (900 mV output) time be stable with any load capacitor (few pF of on-chip ca-
steps. To allow for transient settling a 510 s delay at the pacitance in parallel with unpredictable external load);
beginning of the phases is introduced. consume only few A from supply.
These requirements are achieved using a nested gain design
V. SAMPLING AND BUFFERING OF THE 256 MV REFERENCE [6] as shown in Fig. 7. The main gain path consists of the differ-
The S/H circuit of Fig. 5(b) is utilized for sampling the ential pair , the folded cascode , and the
900 mV voltage needed by the POR comparator. A comple- follower . The current gain of the transistor is boosted
mentary circuit for sampling the 256 mV voltage needed for by the loop, which is amended by circuit controlling
the ADC is not possible in the process due to the substrate body the minimum current through and providing pull-down ca-
connection of all NMOS devices on chip. pability in the buffer. This circuit includes pull-down transistor
To circumvent this limitation, the switch used in the and voltage source .
complimentary S/H circuit of Fig. 6 is PMOS type instead of While consuming only 1 A this buffer has 500 kHz band-
NMOS. To turn it ON during sampling its gate is driven below width and is stable with an on-chip load capacitor of only 20 pF
substrate by the charge pump . as well as with external one of 0.1 F or more.
The 256 mV reference is used by the on-chip ADC, but The offset of the buffer (up to 5 mV) can significantly
also may be routed to the pin for external use, which means damage accuracy of the 256 mV reference.
IVANOV et al.: AN ULTRA LOW POWER BANDGAP OPERATIONAL AT SUPPLY FROM 0.75 V 1521

TABLE I
REFERENCE PARAMETERS AND COMPARISON

To prevent this offset, the buffer is placed during sampling

inside the 186 mV scaling loop, as shown in Fig. 8. As a re-
sult, the offset of the buffer does not affect the reference accu-
racy since the voltage across the hold capacitor is
256 mV . According to Monte-Carlo simulations, the
maximum error introduced into the 256 mV reference voltage
by the auto-zeroed scaling amplifier and buffer together does
not exceed 200 V (6 sigma), or 0.1%.

VI. STARTUP PROCEDURE AND TIMING

For reliable operation in a battery driven digital application
it is especially important to assure correct system behavior at
power up as well as at power down. To assure reliable logic op-
eration it needs to be checked that the supply voltage is higher
than the minimum voltage used for synthesis of the digital cir-
cuits. With discontinuous operation of the reference core, it ne-
cessitates a 3-step startup procedure illustrated by a diagram in
Fig. 9.
The biasing core (Fig. 10) starts first. Unit current in this core
is equal to , where is area ratio of
. is set to 5 nA by a 2 MOhm resistor . This
is by far the largest resistor in the reference and occupies ap-
proximately 10% of its die area.
The biasing core is followed by the comparators checking
supply against ) and . First check is
necessary to guarantee operation of T-gates inside the flip-flops Fig. 17. Production distribution histogram of reference output voltage.
of the state machine. The second checks for the correct operation
of the reverse bandgap core. After these checks passed, the local
clock oscillator (20 kHz) and state machine are started. passed, the comparator of the continuous system POR is en-
The startup timing is illustrated in Fig. 11. abled. Otherwise, the reference core is turned off till the next
After the 186 mV reference voltage is generated by the re- refresh period in another 100 ms.
verse bandgap core, the scaling amplifier sequentially gener- The comparator of the continuous POR consumes 10 nA
ates 256 mV and then 900 mV outputs. Then it is switched into which ensures approximately 5 s propagation delay. It guaran-
comparator mode and checks with an additional resistive divider tees reliable shutdown of the microprocessor in case the battery
the supply voltage to be larger than 1.1 V (the microprocessor is almost fully discharged and cannot support the reliable
should not be starting if battery is not fresh). If this check is system operation any more.
1522
The 20 kHz oscillator has an RC ring topology and consumes
approximately half of the 200 nA current budget of the refer-
ence. It is also clock to a state machine which provides digital
signals to enable the bandgap core once every 100 ms as well
as all the timing signals for the reference sampling sequence.
VII. SIMULATION AND MEASUREMENTS RESULTS
This bandgap reference is implemented in a standard dig-
ital CMOS process with 130 nm minimum channel length. The
layout of the cell is shown in Fig. 12. It occupies 70,000 m of
area. Approximately 30% of it is taken by the resistors, mainly
in the biasing core (Fig. 10). Having a high-ohmic resistor
option available would therefore significantly shrink the circuit
size.
The highest error of the reference voltage comes from ripple
during the sampling procedure. This ripple on the 256 mV ref-
erence output can be as large as 20 mV peak to peak. A typical
ripple waveform is shown in Fig. 13. The ripple can be elimi-
nated by better timing and non-overlapping control in the sam-
pling circuitry, combined with charge injection compensation.
However, for the use case in this system this is not needed. The
sampling is timed to system events and the reference is not used
during ripple moments.
Comparing SPICE simulation results, the temperature vari-
ation of the reverse bandgap reference voltage is similar to a
classic bandgap curvature as shown in Fig. 14. Its curvature is
even lower than the classic bandgap temperature variation in the
same temperature range % due to the complicated temper-
ature dependence of the diode biasing current. This biasing cur-
rent is defined by the voltage drop across resistor of Fig. 2
(which has a negative TC) and the nonlinear temperature depen-
dence of the poly resistor itself.
The measured temperature variation of the 256 mV reference
voltage of the trimmed set of 180 units is shown in Fig. 15 and
supply variation is in Fig. 16. All data has been taken on pack-
aged parts.
The slightly negative dependence of the output voltage is at-
tributed to incorrect capacitance layout extraction which caused
a change in the capacitor divider ratio.
The distribution of the untrimmed and trimmed reference
values in production is shown in Fig. 17. The data out of 90,000
units from five wafer lots are taken for the purpose.
Untrimmed references have approximately % variation
in reference voltage (3 sigma). This is similar to the classic
bandgap spread. With trimming precision of less than 0.5%
(3 sigma) is achieved. Table I compares this design to prior
state of the art references. With the exception of [4] the new
concepts allows for higher precision at a lower power and
similar area. Since [4] uses complementary bipolar transistors
it cannot be used in standard digital CMOS technologies.
VIII. CONCLUSION
We have introduced a new reference circuit concept able to
operate down to supply voltages as low as 0.75 V. The circuit
consumes 170 nW of power and the reverse bandgap operation
principle for reference generation enables the best accuracy in
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 7, JULY 2012
the sub-volt class of voltage references. Using switched-capac-
itor techniques for reference generation is not only solving lim-
itations imposed by the digital CMOS process, but also allows
us to decrease the minimum operating voltage by 150 mV, com-
pared to the reverse bandgap presented in [4]. This technique
well aligns to the introduced S/H buffer approach which enables
the design of a voltage reference with nano-power consumption
while preserving low noise and high accuracy.
ACKNOWLEDGMENT
The authors thank Gerd Poeschl for measuring the statistical
data, Thomas Tost and Estelle Tay for floor planning and layout,
and Alicia Fresno-Delso for laboratory measurement support.
REFERENCES
[1] H. Banba, A. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi,
and K. Sakui, A CMOS bandgap reference circuit with sub-1-V oper-
ation, IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 670674, May
1999.
[2] K. N. Leung and P. K. T. Mok, A CMOS voltage reference based on
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Solid-State Circuits, vol. 38, no. 1, pp. 146150, Jan. 2003.
[3] K. Ueono, T. Hirose, T. Asai, and Y. Amemiya, A 300 nW 15 ppm/ C
20 ppm/V CMOS voltage reference circuit consisting of subthreshold
MOSFETs, IEEE J. Solid-State Circuits, vol. 44, pp. 20472054, July
2009.
[4] K. Sanborn, D. Ma, and V. Ivanov, A sub-1-V low-noise bandgap
voltage reference, IEEE J. Solid-State Circuits, vol. 42, pp.
24662481, Nov. 2007.
[5] Y. Tsividis, Accurate analysis of temperature effects in
characteristics with application to bandgap reference sources, IEEE
J. Solid-State Circuits, vol. 15, no. 5, pp. 10761084, Dec. 1980.
[6] V. Ivanov, Design methodology and circuit techniques for any-load
stable LDOs with instant load regulation and low noise, in Advanced
Analog Circuit Design. New York: Springer, 2008.
Vadim Ivanov (M96) received the M.S.E.E. degree
in 1980, and the Ph.D. in 1987, both in the USSR.
He designed electronic systems and ASICs for
naval navigation equipment from 1980 to 1991 in
St. Petersburg, Russia and mixed signal ASICs for
sensors, GPS/GLONASS receivers and for motor
control between 1991 and 1995. He joined Burr
Brown (presently Texas Instruments/Tucson) in
1996 as a senior member of technical staff, where
he designed multiple operational, instrumentation,
power amplifiers and voltage references as well as
switching and linear voltage regulators. He has more than 60 US patents and
applications on analog circuit techniques and authored around 30 technical
papers and three books: Power Integrated Amplifiers (Leningrad, Rumb, 1987),
Analog System Design Using ASICs (Leningrad, Rumb, 1988), both in Russian,
and Operational Amplifier Speed and Accuracy Improvement (Kluwer, 2004).
Ralf Brederlow (SM06) was born in Munich, Ger-
many, in 1970. He received the Dipl.-Phys. degree
from the Technical University of Munich in 1996 and
the Dr.-Ing. degree from the Technical University of
Berlin in 1999.
In 1996 he was associated with Siemens Corpo-
rate Research, working on the characterization, mod-
eling and reliability of noise in analog circuits. 1999
he joined Corporate Research of Infineon Technolo-
gies, working as designer and project manager for de-
sign/technology co-optimization. During this period
he worked on noise tolerant analog and digital module design, on design for
manufacturing for analog CMOS circuits, polymer electronics for RFID, and
sensor systems for bio-chemical applications. In 2005 he joined Infineon Tech-
nologies Smart Card division. There he was responsible for the development of
the analog power and communication interface block for a new dual mode smart
IVANOV et al.: AN ULTRA LOW POWER BANDGAP OPERATIONAL AT SUPPLY FROM 0.75 V
card IC family. In October 2006 he joined Texas Instrument Germany as Senior
Member of Technical Staff and leader of a design team for analog peripherals for
TIs ultra low power 16 bit microcontrollers (MSP430). This included designs
of analog-to-digital, and digital-to-analog converters, power management and
clock circuitry, and communication interface blocks. From September 2008 to
January 2011 he was responsible for new IP development (analog, digital, and
memory) within TIs MSP430 microcontroller family. Since February 2011 he
is a Distinguished Member Technical Staff responsible for predevelopment of
new technology and IP for the ultra low power microcontroller families at Texas
Instruments.
Dr. Brederlow has authored or co-authored more than 50 technical publica-
tions and holds 10 patents. He has been General Program Chair of the 2008
International Electron Device Meeting (IEDM), is a member of the European
Solid State Device and Circuit (ESSDERC/ESSCIRC) steering committee, and
the European Solid State Circuit Conference technical committee. From 2000 to
2005 he participated in the International Roadmap for Semiconductors (ITRS)
as member and sub-group lead in the wireless technology and the design tech-
nical working group. Ralf Brederlow is a Senior Member of IEEE, and a member
of VDE and of DPG.
1523
Johannes Gerber (M98) received the Dipl.-Ing. de-
gree in electrical engineering from the University of
Erlangen-Nuernberg, Germany, in 1993.
From 1993 to 1998, he worked at the Fraunhofer
Institute for Integrated Circuits IIS in Erlangen, Ger-
many in the field of integrated sensors in CMOS and
analog circuit design. In 1998 he joined the RF de-
sign group at Texas Instruments in Freising, Germany
where he concentrated on the CMOS integration of
frequency synthesizers and high speed serial commu-
nication devices. He later focused on low power/low
voltage circuits. He is currently working in the MSP430 microcontroller de-
partment. His research interests include bandgaps, operational amplifiers, oscil-
lators, LDOs with low and ultra low power consumption.