PROJECT REPORT

ON

GPIO PIN EXPANSION USING I2C

INTERFACE
January 2012

SUBMITTED FOR

PARTIAL FULFILMENT OF THE REQUIREMENT FOR THE AWARD OF

PG DIPLOMA

POST GRADUATE DIPLOMA IN EMBEDDED SYSTEM &

VLSI DESIGN

Submitted By:

Praveen Kumar Akanksha Mahajan

110521002, PGDEVD 110521008, PGDEVD

Ekta Kumari Parul Chauhan

110521016, PGDEVD 110521036, PGDEVD

Under the Esteemed Guidance of

Mr. Ravi Payal

CENTRE FOR DEVELOPMENT OF ADVANCED

COMPUTING, NOIDA
 CERTIFICATE

This is to certify that the project entitled GPIO Pin Expansion Using I2C

Interface has been prepared jointly by four students - Praveen Kumar,

Akanksha Mahajan, Ekta Kumari and Parul Chauhan of PGDEVD and

submitted under my supervision. The students have prepared a basic conceptual

model of GPIO Pin Expansion Using I2C Interface by themselves. The

project is being submitted by the students as partial fulfillment of the

requirement for the award of the PGDEVD of CDAC, Noida.

Signature Signature

MR. V.K. SHARMA MR. RAVI PAYAL

Head of Department, Senior IT Consultant
CDAC Noida CDAC Noida

i
 ACKNOWLEDGMENT

It is matter of great pride and privilege for us to have the esteemed supervision
of our Mr. V. K. SHARMA (Program Coordinator, CDAC Noida) for
giving us this opportunity of making this project.

It gives us the immense pleasure in thanking Mr. RAVI PAYAL (Senior IT

Consultant, CDAC Noida) who gave us the proper guidance and invaluable
support in completing this project successfully.

Were also very grateful to Mr. RAVI PAYAL (Senior IT Consultant, CDAC
Noida) for providing various facilities at college which helped in successful
completion of the project.

And finally, a special thanks to all the helping staff for their invaluable support.

PGDEVD Praveen Kumar

Batch XXI (Aug, 2011 Jan 2012) Akanksha Mahajan
CDAC Noida, Ekta Kumari
Department of IT, Parul Chauhan
Government of India
ii
 ABSTRACT
In some cases, it may be required to have access to GPIO (General Purpose

Input/Output) pins from a relatively long PCB trace path within the system.

Since the I2C interface is a two-wire system, the design aims to provide multiple

inputs and outputs pins at the remote end with just a common two-wire trace.

This will provide increase design flexibility and also adds to physical

compactness of entire system. It also enables smaller packaging and reduced pin

count.

The design aims to achieve the capability to provide general purpose I/O

(GPIO) pin expansion via an industry standard I2C bus.

To reduce package size and pin count, the number of general purpose I/Os are

limited in many microprocessor-based systems. However, if the system has an

I2C interface, additional GPIO pins via the I2C bus can be easily added.

iii
 TABLE OF CONTENTS

Certificate i
Acknowledgement ii
Abstract iii

1. Architecture
1.1 I2C Interface for GPIO Pin Expansion 1
1.2 I2C Signal Format 2

2. I2C Bus Protocol

2.1 Data Validity 3
2.2 START and STOP Conditions 4
2.3 Packet format 4
2.4 Clock Stretching 5
2.5 Acknowledge or No Acknowledge 6
2.6 Clock Synchronization 7
2.7 Arbitration 8

3. Verilog Code
3.1 Design Block 9
3.2 Stimulus Block 14

4. Simulation Result
4.1 Simulated Waveform 17

5. Synthesis Report
5.1 RTL Schematic 19
5.2 Technology Schematic 20
5.3 Synthesis Report 21

6. Conclusion 23

7. Bibliography 24
1. ARCHITECTURE

1.1 I2C Interface for GPIO Pin Expansion

The SPARTAN 2 FPGA acts as a slave on the I2C bus and has two pins on its I2C interface:
the I2C clock SCL and the I2C data line SDA. The host system, which acts as an I2C master,
communicates with the SPARTAN 2 FPGA device (which acts as an I2C slave). The FPGA
present eight general purpose input ports and eight general purpose output ports to the host.
Data, which is transmitted serially over the I2C bus, is received in parallel at the GPIO pins.
This way, all eight general purpose I/Os can be read or written at the same time.

Figure 1.1 - GPIO Pin Expansion Using I2C Interface

Table 1.1 - I2C Interface Pin Descriptions

Signal Purpose Direction

SCL I2C clock Output
SDA I2C serial data Bidirectional

GPIO Pin Expansion Using I2C Interface 1

1.2 I2C Signal Format
For the I2C interface, the FPGA (I2C slave) has a built-in 7-bit address and follows the
general I2C protocol. The start signal is sent by the master, followed by the 7-bit address and
an R/W bit. When the address broadcast on the I2C bus matches a slave devices address, an
ACK (acknowledge) signal is sent by the device followed by data according to the read or
write signal sent by the master. This is then followed by another ACK signal. The exchange
of data continues in this manner until the STOP (P) signal is sent by the master.

Figure 1.2 - I2C Signal Format

Whenever the master issues a write condition (R/W = 0), the data received on the I2C bus is
used to update the general purpose output pins until a stop or repeat start condition is
encountered. Similarly, when the I2C master issues a read condition (R/W = 1), the values at
the general purpose input pins are sampled at the ACK bit and transmitted serially over the
I2C bus. This process continues until the master issues a stop or repeat start.

Table 1.2 GPIO Pin Descriptions

Signal Purpose Direction

8-bit Input General Input
8-bit Output General Output

GPIO Pin Expansion Using I2C Interface 2

2. I2C BUS PROTOCOL
The I2C bus was originally started by NXP Semiconductors, but in recent years has become a
widely used standard adapted by many semiconductor chip companies. I2C is ideal for
attaching low-speed peripherals to a motherboard or embedded system or anywhere that a
reliable communication over a short distance is required. I2C provides a reliable connection
oriented communication. I2C devices use only 2 pins for data transfer, instead of the 8 or
more pins used in traditional buses. They are called SCL (Serial Clock), which synchronize
the data transfer between two chips, and SDA (Serial Data). This reduction of communication
pins reduces the package size and power consumption drastically, making them ideal for
many applications in which space is a major concern. These two pins, SDA and SCK, make
the I2C a 2-wire interface.

Term Description

Transmitter the device which sends data to the bus

Receiver the device which receives data from the bus
Master the device which initiates a transfer, generates clock signals and terminates
a transfer
Slave the device addressed by a master
Multi-master more than one master can attempt to control the bus at the same time without
corrupting the message
Arbitration procedure to ensure that, if more than one master simultaneously tries to control
the bus, only one is allowed to do so & the winning message isnt corrupted

Table 2.1 I2C Bus terminology

2.1 Data Validity

I2C is a synchronous serial protocol; each data bit transferred on the SDA line is
synchronized by a high-to-low pulse of clock on the SCL line. According to I2C protocols the
data line cant change when the clock line is high; it can change only when the clock line is
low. The START and STOP conditions are the only exceptions to this rule.

Figure 2.1 - I2C Bit Format

GPIO Pin Expansion Using I2C Interface 3

2.2 START and STOP conditions
I2C is a connection-oriented communication protocol. This means that each transmission is
initiated by a START condition and is terminated by a STOP condition. START and STOP
conditions are always generated by the master.
START and STOP conditions must be distinguished from bits of address or data. Thats why
they dont obey the bit format rule mentioned above.

START and STOP condition are generated by keeping the level of the SCL line high and then
changing the level of the SDA line. The START condition is generated by high-to-low
change in the SDA line when SCL line is high. The STOP condition is generated by a low-to-
high change in the SDA line SCL is low.

Figure 2.2 START and STOP conditions

2.3 Packet format

In I2C, each address or data to be transmitted must be framed in a packet. Each packet is 9
bits long. The first 8 bits are put on the SDA line by the transmitter, and the 9th bit is an
acknowledgment by the receiver or it may be NACK (not acknowledge). The clock is
generated by the master, regardless of whether its the transmitter or the receiver. To get an
acknowledgement, the transmitter releases the SDA line during the ninth clock so that the
receiver can pull the SDA line low to indicate an ACK. If the receiver doesnt pull the SDA
line low, its considered as NACK.

In I2C, each packet may contain either address or data. START condition + address packet +
one or more data packet + STOP condition together form a complete data transfer.

Address Packet format

All the address packets transmitted on the I2C bus are 9-bits long. An address packet consists
of 7 address bits, 1 READ/WRITE control bit, and an acknowledge bit.

Address bits are used to address a specific slave device on the bus. The 7-bit address lets the
master address a maximum of 128 slaves on the bus, although the address 0000 000 is
reserved for general call and all address of the format 1111 xxx are reserved. That means 119
devices can share I2C bus. In I2C bus the MSB of the address is transmitted first. The 8th bit in
the packet is the READ/WRITE control bit. If this bit is set the master will read the next
frame (data) from the slave, otherwise, the master will write the next frame (data) on the bus
to the slave. When a slave detects its address on the bus, it knows that its being addressed
GPIO Pin Expansion Using I2C Interface 4
and it should acknowledge in the 9th SCL (ACK) cycle by changing SDA to zero. If the
addressed slave isnt ready or for any reason doesnt want to service the master, it should
leave the SDA line high in 9th clock cycle. This is considered to be NACK. In case of NACK,
the master can transmit a STOP condition to terminate the transmission, or a REPEATED
START condition to initiate a new transmission.

When a master transmits address 0000 000, all slaves respond by changing the SDA line to
zero and wait to receive the data byte. This is useful when a master wants to transmit the
same data byte to all slaves in the system. The general call address cant be used to read data
from slaves because no more than one slave is able to write to the bus at a given time.

Data Packet format

Like other packets, data packets are 9 bits long too. The first 8 bits are a byte of data to be
transmitted, and the 9th bit is the ACK. If the receiver has received the last byte of data and
there is no more data to be received, or the receiver cant receive or process more data, itll
signal a NACK by leaving the SDA line high. In data packets, like address packets, MSB is
transmitted first.

Combining Address and Data Packet

In I2C, normally, a transmission is started by a START condition, followed by an address
packet, one or more data packets, and finished by a STOP condition.

Figure 2.3 Typical Data Transmission

2.4 Clock Stretching

One of the features of the I2C protocol is clock stretching. It is a kind of flow control. If an
addressed slave device isnt ready to process more data it will stretch the clock by holding the
clock line SCL low after receiving (or sending) a bit of data. Thus the master will not be able
to raise the clock line (because devices are wired-ANDed) and will wait until the slave
releases the SCL line to show its ready to transfer the next bit.

GPIO Pin Expansion Using I2C Interface 5

2.5 Acknowledge or No Acknowledge
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to
signal the transmitter that the byte was successfully received and another byte may be sent.
All clock pulses including the acknowledgment 9th clock pulse are generated by the master.

The Acknowledge signal is defined as follows: the transmitter releases the SDA line during
the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable
LOW during the HIGH period of this clock pulse. Set-up and hold times must also be taken
into account. When SDA remains HIGH during this 9th clock pulse, this is defined as the Not
Acknowledge signal. The master can then generate either a STOP condition to abort the
transfer, or a repeated START condition to start a new transfer.

There are five conditions that lead to the generation of a NACK:

1. No receiver is present on the bus with the transmitted address so there is no device to
respond with an acknowledgment.
2. The receiver is unable to receive or transmit because its performing some real-time
function and is not ready to start communication with the master.
3. During the transfer the receiver gets data or commands that it does not understand.
4. During the transfer, the receiver cannot receive any more data bytes.
5. A master-receiver needs to signal the end of the transfer to the slave transmitter.

Figure 2.6 A complete data transfer

GPIO Pin Expansion Using I2C Interface 6

2.6 Clock Synchronization

Two masters can begin transmitting on an idle bus at the same time and there needs to be a
method for deciding which will take control of the bus and complete its transmission. This is
done by clock synchronization and arbitration. In single master systems, clock
synchronization and arbitration are not needed.

Clock synchronization is performed using the wired-AND connection of I2C interfaces to the
SCL line. This means that a HIGH to LOW transition on the SCL line will cause the masters
concerned to start counting off their LOW period and, once a master clock has gone LOW, it
will hold the SCL line in that state until the clock HIGH state is reached. However, the LOW
to HIGH transition of this clock may not change the state of the SCL line if another clock is
still within its LOW period. The SCL line will therefore be held LOW by the master with the
longest LOW period. Masters with shorter LOW periods enter a HIGH wait-state during this
time.

When all masters concerned have counted off their LOW period, the clock line will be
released and go HIGH. There will then be no difference between the master clocks and the
state of the SCL line, and all the masters will start counting their HIGH periods. The first
master to complete its HIGH period will again pull the SCL line LOW.

Figure 2.4 - Clock synchronization during the arbitration process

In this way, a synchronized SCL clock is generated with its LOW period determined by the
master with the longest clock LOW period, and its HIGH period determined by the one with
the shortest clock HIGH period.

GPIO Pin Expansion Using I2C Interface 7

2.7 Arbitration

Arbitration, like synchronization, refers to a portion of the protocol required only if more than
one master will be used in the system. Slaves are not involved in the arbitration procedure. A
master may start a transfer only if the bus is free. Two masters may generate a START
condition within the minimum hold time (t HD : STA ) of the START condition which results in a
valid START condition on the bus. Arbitration is then required to determine which master
will complete its transmission.

Arbitration proceeds bit by bit. During every bit, while SCL is HIGH, each master checks to
see if the SDA level matches what it has sent. This process may take many bits. Two masters
can actually complete an entire transaction without error, as long as the transmissions are
identical. The first time a master tries to send a HIGH, but detects that the SDA level is
LOW, the master knows that it has lost the arbitration and will turn off its SDA output driver.
The other master goes on to complete its transaction.

No information is lost during the arbitration process. A master that loses the arbitration can
generate clock pulses until the end of the byte in which it loses the arbitration and must
restart its transaction when the bus is idle.

If a master also incorporates a slave function and it loses arbitration during the addressing
stage, it is possible that the winning master is trying to address it. The losing master must
therefore switch over immediately to its slave mode.

Figure shows the arbitration procedure for two masters. Of course, more may be involved
depending on how many masters are connected to the bus. The moment there is a difference
between the internal data level of the master generating DATA1 and the actual level on the
SDA line, the DATA1 output is switched off. This will not affect the data transfer initiated by
the winning master.

Figure 2.5 Arbitration procedures of two masters

Since control of the I2C-bus is decided solely on the address and data sent by competing
masters, there is no central master, nor any order of priority on the bus.

There is an undefined condition if the arbitration procedure is still in progress at the moment
when one master sends a repeated START or a STOP condition while the other master is still
sending data.
GPIO Pin Expansion Using I2C Interface 8
3. VERILOG CODE

3.1 Design Block

/*********************************************************************************
I2C to GPIO Port expander
*********************************************************************************/
`timescale 1us/10ns

module I2C_to_GPIO ( sda, sclk, GPIO_input, GPIO_output);

inout sda; // Bidirectional SDA

input sclk; // Input for slave SCLK
input [7:0] GPIO_input;
output [7:0] GPIO_output;
parameter slave_address = 7'h0; // can be changed as per the protocol
parameter n = 8;

reg start_stop; // Indicated if the device has detected a start and is busy in some operation
reg start, stop; // Goes high temporarily when a start or stop is detected
reg some_other_device; // to reset start_stop, when bus address is different from the device
address
reg repeat_start; // to reset everything if repeat start is detected.
reg write_flag; // to set when write operation begins
reg reset; // Used to reset the start , stop registers
reg sda_out; // To force the SDA output Low. remains tristated for sending High Logic.
reg done; // To Indicate data transfer done
reg [3:0]count; // Down Counter ( 7 to 0 + ACK bit )

reg [n-1:0] GPIO_output; // parallel store

reg [n-1:0] GPIO_input_reg; // Stores the Values at the input pins before sending to
master
reg data_or_address; // high for data, low for address
reg sda_ack; // high for acknowledge
reg read_oper; // high for master read
reg add_is_matching; // high for address matching

/********************************************************************************/
// Detecting STOP Condition on the SDA Bus
always @ (posedge sda or posedge reset)
if (reset)
stop <= 0;
else if (sclk)
stop <= 1;

// Detecting START Condition on the SDA Bus

always @ (negedge sda or posedge reset)
if (reset)
start <= 0;
else if (sclk)
start <= 1;
GPIO Pin Expansion Using I2C Interface 9
// Tracking START_STOP related status of the device

always @ (negedge sclk)

if (start_stop & start)
begin
repeat_start <= 1;
reset <= 1;
end
else if (start)
begin
start_stop <= 1;
reset <= 1;
repeat_start <= 0;
end
else if (stop)
begin
start_stop <= 0;
reset <= 1;
repeat_start <= 0;
end
else if (some_other_device)
begin
start_stop <= 0;
repeat_start <= 1;
end
else
begin
reset <= 0;
repeat_start <= 0;
end

/********************************************************************************/

// Counting of bits. First eight bits are data and the last one is ack.

wire sda_is_ack = count[3] & count [2]; // High for ACK , count = 1111

// Down Counter, 1111 is ACK

always @ (negedge sclk)
if (start)
count <= 4'h7; // it would decrease to 7 on the first pos edge of sclk.
else if (start_stop)
begin
if (sda_is_ack)
count <= 4'h7; // count is restored to 7
else
count <= count - 4'h1; // count is decremented until zero.
end

/********************************************************************************/

GPIO Pin Expansion Using I2C Interface 10

// Taking the Inputs from SDA line and Comparing with Address

always @(posedge sclk)

if (start_stop)
begin
if (~sda_is_ack)
begin
sda_ack <= 0;
if (~data_or_address | repeat_start)
begin
if (repeat_start)
begin
add_is_matching <= 1; // high means matching
data_or_address <= 0; // default is address
some_other_device <= 0; // High means that device address does not match with SDA
data
write_flag <= 0;
done <= 0; // Low means Transfer is pending
end
if (count == 7 & sda != slave_address[6]) add_is_matching <= 0;
if (count == 6 & sda != slave_address[5]) add_is_matching <= 0;
if (count == 5 & sda != slave_address[4]) add_is_matching <= 0;
if (count == 4 & sda != slave_address[3]) add_is_matching <= 0;
if (count == 3 & sda != slave_address[2]) add_is_matching <= 0;
if (count == 2 & sda != slave_address[1]) add_is_matching <= 0;
if (count == 1 & sda != slave_address[0]) add_is_matching <= 0;
if (count == 0 & ~sda )
begin
read_oper <= 0;
data_or_address <= 1;
end
else if (count == 0)
begin
read_oper <= 1;
data_or_address <= 1;
end
end
else if (~read_oper & ~done)
begin
if (count == 7) GPIO_output[7] <= sda;
if (count == 6) GPIO_output[6] <= sda;
if (count == 5) GPIO_output[5] <= sda;
if (count == 4) GPIO_output[4] <= sda;
if (count == 3) GPIO_output[3] <= sda;
if (count == 2) GPIO_output[2] <= sda;
if (count == 1) GPIO_output[1] <= sda;
if (count == 0)
begin
GPIO_output[0] <= sda;
done <= 1;
end

GPIO Pin Expansion Using I2C Interface 11

 end
else
if (count == 0) done <= 1;
end
else
begin
if (add_is_matching)
begin
sda_ack <= 1;
if (read_oper) write_flag <= 1;
end
else begin
data_or_address <= 0;
some_other_device <= 1;
end
end
end
else
begin
add_is_matching <= 1; // high means matching
sda_ack <= 0; // high means ACK sent, drives sda low
data_or_address <= 0; // default is address
some_other_device <= 0;
write_flag <= 0;
done <= 0;
end

/********************************************************************************/

// Writing ACK and DATA on the SDA Line

wire ack_flag = (count[3]|count[2]|count[1]|count[0]); //becomes low when count is 0

always@(negedge sclk)
if (start_stop)
begin
if (~ack_flag)
begin
if ( add_is_matching & ~write_flag)
sda_out <= 1'b0;
else
sda_out <= 1'bz;

if (read_oper & ~done) GPIO_input_reg <= GPIO_input;

end
else if (read_oper & data_or_address & ~done)
begin
if (ack_flag)
begin
if (~GPIO_input_reg[7])
sda_out <= 1'b0;

GPIO Pin Expansion Using I2C Interface 12

 else
sda_out <= 1'bz;

GPIO_input_reg <= GPIO_input_reg << 1;

end
end
else
sda_out <= 1'bz;
end

wire sda;
assign sda = sda_out;

endmodule

GPIO Pin Expansion Using I2C Interface 13

3.2 Stimulus Block
/******************************************************************************
Stimulus for I2C to GPIO Port expander.
******************************************************************************** */

`timescale 1us/10ns

module test_I2C_to_GPIO;

reg sclk;
reg [7:0]GPIO_input;

reg start_t;
reg sda_in;
reg ack_check;
reg GPIO_input_check;
reg read_oper_check;
reg write_oper_check;
reg slave_add_check;

wand sda;
wire [7:0] GPIO_input_reg, GPIO_output;
wire [3:0] count;

// Linking module under test

I2C_to_GPIO test (sda, sclk, GPIO_input, GPIO_output);

reg[7:0] GPIO_input_store; //Stores the data from GPIO input line which master wants to read
reg[7:0] GPIO_output_send; //Stores the data which master wants to write at GPIO output line
reg[6:0] slave_add_compare; //For random slave address

integer i = 0;
integer r_seed; // Seed ensures that the same random sequence is generated during every
simulation
parameter tdelay = 3.5 ;
parameter testcycle = 100.0;

assign sda = sda_in;

initial // Generates serial clock of time period 10

begin
sclk = 0;
forever #5 sclk = !sclk;
end

initial
r_seed = 2; // arbitrarily define the seed as 2

GPIO Pin Expansion Using I2C Interface 14

always @(posedge sclk) // Test that slave acknowledges only the correct address
begin

if (slave_add_check & (slave_add_compare != 0000000) & ~sda)

$display(" Slave acknowledging wrong address at time %d", $time);
else if (slave_add_check)
$display("PASS: I2C address check successful at time %d", $time);

if (sda & ack_check)

$display(" Acknowledge Fail at time %d", $time);
else if (ack_check)
$display("Acknowledge recieved correctly %d", $time);

if (write_oper_check & (GPIO_output == GPIO_output_send))

$display ("PASS: I2C Write successful at time %d", $time);
else if (write_oper_check)
$display ("Write Failed at time %d !" , $time);

if (read_oper_check & (GPIO_input == GPIO_input_store))

$display ("PASS: I2C Read successful at time %d", $time);
else if (read_oper_check)
$display ("I2C Read Failed at time %d !" , $time);
end

initial
begin
@(negedge sclk)
$display("Testing for random values");
#tdelay sda_in = 1;
#tdelay sda_in = 0; // For start

// Generate random slave address

slave_add_compare = $random(r_seed);

#tdelay sda_in <= slave_add_compare[6];

#10 sda_in <= slave_add_compare[5];
#10 sda_in <= slave_add_compare[4];
#10 sda_in <= slave_add_compare[3];
#10 sda_in <= slave_add_compare[2];
#10 sda_in <= slave_add_compare[1];
#10 sda_in <= slave_add_compare[0];
#10 sda_in <=1; //For read operation
#10 slave_add_check <= 1;
#10 slave_add_check <= 0;

# testcycle
@ (negedge sclk) //For repeat start
$display ("Starting a write operation", $time);
#tdelay sda_in = 1;
#tdelay sda_in = 0;
#tdelay sda_in = 0; // Sending slave address=0000000

GPIO Pin Expansion Using I2C Interface 15

 #70 sda_in = 0; // For write operation
#10 sda_in = 1;
ack_check <=1;

//For storing a random data which master writes on GPIO output

GPIO_output_send <= $random(r_seed);

#10 ack_check <= 0;

sda_in <= GPIO_output_send[7];
#10 sda_in <= GPIO_output_send[6];
#10 sda_in <= GPIO_output_send[5];
#10 sda_in <= GPIO_output_send[4];
#10 sda_in <= GPIO_output_send[3];
#10 sda_in <= GPIO_output_send[2];
#10 sda_in <= GPIO_output_send[1];
#10 sda_in <= GPIO_output_send[0];
#10 sda_in <= 1;
write_oper_check <= 1;
#10 write_oper_check <= 0 ;

# testcycle
$display("starting a read operation", $time);
@ (negedge sclk) //For repeat start
#tdelay sda_in= 1;
#tdelay sda_in= 0; //Sending slave address=0000000
#75 sda_in <=1; //For read operation
GPIO_input = $random(r_seed);
#5 ack_check <= 1;
#10 ack_check <= 0;

//For Storing the data from sda line which master is reading
#10 GPIO_input_store[7] <= sda;
#10 GPIO_input_store[6] <= sda;
#10 GPIO_input_store[5] <= sda;
#10 GPIO_input_store[4] <= sda;
#10 GPIO_input_store[3] <= sda;
#10 GPIO_input_store[2] <= sda;
#10 GPIO_input_store[1] <= sda;
#10 GPIO_input_store[0] <= sda;
#10 read_oper_check <= 1;
#10 read_oper_check <= 0;

# testcycle
@ (negedge sclk) //For stop
#tdelay sda_in = 0;
#tdelay sda_in = 1;
$display (" End of testcycle, for another random check, run again ");
#10 $stop;
end

endmodule

GPIO Pin Expansion Using I2C Interface 16

4. SIMULATION RESULT
4.1 Simulated Waveform

GPIO Pin Expansion Using I2C Interface 17

Transcript
ModelSim> vsim work.test_I2C_to_GPIO
# vsim work.test_I2C_to_GPIO
# Loading work.test_I2C_to_GPIO
# Loading work.I2C_to_GPIO
add wave sim:/test_I2C_to_GPIO/*
VSIM 4> run -all
# Testing for randoms values
# PASS: I2C address check successful at time 105
# Starting a write operation 220
# Acknowledge recieved correctely 315
# PASS: I2C Write successful at time 405
# starting a read operation 511
# Acknowledge recieved correctly 615
# PASS: I2C Read successful at time 715
# End of testcycle, for another random check, run again
# Break in Module test_I2C_to_GPIO at I:/CDAC Project/GPIO Pin Expansion using
I2C/code/test_I2C_GPIO - Copy.v line 152

GPIO Pin Expansion Using I2C Interface 18

5. SYNTHESIS REPORT
5.1 RTL Schematic

GPIO Pin Expansion Using I2C Interface 19

5.2 Technology Schematic

GPIO Pin Expansion Using I2C Interface 20

5.3 Synthesis Report
// Precision RTL Plus 2011a.61 (Production Release) Fri May 20 13:37:48 PDT 2011
//
// Copyright (c) Mentor Graphics Corporation, 1996-2011, All Rights Reserved.
// Portions copyright 1991-2008 Compuware Corporation
// UNPUBLISHED, LICENSED SOFTWARE.
// CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
// PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
//
// Running on Windows 7 vaio@MYLAPPY 6.01.7600 x86
//
// Start time Thu Jan 26 17:55:00 2012
# -------------------------------------------------
# Info: [9566]: Logging session transcript to file <...>/examples/precision.log
execute -cmd C:/PROGRA~1/MENTOR~1/PRECIS~1.61/Mgc_home/bin/preciseip -dir "C:/Program
Files/Mentor Graphics/Precision_Synthesis 2011a.61/Mgc_home/shared/examples"
new_project -name project_9 -folder "C:/Program Files/Mentor Graphics/Precision_Synthesis
2011a.61/Mgc_home/shared/examples" -createimpl_name project_9_impl_1
add_input_file {{I:/GPIO Pin Expansion Using I2C Interface/GPIO Pin Expansion using I2C
Interface/code/I2C_to_GPIO.v}}
setup_design -manufacturer Xilinx -family SPARTAN2 -part 2s50tq144 -speed -6
setup_design -frequency 100 -input_delay 0 -output_delay 0 -max_fanout=10000
compile
# Info: [3022]: Reading file: <...>/techlibs/xis2.syn.
# Info: [629]: Loading library initialization file <...>/userware/xilinx_rename.tcl
# Info: XILINX
# Info: [40000]: hdl-analyze, Release RTLC-Precision 2011a.9
# Info: [41002]: Analyzing input file "I:/GPIO Pin Expansion Using I2C Interface/GPIO Pin
Expansion using I2C Interface/code/I2C_to_GPIO.v" ...
# Info: [654]: Top module of the design is set to: I2C_to_GPIO.
# Info: [652]: Current working directory: <...>/examples/project_9_impl_1.
# Info: [40000]: RTLC-Driver, Release RTLC-Precision 2011a.9
# Info: [40000]: Last compiled on May 11 2011 20:44:50
# Info: [44512]: Initializing...
# Info: [44504]: Partitioning design ....
# Info: [40000]: RTLCompiler, Release RTLC-Precision 2011a.9
# Info: [40000]: Last compiled on May 11 2011 20:50:54
# Info: [44512]: Initializing...
# Info: [44522]: Root Module I2C_to_GPIO: Pre-processing...
# Warning: [45729]: sda_ack has never been used.
# Info: [44523]: Root Module I2C_to_GPIO: Compiling...
# Info: [44838]: Macro Modgen_Counter "counter_dn_sload_clock_cnt_en_0_4" inferred for node
"count".
# Info: [45193]: Net sda_out is unused after optimization
# Info: [44842]: Compilation successfully completed.
# Info: [44841]: Counter Inferencing === Detected : 1, Inferred (Modgen/Selcounter/AddSub) : 1 (1 /
0 / 0), AcrossDH (Merged/Not-Merged) : (0 / 0), Not-Inferred (Acrossdh/Attempted) : (0 / 0), Local
Vars : 0 ===
# Info: [44856]: Total lines of RTL compiled: 204.
# Info: [44835]: Total CPU time for compilation: 0.5 secs.
# Info: [44513]: Overall running time for compilation: 1.0 secs.
# Info: [652]: Current working directory: <...>/examples/project_9_impl_1.
# Info: [15326]: Doing rtl optimizations.

GPIO Pin Expansion Using I2C Interface 21

# Info: [655]: Finished compiling design.
synthesize
# Info: [652]: Current working directory: <...>/examples/project_9_impl_1.
# Info: [15002]: Optimizing design <...>.I2C_to_GPIO.INTERFACE
# Info: [15002]: Optimizing design <...>.I2C_to_GPIO.INTERFACE
# Info: [8040]: Added global buffer BUFGP for Port port:sclk
# Info: [12045]: Starting timing reports generation...
# Info: [12046]: Timing reports generation done.
# Info: [12047]: POST-SYNTHESIS TIMING REPORTS ARE ESTIMATES AND SHOULD NOT
BE RELIED ON TO MAKE QoR DECISIONS. For accurate timing information, please run place-
and-route (P&R) and review P&R generated timing reports.
# Info: [3027]: Writing file: <...>/project_9_impl_1/I2C_to_GPIO.edf.
# Info: [3027]: Writing file: <...>/project_9_impl_1/I2C_to_GPIO.ucf.
# Info: [655]: Finished synthesizing design.
# Info: [11019]: Total CPU time for synthesis: 0.6 s secs.
# Info: [11020]: Overall running time for synthesis: 0.7 s secs.

GPIO Pin Expansion Using I2C Interface 22

6. CONCLUSION
The design successfully achieves the capability to provide general purpose I/O (GPIO) pin
expansion via an industry standard I2C bus. Since the I2C interface is a two-wire system, the
design provided multiple input and output pins at the remote end with just a common two-
wire trace.

As a result of which design flexibility as well as physical compactness of entire system can
be achieved. It also enables smaller packaging and reduced pin count.

As illustrated by the design, SPARTAN 2 FPGAs are an excellent choice to implement

industry standard interfaces, such as I2C. Their low power and easy power-on-feature make
them ideal FPGA devices to implement applications such as I2C interfaces to provide GPIO
pin expansion.

GPIO Pin Expansion Using I2C Interface 23

7. BIBLIOGRAPHY
References:

1. Samir Palnitkar (1996), Verilog HDL A Guide to Digital Design and Synthesis.

2. Muhammad Ali Mazidi, Sarmad Naimi and Sepher Naimi, The AVR Micro-controller and

Embedded Systems using Assembly and C.

3. NXP Semiconductor, UM10204 I2C-bus Specification and User Manual.

Websites:
1. Altera Corporation http://www.altera.com.

2. Xilinx - http://www.xilinx.com/

GPIO Pin Expansion Using I2C Interface 24