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Chapter 3


3.1 Flow of the Study

The Figure 3.1 below shows the overall process flow in order to achieve

the objectives of the study. Before designing the logic circuit, the researchers

underwent thorough investigation and research on different logic design styles

to compensate for the precharge issue of the NOR based dynamic NAND

decoder from different journals, books, and other related studies to the subject.

Figure 3.1 Process flow chart

This will guide and support the researchers during the actual designing

process. With adequate data and information regarding the basics of decoder

and dynamic logic circuits, the researchers will advance to the first step of the

actual designing process. The designed circuit will then be analyzed if its

operation produces a logic-level low during the precharge phase. If verified, it

is then used to design a 3-to-8 decoder and a 4-to-16 decoder which is then

tested if it obeys the rule of one-hot-decode. When the initial pre-simulation

results are satisfactory, the design will then be implemented in 65nm CMOS

Process technology.

After implementation, various verification step such as design rule

check, layout vs schematic and layout parasitic extraction will then follow.

When verification process is completed, post-simulation results will then be

examined. As stated in the Section 1.4, the parameters to be examined will be

the latency, slew rate, power consumption and cell area. Also, comparison with

the conventional NAND decoder, conventional NOR decoder and the reference

architecture in [1] will be compared and examined. Simulation results will be

then analyzed if the specifications of the objectives were met. The succeeding

sections will discuss on how to achieve the objectives of the study.

3.2 NOR based Dynamic NAND Decoder

Figure 3.2. 2-to-4 NOR decoder

The Figure 3.2 above shows a 2 to 4 NOR decoder, we can observe that

it has a similar structure with the 2 to 4 NAND decoder but instead we used

NOR gates instead of NAND gates with an inverter in the output line. NOR is

used instead of NAND gates due to its inherent advantage from NAND gates

when increasing the number of fan-ins as discussed in [1]. The decoder has two

input lines A and B and four output line R1, R2, R3, and R4. The inputs are

complimented by the two inverters. If input signals A and B are both 0 (00 being

the address for decode line R1), the first NOR gate receives logic 0 in both of

its input and produces a logic 1 signal output. Thus, this device is also known

to be active high because the active state is logic 1. Under the same input

conditions, the remaining NOR gate resolves to logic 0 at decode outputs R2-

R4. The summary of operation of a NOR decoder is summarized in Table 3.1,

this decoder also exhibits a one-hot-decode scheme where only one decode

output is in the logic 1 state.

A B R1 R2 R3 R4

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

Table 3.1. NOR decoder truth table

Figure 3.3 shows the dynamic implementation of the NOR gates used in

the decoder. It consists of a PMOS device in the pull-up network with its source

connected to VDD and its drain connected to the two parallel NMOS device

where the gates are connected to inputs A and B. Another NMOS device whose

source is connected to the ground and its drain connected to the source of the

parallel NMOS, has its gate connected to the clock input same with the PMOS

in the pull-up network. As discussed in dynamic logic, it has two phase of

operation, the precharge and evaluation phase. When the clock goes low

(precharge), the PMOS transistor is conducting and the output of the decode

line is precharged to logic-high level of Vdd. When the clock signal becomes

high (evaluate), the precharge PMOS transistor turns off. As an example, if both
input signals A and B represent both logic 0, both NMOS transistors are turned

off and NOR output (buffered by two inverters) will be at logic-high level Vdd.

Figure 3.3. Dynamic NOR gate

The undesirable characteristic of the dynamic NOR gate is exhibited

during the precharge phase where all the output line would be asserted because

each NOR gate would have an output of logic-high level 1.

3.3 Proposed Three-input Dynamic NOR gate

The key to solving the precharge issue in dynamic NOR gate based

NAND decoder is the by designing a dynamic NOR gate that has a scheme to

compensate for the logic-high output during this stage of operation. In our

objective, we are to design a NOR logic that is at logic low output during the

precharge phase and use it to design a low power and area efficient decoder.
Figure 3.4. Three input NOR gate Table 3.2. Three input NOR gate truth table

Figure 3.4 shows the symbol for a three-input NOR gate with inputs X,

Y and Z and an output line F. Table 3.2 summarizes the output of the logic gate

with different combinations of input logic. This will be the reference used by

the researchers to come up with the design for three-input NOR gate.

Figure 3.5. Proposed three-input domino logic NOR gate architecture equivalent
The equivalent three-input NOR gate equivalent shown in Figure 3.5 is

proposed for this study. This circuit uses the principle of domino logic in the

dynamic circuits where and N-type dynamic logic block is followed by a static

inverter. This scheme is used in cascading dynamic logic where during

precharge, the output of the N-type dynamic gate is charged up to VDD and the

output of the inverter is set to 0. During evaluation, based on the inputs, the

dynamic gate conditionally discharges and the output of the inverter makes a

conditional transition from 0 to 1 [5]. Hence, providing a way for making sure

that the output of the NOR gate during precharge is always set to 0.

Due to the limitation of domino circuits where only non-inverting logic

can be implemented, we used the principles of De Morgans theorem and

performed simple Boolean transformation to our three-input NOR gate so that

we can reorganize the logic gates in such a way we can implement it in domino

logic style [6].

Table 3.3. Truth table for the three-input Domino NOR gate
The Table 3.3 shows the truth table of the three-input Domino NOR

gate, we can see that its final output is similar to a conventional three-input NOR

gate. Hence, we can conclude that somehow our design Domino NOR gate

works the same with a typical NOR gate. This design of a three-input NOR gate

will then be used to construct a 3-to-8 decoder.

Figure 3.6. Three-input domino NOR gate dynamic implementation

The dynamic implementation of the proposed three-input domino NOR

gate is shown in Figure 3.6. where the first two inputs A and B are implemented

on a NOR gate and the third input C is inverted where both of its output are

combined in the succeeding NAND gate and the final output is complimented

in the output line by a static inverter. This design will be used in the

implementation of the study.

3.4 Four-input NOR gate

Figure 3.7. Proposed four-input domino NOR gate.

Table 3.4. Truth table of logic restructured 4-input NOR gate

The proposed four-input domino NOR gate is shown in Figure 3.7 where

the two four inputs A, B, C and D are precoded by two NOR gates, the output

of the first stage is then combined in the NAND gate with the output

complimented by the output static inverter and exhibiting domino logic style.

The truth table of the logic restructured four-input NOR gate is summarized in

Table 3.4 where it shows that the NOR gate will only output a 1 logic when all

of the four inputs are 0. The 4-input NOR gate is restructured to achieve an

equivalent logic circuit shown in figure 3.7, this will be then used to implement

a 4-to-16 decoder.

Figure 3.8. Dynamic implementation of the proposed 4-input NOR gate

The proposed 4-input NOR gate and its dynamic implementation is

shown in Figure 3.8. It consists of two dynamic NOR gates for the four inputs

A, B, C and D. The NAND gate combines the output of the first stage through

the series stack of NMOS in the pull-down network. This circuit is simulated

using 65nm CMOS library to verify its functionality and to confirm the claim

that it has a logic-low level output during the precharge phase.

3.5 3-to-8 and 4-to-16 NOR based NAND Decoder










Figure 3.9 Proposed 3-to-8 Dynamic NOR Decoder

The proposed 3-to-8 dynamic NOR decoder is shown in the Fig. 3.9

where the restructured 3-input domino logic is used to perform the decoding

function. The three inputs A, B, and C and the clock used in the dynamic circuit
are used in combination to produce an output and assert the output line based

on the input address. From this schematic diagram, the specified parameters will

be examined and this schematic diagram of the proposed 3-to-8 NOR decoder

will be laid out on 65 nm CMOS technology using Synopsys Custom Designer.

The truth table for the proposed 3-to-8 NOR decoder will be the same

as with Table 1.1. When the clock is high, the inputs from A, B and C are

resolved by the NOR gate. For example, if all of the input signals A, B and C

represents a logic 0, the address to be asserted will be out0 and so on.

Using the designed 4-input domino logic NOR gate, we can construct

our 4-to-16 decoder shown in Figure 3.10 which is the other focus on this study.

This decoder will be implemented in 65 nm technology in Synopsys Custom

Designer. The size of the transistors is set to minimum or standard cell because

it is one of the properties of dynamic logic that it is non-ratioed.

The truth table of the proposed 4-to-16 decoder is same with the truth

table shown in Table 1.2. The proposed decoder will work the same as the

conventional decoder during the evaluation stage but will be relatively faster

and will consume less power because it is implemented on dynamic logic. The

results and discussions of the verification and implementation of the design will

be discussed further in Chapter 5 of this study.

Figure 3.10 Proposed 4-to-16 Dynamic NOR Decoder

3.6 Dynamic Conventional NAND decoder, Conventional NOR decoder

and Cross-coupled output NOR Decoder [1].

This section discusses about the conventional NAND decoder,

conventional NOR decoder and a cross-coupled output NOR decoder from the

study of Khanna et. Al. These architectures will be simulated under the same

clock and input conditions with the proposed 3-to-8 and 4-to-16 NOR decoder
for reference in this study. The slew rate, power consumption and latency of

these architectures will also be analyzed and compared with our design if it met

the specifications.

3.6.1 Conventional Dynamic NAND Decoder

(a) (b)

Figure 3.11 Dynamic implementation of (a) 3-input NAND (b) 4-input NAND gate

The conventional NAND decoder discussed will be used in the study as

reference, the most basic architecture will be used and the three-input and four-

input dynamic NAND gates are shown in Fig. 3.11a and Fig. 3.11b respectively.

As seen in the figure, as more inputs (fan-in) are added to the decoder, an NMOS

transistor will be added to the series stack. When the clock is 0, the output line

is precharged to Vdd, and when the clock rises up to 1 the logic function of the

pull-down NMOS transistors will be realized [11].

A B C D clk


A B C clk out1


out0 out4

out1 out5


out3 out8


out5 out11

. out12

out7 out14


(a) (b)
Figure 3.12 a) 3-to-8 NAND decoder b) 4-to-16 NAND decoder

Figure 3.12a and Figure 3.12b shows the schematic diagram of a 3-to-8

NAND decoder and a 4-to-16 NAND decoder, respectively. This will be used

in the study as reference. Both of the decoders will be simulated and analyzed

using 65nm technology in Synopsys Custom Designer. These NAND decoder

follows the one-hot-decode rule. If the address input is set to 0000, output line

out0 will turn into logic level 1 while other output lines are kept to logic 0.

Similarly, if the address input is set to 0001, output line out1 will turn to logic

level 1 and other outlines are set to logic 0 and so on.

3.6.2 Conventional Dynamic NOR Decoder

(a) (b)
Figure 3.13 a) 3-input dynamic NOR gate b) 4-input NOR gate

Another architecture to be used for comparison is the conventional

NAND decoder which uses the three-input and four-input dynamic NOR gate

shown in Figure 3.13 and it will also be simulated and tested with the same

conditions with the proposed architecture and with the conventional NAND

decoder. The NOR decoder will be running under the same clock frequency

same with the others (50 MHz) and its latency, slew rate and power

consumption will be tested. Simulation will be done using 65nm technology in

Synopsys Custom Designer. The sizes of the transistors used will also be the

standard size from the library. The 3-to-8 and 4-to-16 decoder architecture on

which these dynamic NOR gates are to beimplemented will also be the same

with Figure 3.9 and Figure 3.10, respectively.

3.6.3 Dynamic NOR Gates for NAND Decode

The study presented by Khanna et. al will also used as a reference for this study.

As stated in the paper, their design has addressed the precharge issue of the

dynamic NOR gates for NAND decode by cross-coupling the output of the NOR

gate and adding an inverter and a NAND gate at the output line to make sure

that the decode line asserts logic 0 when the clock signal is low as shown in

Figure 2.3. This architecture will also be implemented with the same testing and

input conditions with the proposed architecture, conventional dynamic NAND

decoder and conventional dynamic NOR decoder using standard sizes for the

transistors and using a 50 MHz clock frequency. The latency, power

consumption and slew rate of the architecture will be examined.

C B A clk









Figure 3.14 3-to-8 cross-coupled output NOR Decoder

D C B A clk

















Figure 3.15 4-to-16 cross-coupled output NOR decoder.

The Fig. 3.14 and Fig. 3.15 shows the 3-to-8 and 4-to-16 decoders

derived from the study of Khanna et. al which addresses the issue of precharge

for NOR gate based NAND decoder. The process of decoding the input address

into output decode lines were discussed in Section 2.1 of this paper. The paper

initially tested a 2-to-4 decoder, using the principles stated in the reference, we

derived a 3-to-8 and 4-to-16 decoder architecture based on the theory presented.

To verify their claim the researchers will simulate and test the architecture using

the same parameters mentioned earlier to be compared with the proposed

design. Results and discussions will be presented in the next chapter.