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Solar Energy 117 (2015) 180186
www.elsevier.com/locate/solener

Periodically patterned Si pyramids for realizing high ecient solar

cells by wet etching process
Melvin David Kumar a, Hyunyub Kim b, Joondong Kim a,
a
Department of Electrical Engineering, Incheon National University, Incheon 406772, Republic of Korea
b
Research Division, Plansee Korea HPM Inc., Siheung 429926, Republic of Korea

Received 4 March 2015; received in revised form 25 April 2015; accepted 28 April 2015
Available online 16 May 2015

Communicated by: Associate Editor Nicola Romeo

Abstract

Periodic Si structures were designed for a high-ecient solar cell. Wet-etching method was applied to tailor the light-absorbing Si
substrate to periodic patterns. Electrical conductor of a thin indium-tin-oxide (ITO) layer was coated onto the patterned Si structures
as an anti-reection coating layer, which eectively reduces the light-reection at a surface. Due to the optical end electrical benets
of an ITO layer, the periodic Si solar cell provided much improved current density of 36.28 mA/cm2 with a conversion eciency of
16.3%. For quantum eciencies, this ITO-coated periodic Si structure solar cell is enormously eective to improve long-wavelength pho-
tons. This study reveals that eciency of solar cells could be readily enhanced via large-scale available wet-etching processes with an
electrical conductive ITO coating method.
2015 Elsevier Ltd. All rights reserved.

Keywords: Wet etching; Pyramid patterns; Si solar cells; ITO

1. Introduction generates more number of free electrons by absorbing max-

The solar cell research is a hot and higher progressive
research eld for past few decades because of increasing
awareness to pursue the pollutant free energy
(Karni, 2011; Trancik, 2014). An ecient photovoltaic
device is expected to utilize as much incident photons as
possible in order to attain high eciency. Therefore, many
research groups are carrying on their experiments in diver-
sied platforms like Si based solar cells, dye sensitized solar
cells, thin lms solar cells, quantum dot solar cells, etc., to
enhance the eciency (Fonash, 2010; Yaacobi-Gross
et al., 2011; Yum et al., 2014). The main objective of these
experiments is to emerge with a photoelectric device which
Corresponding author.
E-mail address: joonkim@incheon.ac.kr (J. Kim).
imum number of incident photons. In the present article,
the innovative and cost-eective research method to
improve the optical and electrical performances of
Si-based solar cells has been discussed. Inherently, Si has
the low band gap energy of 1.1 eV which leads to limited
light absorption (Hu and Chen, 2007). However, the pat-
terned Si substrates with dierent structures increase the
prociency of the devices due to their low reection and
reduced resistivity (Diaz-Quijada et al., 2011; Huang
et al., 2009; Lee et al., 2013; Mukherjee et al., 2009;
Zeballos et al., 2010). Surface enlargement via patterning
of Si substrates provides the initiative solution to acquire
the enhanced optical and electrical properties. Recently,
few advanced methods such as ion beam lithography, elec-
tron beam lithography and focused ion beam milling have
been used to structure the Si substrates in micro and nano

http://dx.doi.org/10.1016/j.solener.2015.04.034
0038-092X/ 2015 Elsevier Ltd. All rights reserved.
 M.D. Kumar et al. / Solar Energy 117 (2015) 180186
dimensions. Nevertheless, these methods produced better
results only in the small scale fabrications and few results
were found yet with the eciencies more than 15% when
large areas to be structured (Jeong et al., 2013; Krogstrup
et al., 2013; Kulakci et al., 2013). In addition, they are cost
wise expensive. The pattern formations on Si substrates
using chemically etched masks are the most viable and the
best alternative to the above said processes. The most com-
monly used etching processes are wet etching, reactive iron
etching, dry etching and plasma etching. Among them, wet
chemical etching process is the facile and cast eective
method to prepare patterned Si substrates which are used
for potential applications (Peng et al., 2002, 2004). These
benecial structures could be further improved by covering
them with thin layer of anti-reection coating. Especially,
ITO layer is well suited to be coated over the patterned Si
structures due to its unique properties of high transparency,
low resistivity, high carrier concentration, wide energy band
gap and eminent work functions (Schlaf et al., 2001; Yun
et al., 2013; Zhang et al., 2012). Moreover, the ITO layer
can perform various roles such as ohmic contacts, rectifying
junctions, anti-reectors and passivation layer prociently.
In the present work, we have demonstrated the eciency
of 16.3% for wet etched Si pyramid structure. This is rela-
tively higher eciency when compared to 13.7% of all back
contact Si solar cells (Jeong et al., 2013). The defect free
surface, desired patterns to enlarge the surcial length,
adjustable depth to avail maximum light absorption and
short carrier collection length are the important features
of adopting wet etching method in photovoltaic industries.
The characteristics of wet etched Si pyramid structure were
compared to those of at reference Si substrate in the
motive to explore the eectiveness of structured Si sub-
strates and wet chemical etching method. In the present
scenario of photoelectric research, this report would be
more useful for the researchers to fabricate the desired pat-
terns on Si substrates via cost eective methods and to
achieve the improved eciency.
2. Experimental procedure
The Si pyramid structure was patterned on a 4 in.
Chokralsky (CZ) grown 500 lm thick, p-type (1 0 0) Si wafer
having a resistivity of 110 X cm via chemical wet etching.
As a rst step of this process, the Si substrates were masked
with photoresist (PR) pattern which was prepared by spin
coating method at 3000 rpm for 30 s to have 2 lm thick-
nesses. After exposing UV light at 200 W, the PR patterns
were developed. Then SiO2 layer was deposited on the
pre-coated PR pattern to make SiO2 pillar arrays by sputter-
ing method. A lift-o procedure was followed to remove the
template of PR pattern, leaving SiO2 pillar arrays on a Si
substrate. A detailed schematic representation of prepara-
tion method is shown in Fig. 1. The base substrate with
SiO2 mask was undergone wet etching process for 10 min.
The wet-etching solution was prepared by mixing of
NaOH (2.5 wt%) and isopropyl alcohol (5 wt%) in the base
181
of de-ionized water (92.5 wt%). The prepared solution was
maintained at 60 C during the fabrication process. During
the wet etching process, the areas covered by SiO2 mask were
protected from being etched out, resulting in the formation
of periodically patterned Si pyramids. The SiO2 mask was
easily removed by hydrouoric solution after the etching
process. Each Si pyramid has a height of about 2.08 lm with
a width of about 3.5 lm. Then, pn junction was formed by
owing phosphorous oxychloride (POCl3) as an n-type dop-
ing agent, in a furnace at 800 C temperature for 40 min.
After the junction formation, a buered hydrouoric acid
(5% HF) solution was used to remove phosphor silicate glass
(PSG). At this stage, a thin ITO layer of 80 nm thickness was
deposited by supplying the DC power of 300 W to a 4-in.
ITO target (In2O2 containing 10 wt% SnO2) at room temper-
ature (RT) under Ar atmospheric condition using DC sput-
tering system (SNTEK, Korea). The top ITO lm passivates
the n-type doped emitter Si layer and also works as an
anti-reection coating. The prepared samples were tailored
to a size of 3.2  3.2 cm2. For the electrodes purpose, the
Ag paste (Ferro 33-462) and Al paste (Ferro 53-102) were
screen printed on front and back side of the devices respec-
tively. Then, the electrodes were undergone the co-ring pro-
cess in a belt furnace at a temperature of 850 C.
The surface morphology of pyramid structured Si device
was observed by eld emission scanning electron micro-
scope (FESEM, FEI Sirion). The optical properties of the
prepared samples were characterized using UV spectropho-
tometer (Scinco, Neosys-2000). IV characteristics were
analyzed using a simulator system (McScience-K3000)
under one-sun (100 mW/cm2) illumination by using a
power meter (McScience-K101). Quantum eciency
measuring system (McScience-K3100) was employed to
measure internal and external quantum eciencies.
3. Results and discussions
3.1. Structural properties
During the etching process, the time-to-time formations
of Si pyramid structure on the substrate were recorded
using FESEM as shown in Fig. 2(al). From Fig. 1, it is
well seen that the performance of wet-etching process is
perfect in structuring the Si substrates. The uniform array
of Si patterns with identical spacing was observed from
the titled images of the samples. The prepared wet etching
solution is sensitive to etch the portions which are not cov-
ered with SiO2 deposition. Therefore, it has created a depth
of 318 nm around SiO2 coated regions within a minute of
etching time as shown in Fig. 2(a) and (g). When etching
time is increased, the depth also is increased and Si pillar
structures are gradually transformed into accurate pyra-
mids over a time of 10 min. The pyramid structure which
was formed as a result of 10 min wet etching is used for fur-
ther characterizations. The etching depth with respect to
the etching time showed almost linear behavior which is
determined from Fig. 3. There were no sudden changes in
182 M.D. Kumar et al. / Solar Energy 117 (2015) 180186

Fig. 1. Schematic representation of Si pyramid formation in wet etching process.

Fig. 2. The tilted FESEM images of time-to-time wet etched Si pyramid formation for (a) 1 min (b) 2 min (c) 4 min (d) 6 min (e) 8 min (f) 10 min etching
time and the surface images of Si patterns with depth, width and spacing between adjacent structures shown for (g) 1 min (h) 2 min (i) 4 min (j) 6 min (k)
8 min (l) 10 min etching time.

pattern smooth while the other parts of Si substrates were

eroded upon etching. The dimensions of Si patterns with
respect to etching time are given in Table 1. It is inferred
from Table 1 that the bottom of Si patterns progressively
increase and simultaneously, the top portion of the respec-
tive patterns decrease upon increasing etching time. Hence,
the space between Si pillar patterns (Fig. 2(a)) is seemed as
larger than the space between Si pyramids (Fig. 2(f)).

Table 1
Physical dimensions of the prepared samples.
Etching time (min) Width (lm) Depth (lm) Spacing (lm)
Top Bottom
Fig. 3. The etching rate of wet etching process with respect to time. 1 4.33 4.33 0.32 5.31
2 4.72 4.72 0.54 4.88
4 4.82 6.13 0.89 3.70
the depth of the etched patterns. It shows that the prepared 6 3.97 6.62 1.53 3.13
solution has etched the Si substrate with gradual robust- 8 3.59 6.92 2.10 2.70
ness. Signicantly, the top SiO2 keeps the surface of Si 10 3.68 6.40 2.10 3.31
 M.D. Kumar et al. / Solar Energy 117 (2015) 180186
3.2. Optical properties
The optical properties of Si pyramid patterns were
enriched by adopting the top ITO layer coating. The eect
of ITO lms was well replicated in the reectance prole of
the prepared samples as shown in Fig. 4. The optical reec-
tance of wet etched Si pyramids and at Si substrates were
intensively analyzed as a function of wavelength. Both the
samples were coated with a layer of ITO material in order
to reduce the surface reection. Therefore, the reectance
of a at Si substrate without ITO layer was also studied
to understand the eciency of ITO layer in reducing the
optical reection in Si based photoelectric devices. The
average reectance (3001100 nm) of Si substrate without
ITO layer was found to be 36.48%. This was reduced to
14.36% in the at substrate with the ITO layer. Further,
it was reduced to 8.35% when the at substrate is periodi-
cally patterned with wet etching process. Eventually, it is
the good sign that both the ITO coated samples presented
the low average reectance value of lesser than 15%. This is
mainly attributed to the presence of ITO layer which devel-
oped the graded index arrangement to reduce the reectiv-
ity. The refractive indices of air and Si are 1.0 and 3.9
respectively. Since ITO has an intermediate refractive index
value of 1.83 (Zhang et al., 2012), it acts as an ecient
anti-reector and provides minimum reection. From the
present result, it is veried that the minimum reection
oered by ITO layer can be further reduced by means of
patterning the Si substrates using wet etching method. To
be exact, the wet etched Si pyramid structures demon-
strated the lowest reection <10% for broad wavelength
range of 460930 nm and high reection >10% only in
the small wavelength range of 370450 nm. And, the error
bars which are added with the reectance data of Si pyra-
mid structure showed that there is no much deviation from
the standard value of reection.
As a common characteristic, both patterned and at Si
substrates showed the high reectance values at a
Fig. 4. Reectance prole of a at Si substrate, ITO coated at Si
substrate and wet etched pyramidal Si substrate.
183
wavelength of 400 nm and the low reectance values at
600 nm. Sahoo et al. (2009) reported that it is the natural
tendency of Si substrates, exhibiting high reectance at a
wave length of 400 nm. The low reectance value is
obtained at 600 nm due to the optimized thickness of
ITO layer. Since the wavelength of 600 nm is more impor-
tant for Si based photoelectric devices, the thickness of ITO
layer is precisely calculated and adjusted to get the maxi-
mum absorption at this particular wavelength using quar-
ter wavelength formula as given below,
k
d 1
4n
where n is the refractive index of ITO (Zhao et al., 2010).
The calculated thickness for optimized ITO layer is
80 nm. Hence, the reection of prepared samples is rela-
tively low at this wavelength. In general, the wet etched
Si pyramid substrates with ITO coating improves the opti-
cal performance enormously.
3.3. Electrical properties
The photovoltaic characteristics of prepared samples
were studied under one sun illumination (AM 1.5G,
100 mW/cm2). The light JV curves for wet etched Si pyra-
mid and at Si reference devices were shown in Fig. 5. The
wet etched Si pyramid structures provided the highest short
circuit current density (JSC) of 36.28 mA/cm2 with the con-
version eciency of 16.3% which is higher than the previ-
ously reported values (Jeong et al., 2013; Jung et al.,
2012; Kim et al., 2011; H. Kim et al., 2013; J. Kim et al.,
2013; Oh et al., 2012). The error percentage in the current
density is relatively high up to 0.5 V. From Table 2, it is
understood that eciency increases with increasing JSC
value. Surface enhancement is the key factor to determine
the JSC value. Therefore, the patterned substrates showed
higher eciency than the at Si substrate which oered
JSC value of 33.5 mA/cm2 with relatively low eciency of
Fig. 5. Light JV prole under one sun illumination of wet etched Si
pyramid and at Si devices.
184 M.D. Kumar et al. / Solar Energy 117 (2015) 180186
Table 2
Optical and electrical properties of prepared samples.
Devices Reectance (%) Voc (V) Jsc (mA/cm2) Fill factor (%) Eciency (%) Rser (X) Rsht (X) IRS (mA) IF (A) Rectifying ratio ILCD (A/m2)
Pyramid Si 8.35 0.580 36.28 77.1
Flat Si 14.36 0.597 33.5 72.4
14.5%. However, the surface enhancement has slightly
increased the sheet resistance (Rsht) value in the pyramid
structured Si device when compared with that of at
device. As far as concerning the open circuit voltage
(VOC) values, both the prepared devices yielded approxi-
mately similar values of 0.580.60 V. Kim et al. predicted
that the upgraded VOC values are the result of fair forma-
tion of space charge region (SCR) in ITO/n-Si solar cells.
Hence, it is understood that both patterned and at devices
were sealed with fair SCR in between Si substrate and ITO
layer. In abrupt pn junction formation, the doping density
of donor region will be reduced with increasing distance
from the surface. In the present work, the donor concentra-
tion is matched with the acceptor concentration at 400 nm
depth from top (Kim et al., 2015). As the Si pyramids were
fabricated with 2 lm depth, the space charge region (SCR)
appeared at few nanometer distance from the top of each
pyramid.
The diode characteristics of prepared samples were ana-
lyzed from experimentally measured IV proles under
dark condition as shown in Fig. 6. The lowest reverse sat-
uration (IRS) current of 1.39 mA at 0.8 V was exhibited
by the wet etched Si pyramid structure device. The IRS
value is mainly attributed to the surface defects and leakage
current density of the device. In general, the etching pro-
cesses increase the surface defects thereby increasing the
IRS value which will degrade the device performance
(Ferry et al., 2011; Seo et al., 2013; Wallentin et al.,
2013). However, the wet etching method has reduced the
IRS eectively as compared to the at Si device. The reason
for large IRS value of at Si device is the leakage current
density which is claried from Table 2 that Si pyramid
Fig. 6. Dark IV prole of wet etched Si pyramid and at Si devices.
16.3 0.133 308.72 1.39 2.473 1779 0.14
14.5 0.180 216.4 2.56 3.749 1464 0.26
structures produced by wet etching method has less surface
defects rather than that of at Si substrate. Under the for-
ward bias, the at Si substrate showed the highest forward
current (IF) of 3.749 A at +0.8 V. To get the clear portrait,
the rectifying ratios were calculated from the ratio of cur-
rent value at +0.8 V to the current value at 0.8 eV. The
wet etched Si substrate has the highest rectication ratio
of 1779 because of increased light reactive surface area.
The rectiying ratio of at Si device is found lower
(1464) due to its high IRS value. Based on dark IV analy-
sis, the follwing predictions are proposed. The wet etching
method suppresses the surface defect so that the amount of
leakage current is reduced. The passivation eect of ITO is
more enunciated in wet etching method rather than in at
Si substrate.
The photovoltaic characteristics of the prepared devices
are further analyzed by the studies of external and internal
quantum eciencies (EQE & IQE). The EQE and IQE pro-
les of wet etched Si pyramid and ITO coated at Si
devices were shown in Fig. 7(a) and (b) respectively. Both
devices oered better eciencies but with signicant dier-
ences. The EQE values of the samples attained maximum
at a wavelength of 600 nm due to greater optical absorp-
tion of ITO layer at this region. Followed by 600 nm, the
EQE of at Si device was gradually decreased whereas
the EQE of wet etched Si device maintained an improved
eciency status (>85%) over a broad wavelength range
of 550950 nm. The wavelength region between 600 and
900 nm is the most substantial zone for Si based photoelec-
tric applications (Guo et al., 2012; Han and Chen, 2010).
The stability of EQE over wide range of wavelengths is
observed for pyramid structured Si device. Moreover, as
compared to at Si device, the Si pyramid structures navi-
gate more number of incident photons into pn junction
and consequently increase the carrier collection eciency
(Cho et al., 2014). The EQE prole reects how the device
interacts with the incident light in terms of absorption and
reection. Hence, it is clearly observed that the EQE prole
of the prepared devices follow the same trend as they
followed in the reectance prole. Specically, at
k = 600 nm, both the devices showed the minimum reec-
tance compared to other wavelength region. However, fol-
lowed by the wavelength of 600 nm, the reectance of the
at Si device increased than that of pyramid structured Si
device. Therefore, the EQE of pyramid structured device
has improved after 600 nm. There is an abrupt reduction
observed in the EQE values of the prepared devices at near
infrared (NIR) region. This is caused by the optical losses
due to the free carrier absorption of TCO at the longer
wavelengths (Kim et al., 2011). The EQE of a photovoltaic
 M.D. Kumar et al. / Solar Energy 117 (2015) 180186
Fig. 7. (a) External and (b) internal quantum eciencies as a function of wavelengths of Si pyramid and at Si devices.
device is commonly aected by the external factors such as
reections and absorptions, while the IQE depends only on
the number of absorbed photons which are incident on the
junction rather than the device (Yang et al., 2008). As it is
independent of reection and absorption, the IQE values
always exceed the EQE values over a broad spectral range
(Koida et al., 2009; Yoo et al., 2009). From Fig. 7(b), it is
observed that both the devices showed better eciency
over a wide range of wavelengths. The IQE of wet etched
Si device reached 93% at k = 600 nm and then gradually
increased to attain maximum value of 98% at k  830 nm.
In contradict to this, the at Si device attained maximum
value at k = 600 nm and then gradually decreased when
wavelength increases. Hence, the carrier collection and sep-
aration eciency of wet etched Si pyramid device spreads
over broad spectral range as compared to at Si device.
The error bars in the middle range of wavelengths
(500950 nm) showed the maximum deviation in the e-
ciencies compared to the other wavelength regions. In
general, patterned Si devices presented improved EQE
and IQE prole than those of at Si device. In particular,
the quantum eciencies of the at Si device can be further
enhanced by patterning the Si substrate into pyramid
structures.
4. Conclusion
Pyramid pattern and at Si devices were considered for
characterization and discussion. The wet etching method
was employed to make pyramid structures on the Si sub-
strate. Both the prepared samples were coated with ITO
layer of 80 nm thickness. The wet etched Si pyramid device
provided the minimum average reectance of 8.35%. Also,
the highest short circuit current density of 36.28 mA/cm2
with the high conversion eciency of 16.3% was exhibited
by wet etched Si device. Since the leakage current density of
wet etching processed Si device is comparatively low, it is
understood that surface defects during the etching process
will also be low. The EQE and IQE of pyramid patterned
Si device were improved over wide range of wavelengths
as compared to at Si device. This result showed that the
185
reduced surface defects, improved reectance, upgraded
current rectifying ratio, enhanced quantum and conversion
eciencies are the promising advantages of the simple wet
etching method.
Acknowledgements
The authors acknowledge the nancial support of the
Korea Institute of Energy Technology Evaluation and
Planning, in a grant funded by the Ministry of Knowledge
and Economy (KETEP-20133030011000), and Business
for Cooperative R&D between Industry, Academy, and
Research Institute funded Korea Small and Medium
Business Administration (C0219153). M.D. Kumar and
H. Kim equally contributed to this work.
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