Data Path Design

Dr DC Hendry

April 20, 2006

1 RTL Notation

RTL Notation

Remember: this is not a computer language, but a pen and paper notation!

1. For a register capture, i.e., when a register captures a result at the end of
the clock cycle use:
Rtarget expression
where expression is any Boolean or other expression indicating the com-
putation involved.
2. For a signal S to be computed during the clock cycle (often the output of
an FSM), use the notation:
S =< expression >

Clock Cycles

1. During different clock cycles different register transfers will generally oc-
cur.
2. All transfers that occur during one clock cycle are grouped together under
one name.
3. Such clock cycles will proceed in a sequence that is indicated using a right
arrow, thus each clock cycle description will end with a statement such as
cyclename.
4. Conditional statements allow choice between alternative succeeding clock
cycles.
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2 Example

Max/Min Circuit

1. Suppose a circuit is required to compute the maximum and minimum

value of groups of four unsigned numbers that are supplied serially, one
per clock cycle, to the circuit.
2. Four registers will be used, two will contain the maximum and minimum
value for the last group of four numbers seen, two will contain the maxi-
mum and minimum value seen so far in the current group of four numbers.
3. One clock cycle, a reset clock cycle, will be used to start the machine.

The Reset Clock Cycle

1. This clock cycle is simply described in RTL notation by:

cycle_reset {
min <- (others => 1);
max <- (others => 0);
-> cycle_1
}

2. Where VHDL notation is appropriate use this, it will ease the later con-
version of the design to synthesisable VHDL.

Cycles 1, 2 and 3

1. For the first three numbers read from the input (assume that the input is
available via a register called din), the same procedure is followed.
2. So the RTL for these cycles is:

cycle_1 {
if din > max then
max <- din;
if din < min then
min <- din;
-> cycle_2;
}

3. Cycles 2 and 3 are identical except of course for the succeeding cycle.

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Cycle 4

1. The final cycle must update the output registers and reset the min and
max so far.
2. cycle_4 {
if din > max then
out_max <- din;
else
out_max <- max;
end if;
if din < min then
out_min <- din;
else
out_min <- min;
end if;
min <- (others => 1); max <- (others => 0);
}

Status Signals

1. Status lines from the datapath to the controller will be the outputs of the
two comparators implied by the expressions in the if statements. Call
these dmax and dmin.

din din
dmax dmin
2.

max min

Internal Control Signals

1. For this design, internal control signals are required for register load en-
ables, and for multiplexor select signals.
2. Register load enables are required whenever a register conditionally loads
data within any clock cycle.

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3. So register load enable lines are required for each of the four registers, call
these lmin, lmax, lomin and lomax.
4. To reset/set the min and max registers add a set line to the min register
and a reset line to the max register, these are also then internal control
signals.

Multiplexors

1. Multiplexors are required whenever one component has to be driven by

more than one source (assuming buses are not used).
2. These can be identified simply by looking for the same target appearing
in transfers with different sources.
3. In this design this applies to the registers out min and out max.
4. Each of these registers has two possible sources of data, so two 2 to 1
multiplexors needed, call the select lines smin and smax.

5. So these also become outputs of the controller.

Circuitry Around Max and Out max

din

1
> dmax out_
max
0
max
smax

Circuitry Around Min and Out min

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din

1
> dmin out_
min
0
min
smin

The Controller

1. The FSM constituting the controller has five states, cycle reset, cycle 1,
cycle 2, cycle 3 and cycle 4.
2. The inputs are dmin and dmax.
3. The outputs are smin, smax, lmin, lmax, lomin, lomax, setmin and
rstmax.
4. Note that the outputs depend upon the inputs (a consequence of how the
RTL was written) so a Mealy machine is needed.

Unassigned State Table

1. The complete table is simplified by the fact that the next state does not in
this case depend upon any inputs, only the outputs in fact depend upon
the inputs.
2. Since we have two inputs, four columns would be needed per output using
the textbook format. This would mean 24 columns.
3. An alternative format is useful in which each current state is repeated
with different values of the inputs as needed.
4. For this example it may be easier to skip the state table and go straight
to VHDL.

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Unssigned State Table

Current Next

lomax
lomin
dmax

smax
dmin

lmax

smin
lmin
State State
cycle reset cycle 1 - - 0 0 0 0 - -
cycle 1 cycle 2 0 0 0 0 0 0 - -
0 1 0 1 0 0 - -
1 0 1 0 0 0 - -
1 1 1 1 0 0 - -

State Diagram

The state diagram, omitting inputs and outputs is:

cycle cycle cycle cycle cycle

reset 1 2 3 4

VHDL Code

1. The controller code is constructed using typical finite state machine meth-
ods. Two processes are used, one for the the state register, the second for
the next state logic and the output logic.
2. The controller is then instantiated as a subcomponent within the over-
all design. Data registers, comparators and muxes are constructed using
concurrent assignement statements (or processes) within the single archi-
tecture body.

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