File Input and Output

Dr DC Hendry

May 4, 2006

1 File Declarations

Lets be clear from the outset, input/output to a file in VHDL is only used in
simulation code, it is never synthesised. Further, the file handling mechanism
in VHDL is primitive compared to that provided in a language such as C++.

1. File input/output is only used in simulation code. In many simulations

data may be written to file for later analysis, or data to drive the simulation
may be read from file.
2. File input/output is not synthesisable!!
3. The mechanisms provided for file input/output in VHDL are primitive
compared to those found in say C++.
4. There are differences between VHDL 87 and VHDL 93 that are not back-
ward compatible.
5. Some additional features are added in VHDL 93 (particularly the attribute
image that does ease output).

1. Only VHDL 93 style will be discussed, and only files of text will be con-
sidered. Other approaches are usually non-portable (that is, cannot be
transferred from one simulation system to another).
2. Another declaration, that may appear in the declarations section of an
architecture, process, function or procedure is available.
3. The additional package textio from library STD is required. Note that
library STD is always available, so we simple need:

use std.textio.all;
 File Handling

to preceed the relevant design unit.

1. You can either declare the file simply as:

file simdata : text;

where simdata is the name created for this file, and text is the type
declared in std.textio.all. Then open the file using file open.
2. or declare and open the file at the same time. This is simplest if the file
is to be read only once.

file simdata : text open READ MODE is sim.dat;

1. Text files are read/written line at a time. Each line is read into a buffer
of type LINE.
2. When writing text files, data is first written to a buffer of type LINE and
then that buffer is written to the output file.
3. Some typical declarations of line buffers:

ptest : process is
variable inline : line;
variable outline : line;

4. A line is read with readLine(simData, inline);

5. A line is written with writeLine(outData, outline);

1. Objects of type line keep track of how much data has been read from the
line using the supplied reading procedures.
2. The procedure read is overloaded to permit reading of a variety of data
types.
3. The procedure is called as read(inline, target ); or as read(inline,
target, good); where good is a Boolean indicating a successful read.
4. Versions of read are supplied in std.textio for targets of type BIT,
BIT VECTOR, BOOLEAN, CHARACTER, INTEGER, REAL, STRING and TIME.
5. Package std logic textio extends read to also read in STD LOGIC and
STD LOGIC VECTOR. Versions are also available to read/write in hexadeci-
mal and octal formats.

Revision : 1.1 Page 2 of 4 Dr DC Hendry

 File Handling

2 File Copying Example

-
Title : filecopy in VHDL
Project : EG3560
-

use std.textio.all;

entity filecopy is
generic(
infilename : string := "indat.txt";
outfilename : string := "outdat.txt");
end filecopy;

architecture sim of filecopy is

file infile : text open READ MODE is infilename;
file outfile : text open WRITE MODE is outfilename;
begin sim
fcopy: process
variable l : line;
begin process fcopy
while not endfile(infile) loop
readline(infile, l);
writeline(outfile, l);
end loop;
file close(infile);
file close(outfile);
wait;
end process fcopy;
end sim;

The File Copy Program ...

1. Note the use of generics as file names. While not required, it does mean
that the file name can be modified at elaboration time, not requiring
modification of the source code.
2. The procedure endfile may be applied to any file to determine if all data
has already been read from that file.
3. Note how the one line buffer may be used for reading or for writing.
4. The procedure file close may be used to close a file. It is not necessary
as all files will be closed at the end of the simulation, but should be used
nevertheless.

Revision : 1.1 Page 3 of 4 Dr DC Hendry

 File Handling

3 Testing the Adder Example

File driven test of adder

1. Well return to the adder example and construct a testbench which reads
the input data and expected outputs from a file.
2. Such a testbench might be used where all possible inputs to the adder
would take too long to simulate, and only a selected set of inputs, chosen
by some other software, are to be used.
3. Such a testbench may also be used for other purposes, for example, a
different set of test inputs may be used to estimate the power dissipation
of the design.
4. This is a common approach to take when testing a new processor design,
the input file would be the output of the assembler/compiler for the new
processor.

Library Clauses and Entity Header

library ieee;
use ieee.std logic 1164.all;
use ieee.std logic textio.all;
use std.textio.all;

entity adderNbit tb is
generic(infilename : string := "adderdat.txt");

end adderNbit tb;

Revision : 1.1 Page 4 of 4 Dr DC Hendry