Simple

Entities and
Architectures

Dr DC Hendry

Entity
Declarations
GENERICs Simple Entities and Architectures
Types BIT and
BIT VECTOR

Architecture
Bodies
Architecture
Dr DC Hendry
Declarations
Concurrent
Statements

The IEEE
1164 Package
January 2006
 Simple
Entities and
Architectures

Dr DC Hendry 1 Entity Declarations

Entity GENERICs
Declarations
GENERICs

Types BIT and

BIT VECTOR
2 Types BIT and BIT VECTOR
Architecture
Bodies
Architecture
Declarations
3 Architecture Bodies
Concurrent
Statements
Architecture Declarations
The IEEE Concurrent Statements
1164 Package

4 The IEEE 1164 Package

 Entity Declarations

Simple
Entities and
Architectures entity example2 is
Dr DC Hendry port(
A, B, C : in bit;
Entity
Declarations X, Y : out bit);
GENERICs

Types BIT and

end entity example2;
BIT VECTOR

Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Entity Declarations

Simple
Entities and
Architectures entity example2 is
Dr DC Hendry port(
A, B, C : in bit;
Entity
Declarations X, Y : out bit);
GENERICs

Types BIT and

end entity example2;
BIT VECTOR

Architecture
Bodies
Architecture
Declarations
1 The entity declaration gives a name to the design and tells
Concurrent
Statements
us the signals which are input and output from the design.
The IEEE
1164 Package
 Entity Declarations

Simple
Entities and
Architectures entity example2 is
Dr DC Hendry port(
A, B, C : in bit;
Entity
Declarations X, Y : out bit);
GENERICs

Types BIT and

end entity example2;
BIT VECTOR

Architecture
Bodies
Architecture
Declarations
1 The entity declaration gives a name to the design and tells
Concurrent
Statements
us the signals which are input and output from the design.
The IEEE 2 Each input or output signal is given a name (such as A, B
1164 Package
or C), also a direction, and a type.
 Entity Declarations

Simple
Entities and
Architectures entity example2 is
Dr DC Hendry port(
A, B, C : in bit;
Entity
Declarations X, Y : out bit);
GENERICs

Types BIT and

end entity example2;
BIT VECTOR

Architecture
Bodies
Architecture
Declarations
1 The entity declaration gives a name to the design and tells
Concurrent
Statements
us the signals which are input and output from the design.
The IEEE 2 Each input or output signal is given a name (such as A, B
1164 Package
or C), also a direction, and a type.
3 The direction is either IN or OUT (other choices are also
available but should be avoided for synthesis).
 Entity Declarations

Simple
Entities and
Architectures entity example2 is
Dr DC Hendry port(
A, B, C : in bit;
Entity
Declarations X, Y : out bit);
GENERICs

Types BIT and

end entity example2;
BIT VECTOR

Architecture
Bodies
Architecture
Declarations
1 The entity declaration gives a name to the design and tells
Concurrent
Statements
us the signals which are input and output from the design.
The IEEE 2 Each input or output signal is given a name (such as A, B
1164 Package
or C), also a direction, and a type.
3 The direction is either IN or OUT (other choices are also
available but should be avoided for synthesis).
4 A large number of types are available, such as BIT,
INTEGER or BIT VECTOR.
 The same example again ..

Simple
Entities and
Architectures

Dr DC Hendry
entity example2 is
Entity
Declarations
port(
GENERICs -- Inputs
Types BIT and
BIT VECTOR
A : in bit;
Architecture B : in bit;
Bodies
Architecture
C : in bit;
Declarations
Concurrent -- Outputs
Statements

The IEEE
X : out bit;
1164 Package Y : out bit);
end entity example2;
 The same example again ..

Simple
Entities and
Architectures

Dr DC Hendry
1 VHDL is case insensitive, so X is the same as x.
Entity
Declarations
GENERICs

Types BIT and

BIT VECTOR

Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 The same example again ..

Simple
Entities and
Architectures

Dr DC Hendry
1 VHDL is case insensitive, so X is the same as x.
Entity
Declarations
GENERICs
2 Input output signals may be listed individually (the
Types BIT and preferrred approach) or more than one to a line.
BIT VECTOR

Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 The same example again ..

Simple
Entities and
Architectures

Dr DC Hendry
1 VHDL is case insensitive, so X is the same as x.
Entity
Declarations
GENERICs
2 Input output signals may be listed individually (the
Types BIT and preferrred approach) or more than one to a line.
BIT VECTOR
3 Comments are usefully embedded within the syntax,
Architecture
Bodies remember a comment extends to the end of the line.
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 The same example again ..

Simple
Entities and
Architectures

Dr DC Hendry
1 VHDL is case insensitive, so X is the same as x.
Entity
Declarations
GENERICs
2 Input output signals may be listed individually (the
Types BIT and preferrred approach) or more than one to a line.
BIT VECTOR
3 Comments are usefully embedded within the syntax,
Architecture
Bodies remember a comment extends to the end of the line.
Architecture
Declarations
Concurrent
4 The final line above, end entity example2; is VHDL-93
Statements

The IEEE
syntax, VHDL-87 syntax would be end example2;.
1164 Package
 The same example again ..

Simple
Entities and
Architectures

Dr DC Hendry
1 VHDL is case insensitive, so X is the same as x.
Entity
Declarations
GENERICs
2 Input output signals may be listed individually (the
Types BIT and preferrred approach) or more than one to a line.
BIT VECTOR
3 Comments are usefully embedded within the syntax,
Architecture
Bodies remember a comment extends to the end of the line.
Architecture
Declarations
Concurrent
4 The final line above, end entity example2; is VHDL-93
Statements

The IEEE
syntax, VHDL-87 syntax would be end example2;.
1164 Package
5 To request VHDL-93 syntax with the Cadence simulation
tools use ncvhdl -v93 ...
 Generics

Simple
Entities and
Architectures

Dr DC Hendry
1 Certain designs may represent a range of components that
Entity
Declarations differ only in for example the number of bits processed.
GENERICs

Types BIT and

BIT VECTOR

Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Generics

Simple
Entities and
Architectures

Dr DC Hendry
1 Certain designs may represent a range of components that
Entity
Declarations differ only in for example the number of bits processed.
GENERICs

Types BIT and

2 An example would be an adder. Such a design might be a
BIT VECTOR
1-bit adder, a 2-bit adder or a 16-bit adder.
Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Generics

Simple
Entities and
Architectures

Dr DC Hendry
1 Certain designs may represent a range of components that
Entity
Declarations differ only in for example the number of bits processed.
GENERICs

Types BIT and

2 An example would be an adder. Such a design might be a
BIT VECTOR
1-bit adder, a 2-bit adder or a 16-bit adder.
Architecture
Bodies 3 Sucn an integer is called a generic in VHDL.
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Generics

Simple
Entities and
Architectures

Dr DC Hendry
1 Certain designs may represent a range of components that
Entity
Declarations differ only in for example the number of bits processed.
GENERICs

Types BIT and

2 An example would be an adder. Such a design might be a
BIT VECTOR
1-bit adder, a 2-bit adder or a 16-bit adder.
Architecture
Bodies 3 Sucn an integer is called a generic in VHDL.
Architecture
Declarations
Concurrent
4 Generics are always input to a design, and so no direction
Statements
such as IN or OUT is supplied.
The IEEE
1164 Package
 Generics

Simple
Entities and
Architectures

Dr DC Hendry
1 Certain designs may represent a range of components that
Entity
Declarations differ only in for example the number of bits processed.
GENERICs

Types BIT and

2 An example would be an adder. Such a design might be a
BIT VECTOR
1-bit adder, a 2-bit adder or a 16-bit adder.
Architecture
Bodies 3 Sucn an integer is called a generic in VHDL.
Architecture
Declarations
Concurrent
4 Generics are always input to a design, and so no direction
Statements
such as IN or OUT is supplied.
The IEEE
1164 Package 5 A range of types may be used, but for synthesisable
designs, type INTEGER should be used at present.
 Generic Example

Simple
Entities and
Architectures

Dr DC Hendry

entity example3 is
Entity
Declarations generic(
GENERICs

Types BIT and

N : integer;
BIT VECTOR M : integer);
Architecture port(
Bodies
Architecture
Declarations
.
Concurrent
Statements .
The IEEE );
1164 Package
end entity example3;
 Type BIT

Simple
Entities and
Architectures

Dr DC Hendry
1 Signals of type BIT may take one of two values only, either
Entity
Declarations 0 or 1.
GENERICs

Types BIT and

BIT VECTOR

Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Type BIT

Simple
Entities and
Architectures

Dr DC Hendry
1 Signals of type BIT may take one of two values only, either
Entity
Declarations 0 or 1.
GENERICs

Types BIT and

2 These values must be written in quotes, simply writing 0
BIT VECTOR
or 1 is incorrect.
Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Type BIT

Simple
Entities and
Architectures

Dr DC Hendry
1 Signals of type BIT may take one of two values only, either
Entity
Declarations 0 or 1.
GENERICs

Types BIT and

2 These values must be written in quotes, simply writing 0
BIT VECTOR
or 1 is incorrect.
Architecture
Bodies 3 0 and 1 are values that a signal of type BIT may take.
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Type BIT

Simple
Entities and
Architectures

Dr DC Hendry
1 Signals of type BIT may take one of two values only, either
Entity
Declarations 0 or 1.
GENERICs

Types BIT and

2 These values must be written in quotes, simply writing 0
BIT VECTOR
or 1 is incorrect.
Architecture
Bodies 3 0 and 1 are values that a signal of type BIT may take.
Architecture
Declarations
Concurrent
4 0 and 1 are values that a signal of type INTEGER may take.
Statements

The IEEE
1164 Package
 Type BIT

Simple
Entities and
Architectures

Dr DC Hendry
1 Signals of type BIT may take one of two values only, either
Entity
Declarations 0 or 1.
GENERICs

Types BIT and

2 These values must be written in quotes, simply writing 0
BIT VECTOR
or 1 is incorrect.
Architecture
Bodies 3 0 and 1 are values that a signal of type BIT may take.
Architecture
Declarations
Concurrent
4 0 and 1 are values that a signal of type INTEGER may take.
Statements

The IEEE
5 To assign a value to a signal X of type BIT we can say:
1164 Package

X <= 1;
 Type BIT VECTOR

Simple
Entities and Very often we wish to work with signals which do not consist of
Architectures
single bits, but consist of a number of bits, for example an
Dr DC Hendry
address bus, or a data bus.
Entity
Declarations 1 A 32 bit address might be declared in a port list using:
GENERICs
address : in bit vector(31 downto 0);
Types BIT and
BIT VECTOR

Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Type BIT VECTOR

Simple
Entities and Very often we wish to work with signals which do not consist of
Architectures
single bits, but consist of a number of bits, for example an
Dr DC Hendry
address bus, or a data bus.
Entity
Declarations 1 A 32 bit address might be declared in a port list using:
GENERICs
address : in bit vector(31 downto 0);
Types BIT and
BIT VECTOR 2 It might also be declared using:
Architecture
Bodies
address : in bit vector(0 to 31);
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Type BIT VECTOR

Simple
Entities and Very often we wish to work with signals which do not consist of
Architectures
single bits, but consist of a number of bits, for example an
Dr DC Hendry
address bus, or a data bus.
Entity
Declarations 1 A 32 bit address might be declared in a port list using:
GENERICs
address : in bit vector(31 downto 0);
Types BIT and
BIT VECTOR 2 It might also be declared using:
Architecture
Bodies
address : in bit vector(0 to 31);
Architecture
Declarations 3 Individual bits may be assigned using:
Concurrent
Statements address(12) <= 1;
The IEEE
1164 Package
 Type BIT VECTOR

Simple
Entities and Very often we wish to work with signals which do not consist of
Architectures
single bits, but consist of a number of bits, for example an
Dr DC Hendry
address bus, or a data bus.
Entity
Declarations 1 A 32 bit address might be declared in a port list using:
GENERICs
address : in bit vector(31 downto 0);
Types BIT and
BIT VECTOR 2 It might also be declared using:
Architecture
Bodies
address : in bit vector(0 to 31);
Architecture
Declarations 3 Individual bits may be assigned using:
Concurrent
Statements address(12) <= 1;
The IEEE
1164 Package 4 The entire vector may be assigned using:
address <=
10101110010110101110011001110010;
 Type BIT VECTOR

Simple
Entities and Very often we wish to work with signals which do not consist of
Architectures
single bits, but consist of a number of bits, for example an
Dr DC Hendry
address bus, or a data bus.
Entity
Declarations 1 A 32 bit address might be declared in a port list using:
GENERICs
address : in bit vector(31 downto 0);
Types BIT and
BIT VECTOR 2 It might also be declared using:
Architecture
Bodies
address : in bit vector(0 to 31);
Architecture
Declarations 3 Individual bits may be assigned using:
Concurrent
Statements address(12) <= 1;
The IEEE
1164 Package 4 The entire vector may be assigned using:
address <=
10101110010110101110011001110010;
5 When declaring vectors, the downto form is preferred, as
the high bit numbers are the most significant bits.
 Type INTEGER

Simple
Entities and
Architectures

Dr DC Hendry

Entity
Declarations
GENERICs
1 Type INTEGER is normally used for Generic parameters,
Types BIT and and within testbenches, it is not used for data to be
BIT VECTOR
processed by the design.
Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Type INTEGER

Simple
Entities and
Architectures

Dr DC Hendry

Entity
Declarations
GENERICs
1 Type INTEGER is normally used for Generic parameters,
Types BIT and and within testbenches, it is not used for data to be
BIT VECTOR
processed by the design.
Architecture
Bodies
Architecture
2 For representing bit patterns which represent integers,
Declarations
Concurrent
other types are available which include synthesis support
Statements

The IEEE
for basic arithmetic and other manipulation.
1164 Package
 Architecture Bodies

Simple
Entities and
Architectures 1 The architecture body describes the internal operation of
Dr DC Hendry
the design.
Entity
Declarations
GENERICs

Types BIT and

BIT VECTOR

Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Architecture Bodies

Simple
Entities and
Architectures 1 The architecture body describes the internal operation of
Dr DC Hendry
the design.
Entity 2 For a simple combinational logic design this will provide a
Declarations
GENERICs description of the Boolean functions needed to compute
Types BIT and
BIT VECTOR
the outputs based on the inputs.
Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Architecture Bodies

Simple
Entities and
Architectures 1 The architecture body describes the internal operation of
Dr DC Hendry
the design.
Entity 2 For a simple combinational logic design this will provide a
Declarations
GENERICs description of the Boolean functions needed to compute
Types BIT and
BIT VECTOR
the outputs based on the inputs.
Architecture 3 For a more complex design it may be advantageous to first
Bodies
Architecture describe the design at a very high level (c.f. levels of
Declarations
Concurrent
Statements
abstraction).
The IEEE
1164 Package
 Architecture Bodies

Simple
Entities and
Architectures 1 The architecture body describes the internal operation of
Dr DC Hendry
the design.
Entity 2 For a simple combinational logic design this will provide a
Declarations
GENERICs description of the Boolean functions needed to compute
Types BIT and
BIT VECTOR
the outputs based on the inputs.
Architecture 3 For a more complex design it may be advantageous to first
Bodies
Architecture describe the design at a very high level (c.f. levels of
Declarations
Concurrent
Statements
abstraction).
The IEEE 4 There is usually one architecture body which describes the
1164 Package
design at a level acceptable to a synthesis tool - the RTL
level architecture body.
 Architecture Bodies

Simple
Entities and
Architectures 1 The architecture body describes the internal operation of
Dr DC Hendry
the design.
Entity 2 For a simple combinational logic design this will provide a
Declarations
GENERICs description of the Boolean functions needed to compute
Types BIT and
BIT VECTOR
the outputs based on the inputs.
Architecture 3 For a more complex design it may be advantageous to first
Bodies
Architecture describe the design at a very high level (c.f. levels of
Declarations
Concurrent
Statements
abstraction).
The IEEE 4 There is usually one architecture body which describes the
1164 Package
design at a level acceptable to a synthesis tool - the RTL
level architecture body.
5 Thus more than one architecture body may describe the
same design.
 Architecture Body Syntax

Simple
Entities and
Architectures This is the (very) general format of an architecture body:
Dr DC Hendry
architecture rtl of example4 is
Entity
Declarations
GENERICs List of Architecture Declarations
Types BIT and
BIT VECTOR

Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Architecture Body Syntax

Simple
Entities and
Architectures This is the (very) general format of an architecture body:
Dr DC Hendry
architecture rtl of example4 is
Entity
Declarations
GENERICs List of Architecture Declarations
Types BIT and
BIT VECTOR

Architecture
Bodies begin
Architecture
Declarations
Concurrent
Statements
List of Concurrent Statements
The IEEE
1164 Package end architecture rtl;
 Architecture Body Syntax

Simple
Entities and
Architectures This is the (very) general format of an architecture body:
Dr DC Hendry
architecture rtl of example4 is
Entity
Declarations
GENERICs List of Architecture Declarations
Types BIT and
BIT VECTOR

Architecture
Bodies begin
Architecture
Declarations
Concurrent
Statements
List of Concurrent Statements
The IEEE
1164 Package end architecture rtl;

In this example the designer has chosen the architecture name

rtl presumably to indicate that the design may be read by a
synthesis tool.
 Architecture Declarations

Simple
Entities and
Architectures

Dr DC Hendry
Within the architecture declarations we may declare a wide
Entity
Declarations
variety of objects. These include:
GENERICs

Types BIT and

BIT VECTOR

Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Architecture Declarations

Simple
Entities and
Architectures

Dr DC Hendry
Within the architecture declarations we may declare a wide
Entity
Declarations
variety of objects. These include:
GENERICs
Signals to be used within the architecture (in addition to
Types BIT and
BIT VECTOR those signals in the port list of the entity declaration).
Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Architecture Declarations

Simple
Entities and
Architectures

Dr DC Hendry
Within the architecture declarations we may declare a wide
Entity
Declarations
variety of objects. These include:
GENERICs
Signals to be used within the architecture (in addition to
Types BIT and
BIT VECTOR those signals in the port list of the entity declaration).
Architecture
Bodies
Components, that is other designs, which will become a
Architecture
Declarations
subcomponent of this design.
Concurrent
Statements

The IEEE
1164 Package
 Architecture Declarations

Simple
Entities and
Architectures

Dr DC Hendry
Within the architecture declarations we may declare a wide
Entity
Declarations
variety of objects. These include:
GENERICs
Signals to be used within the architecture (in addition to
Types BIT and
BIT VECTOR those signals in the port list of the entity declaration).
Architecture
Bodies
Components, that is other designs, which will become a
Architecture
Declarations
subcomponent of this design.
Concurrent
Statements Constants to be used within the design.
The IEEE
1164 Package
 Architecture Declarations

Simple
Entities and
Architectures

Dr DC Hendry
Within the architecture declarations we may declare a wide
Entity
Declarations
variety of objects. These include:
GENERICs
Signals to be used within the architecture (in addition to
Types BIT and
BIT VECTOR those signals in the port list of the entity declaration).
Architecture
Bodies
Components, that is other designs, which will become a
Architecture
Declarations
subcomponent of this design.
Concurrent
Statements Constants to be used within the design.
The IEEE
1164 Package Functions and procedures.
 Architecture Declarations

Simple
Entities and
Architectures

Dr DC Hendry
Within the architecture declarations we may declare a wide
Entity
Declarations
variety of objects. These include:
GENERICs
Signals to be used within the architecture (in addition to
Types BIT and
BIT VECTOR those signals in the port list of the entity declaration).
Architecture
Bodies
Components, that is other designs, which will become a
Architecture
Declarations
subcomponent of this design.
Concurrent
Statements Constants to be used within the design.
The IEEE
1164 Package Functions and procedures.
User defined types.
 Signal Declarations

Simple
Entities and
The first of these, signal declarations, allows the use of
Architectures additional signals within the architecture. The general format
Dr DC Hendry
is:
Entity
Declarations signal <signal name(s)> : <type> ;
GENERICs

Types BIT and

BIT VECTOR

Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Signal Declarations

Simple
Entities and
The first of these, signal declarations, allows the use of
Architectures additional signals within the architecture. The general format
Dr DC Hendry
is:
Entity
Declarations signal <signal name(s)> : <type> ;
GENERICs

Types BIT and Examples:

BIT VECTOR

Architecture
signal wireA : bit;
Bodies signal opcode : bit vector(7 downto 0);
Architecture
Declarations signal r, s, t : bit;
Concurrent
Statements

The IEEE
1164 Package
 Signal Declarations

Simple
Entities and
The first of these, signal declarations, allows the use of
Architectures additional signals within the architecture. The general format
Dr DC Hendry
is:
Entity
Declarations signal <signal name(s)> : <type> ;
GENERICs

Types BIT and Examples:

BIT VECTOR

Architecture
signal wireA : bit;
Bodies signal opcode : bit vector(7 downto 0);
Architecture
Declarations signal r, s, t : bit;
Concurrent
Statements

The IEEE A further form available is:

1164 Package
signal <signal name> : <type> := <initial value> ;
 Signal Declarations

Simple
Entities and
The first of these, signal declarations, allows the use of
Architectures additional signals within the architecture. The general format
Dr DC Hendry
is:
Entity
Declarations signal <signal name(s)> : <type> ;
GENERICs

Types BIT and Examples:

BIT VECTOR

Architecture
signal wireA : bit;
Bodies signal opcode : bit vector(7 downto 0);
Architecture
Declarations signal r, s, t : bit;
Concurrent
Statements

The IEEE A further form available is:

1164 Package
signal <signal name> : <type> := <initial value> ;
Examples:
signal counter : integer := 0;
 Concurrent Statements

Simple
Entities and
The simplest concurrent statement is the concurrent
Architectures assignment statement, which is in general:
Dr DC Hendry
<signal name> <= <expression> ;
Entity
Declarations
GENERICs
where <expression> must return a value of the appropriate
Types BIT and type.
BIT VECTOR

Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Concurrent Statements

Simple
Entities and
The simplest concurrent statement is the concurrent
Architectures assignment statement, which is in general:
Dr DC Hendry
<signal name> <= <expression> ;
Entity
Declarations
GENERICs
where <expression> must return a value of the appropriate
Types BIT and type. The expression may be built up with a variety of
BIT VECTOR
operators depending upon the type of the signals involved.
Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Concurrent Statements

Simple
Entities and
The simplest concurrent statement is the concurrent
Architectures assignment statement, which is in general:
Dr DC Hendry
<signal name> <= <expression> ;
Entity
Declarations
GENERICs
where <expression> must return a value of the appropriate
Types BIT and type. The expression may be built up with a variety of
BIT VECTOR
operators depending upon the type of the signals involved. For
Architecture
Bodies integers the usual operators, +, -, * and / are available.
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Concurrent Statements

Simple
Entities and
The simplest concurrent statement is the concurrent
Architectures assignment statement, which is in general:
Dr DC Hendry
<signal name> <= <expression> ;
Entity
Declarations
GENERICs
where <expression> must return a value of the appropriate
Types BIT and type. The expression may be built up with a variety of
BIT VECTOR
operators depending upon the type of the signals involved. For
Architecture
Bodies integers the usual operators, +, -, * and / are available. For
Architecture
Declarations signals of type BIT the available operators include:
Concurrent
Statements

The IEEE
1164 Package
 Concurrent Statements

Simple
Entities and
The simplest concurrent statement is the concurrent
Architectures assignment statement, which is in general:
Dr DC Hendry
<signal name> <= <expression> ;
Entity
Declarations
GENERICs
where <expression> must return a value of the appropriate
Types BIT and type. The expression may be built up with a variety of
BIT VECTOR
operators depending upon the type of the signals involved. For
Architecture
Bodies integers the usual operators, +, -, * and / are available. For
Architecture
Declarations signals of type BIT the available operators include:
Concurrent
Statements or for logical or.
The IEEE
1164 Package
 Concurrent Statements

Simple
Entities and
The simplest concurrent statement is the concurrent
Architectures assignment statement, which is in general:
Dr DC Hendry
<signal name> <= <expression> ;
Entity
Declarations
GENERICs
where <expression> must return a value of the appropriate
Types BIT and type. The expression may be built up with a variety of
BIT VECTOR
operators depending upon the type of the signals involved. For
Architecture
Bodies integers the usual operators, +, -, * and / are available. For
Architecture
Declarations signals of type BIT the available operators include:
Concurrent
Statements or for logical or.
The IEEE
1164 Package
and for logical and.
 Concurrent Statements

Simple
Entities and
The simplest concurrent statement is the concurrent
Architectures assignment statement, which is in general:
Dr DC Hendry
<signal name> <= <expression> ;
Entity
Declarations
GENERICs
where <expression> must return a value of the appropriate
Types BIT and type. The expression may be built up with a variety of
BIT VECTOR
operators depending upon the type of the signals involved. For
Architecture
Bodies integers the usual operators, +, -, * and / are available. For
Architecture
Declarations signals of type BIT the available operators include:
Concurrent
Statements or for logical or.
The IEEE
1164 Package
and for logical and.
nor for logical nor.
 Concurrent Statements

Simple
Entities and
The simplest concurrent statement is the concurrent
Architectures assignment statement, which is in general:
Dr DC Hendry
<signal name> <= <expression> ;
Entity
Declarations
GENERICs
where <expression> must return a value of the appropriate
Types BIT and type. The expression may be built up with a variety of
BIT VECTOR
operators depending upon the type of the signals involved. For
Architecture
Bodies integers the usual operators, +, -, * and / are available. For
Architecture
Declarations signals of type BIT the available operators include:
Concurrent
Statements or for logical or.
The IEEE
1164 Package
and for logical and.
nor for logical nor.
nand for logical nand.
 Concurrent Statements

Simple
Entities and
The simplest concurrent statement is the concurrent
Architectures assignment statement, which is in general:
Dr DC Hendry
<signal name> <= <expression> ;
Entity
Declarations
GENERICs
where <expression> must return a value of the appropriate
Types BIT and type. The expression may be built up with a variety of
BIT VECTOR
operators depending upon the type of the signals involved. For
Architecture
Bodies integers the usual operators, +, -, * and / are available. For
Architecture
Declarations signals of type BIT the available operators include:
Concurrent
Statements or for logical or.
The IEEE
1164 Package
and for logical and.
nor for logical nor.
nand for logical nand.
xor for logical exclusive or.
 Concurrent Statements

Simple
Entities and
The simplest concurrent statement is the concurrent
Architectures assignment statement, which is in general:
Dr DC Hendry
<signal name> <= <expression> ;
Entity
Declarations
GENERICs
where <expression> must return a value of the appropriate
Types BIT and type. The expression may be built up with a variety of
BIT VECTOR
operators depending upon the type of the signals involved. For
Architecture
Bodies integers the usual operators, +, -, * and / are available. For
Architecture
Declarations signals of type BIT the available operators include:
Concurrent
Statements or for logical or.
The IEEE
1164 Package
and for logical and.
nor for logical nor.
nand for logical nand.
xor for logical exclusive or.
xnor for exclusive nor (only available with VHDL-93).
 Concurrent Statements

Simple
Entities and
The simplest concurrent statement is the concurrent
Architectures assignment statement, which is in general:
Dr DC Hendry
<signal name> <= <expression> ;
Entity
Declarations
GENERICs
where <expression> must return a value of the appropriate
Types BIT and type. The expression may be built up with a variety of
BIT VECTOR
operators depending upon the type of the signals involved. For
Architecture
Bodies integers the usual operators, +, -, * and / are available. For
Architecture
Declarations signals of type BIT the available operators include:
Concurrent
Statements or for logical or.
The IEEE
1164 Package
and for logical and.
nor for logical nor.
nand for logical nand.
xor for logical exclusive or.
xnor for exclusive nor (only available with VHDL-93).
not for logical inversion.
 Examples:

Simple
Entities and
Architectures

Dr DC Hendry

Entity
Declarations
x <= a or (c and d);
GENERICs

Types BIT and

BIT VECTOR

Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Examples:

Simple
Entities and
Architectures

Dr DC Hendry

Entity
Declarations
x <= a or (c and d);
GENERICs

Types BIT and

BIT VECTOR
y <= e and f and g;
Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Examples:

Simple
Entities and
Architectures

Dr DC Hendry

Entity
Declarations
x <= a or (c and d);
GENERICs

Types BIT and

BIT VECTOR
y <= e and f and g;
Architecture
Bodies
Architecture
Declarations
Concurrent
Statements
z <= ((not e) or g) and a;
The IEEE
1164 Package
 Examples:

Simple
Entities and
Architectures

Dr DC Hendry

Entity
Declarations
x <= a or (c and d);
GENERICs

Types BIT and

BIT VECTOR
y <= e and f and g;
Architecture
Bodies
Architecture
Declarations
Concurrent
Statements
z <= ((not e) or g) and a;
The IEEE
1164 Package Note that round brackets are needed to determine the order of
evaluation of operators. An exception to this rule is then the
same operator appears twice in succession and that operator is
associative.
 The IEEE 1164 Package

Simple
Entities and
Architectures

Dr DC Hendry
Types BIT and BIT VECTOR are seldom used, instead the
equivalent types from the IEEE 1164 Package are used.
Entity
Declarations
GENERICs

Types BIT and

BIT VECTOR

Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 The IEEE 1164 Package

Simple
Entities and
Architectures

Dr DC Hendry
Types BIT and BIT VECTOR are seldom used, instead the
equivalent types from the IEEE 1164 Package are used.
Entity
Declarations
GENERICs library ieee;
Types BIT and use ieee.std logic 1164.all;
BIT VECTOR

Architecture
Bodies
entity parity is
Architecture
Declarations
generic(
Concurrent
Statements
N : integer);
The IEEE
port(
1164 Package packet : in std logic vector(N 1 downto 0);
parityBit : out std logic);
end entity parity;
 Type std logic

Simple
Entities and 1 From now on use type std logic rather than type bit.
Architectures

Dr DC Hendry

Entity
Declarations
GENERICs

Types BIT and

BIT VECTOR

Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Type std logic

Simple
Entities and 1 From now on use type std logic rather than type bit.
Architectures

Dr DC Hendry
2 Type std logic is standardised by IEEE to support both
simulation and synthesis.
Entity
Declarations
GENERICs

Types BIT and

BIT VECTOR

Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Type std logic

Simple
Entities and 1 From now on use type std logic rather than type bit.
Architectures

Dr DC Hendry
2 Type std logic is standardised by IEEE to support both
simulation and synthesis.
Entity
Declarations 3 Signals of type std logic can take nine values to
GENERICs
represent for example:
Types BIT and
BIT VECTOR

Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Type std logic

Simple
Entities and 1 From now on use type std logic rather than type bit.
Architectures

Dr DC Hendry
2 Type std logic is standardised by IEEE to support both
simulation and synthesis.
Entity
Declarations 3 Signals of type std logic can take nine values to
GENERICs
represent for example:
Types BIT and
BIT VECTOR U uninitialised - default value.
Architecture
Bodies
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Type std logic

Simple
Entities and 1 From now on use type std logic rather than type bit.
Architectures

Dr DC Hendry
2 Type std logic is standardised by IEEE to support both
simulation and synthesis.
Entity
Declarations 3 Signals of type std logic can take nine values to
GENERICs
represent for example:
Types BIT and
BIT VECTOR U uninitialised - default value.
Architecture
Bodies
X an unknown value.
Architecture
Declarations
Concurrent
Statements

The IEEE
1164 Package
 Type std logic

Simple
Entities and 1 From now on use type std logic rather than type bit.
Architectures

Dr DC Hendry
2 Type std logic is standardised by IEEE to support both
simulation and synthesis.
Entity
Declarations 3 Signals of type std logic can take nine values to
GENERICs
represent for example:
Types BIT and
BIT VECTOR U uninitialised - default value.
Architecture
Bodies
X an unknown value.
Architecture
Declarations
0 logic 0.
Concurrent
Statements

The IEEE
1164 Package
 Type std logic

Simple
Entities and 1 From now on use type std logic rather than type bit.
Architectures

Dr DC Hendry
2 Type std logic is standardised by IEEE to support both
simulation and synthesis.
Entity
Declarations 3 Signals of type std logic can take nine values to
GENERICs
represent for example:
Types BIT and
BIT VECTOR U uninitialised - default value.
Architecture
Bodies
X an unknown value.
Architecture
Declarations
0 logic 0.
Concurrent
Statements
1 logic 1.
The IEEE
1164 Package
 Type std logic

Simple
Entities and 1 From now on use type std logic rather than type bit.
Architectures

Dr DC Hendry
2 Type std logic is standardised by IEEE to support both
simulation and synthesis.
Entity
Declarations 3 Signals of type std logic can take nine values to
GENERICs
represent for example:
Types BIT and
BIT VECTOR U uninitialised - default value.
Architecture
Bodies
X an unknown value.
Architecture
Declarations
0 logic 0.
Concurrent
Statements
1 logic 1.
The IEEE - a dont care value.
1164 Package
 Type std logic

Simple
Entities and 1 From now on use type std logic rather than type bit.
Architectures

Dr DC Hendry
2 Type std logic is standardised by IEEE to support both
simulation and synthesis.
Entity
Declarations 3 Signals of type std logic can take nine values to
GENERICs
represent for example:
Types BIT and
BIT VECTOR U uninitialised - default value.
Architecture
Bodies
X an unknown value.
Architecture
Declarations
0 logic 0.
Concurrent
Statements
1 logic 1.
The IEEE - a dont care value.
1164 Package
Z high impedance state, used to synthesise
tri-states.
 Type std logic

Simple
Entities and 1 From now on use type std logic rather than type bit.
Architectures

Dr DC Hendry
2 Type std logic is standardised by IEEE to support both
simulation and synthesis.
Entity
Declarations 3 Signals of type std logic can take nine values to
GENERICs
represent for example:
Types BIT and
BIT VECTOR U uninitialised - default value.
Architecture
Bodies
X an unknown value.
Architecture
Declarations
0 logic 0.
Concurrent
Statements
1 logic 1.
The IEEE - a dont care value.
1164 Package
Z high impedance state, used to synthesise
tri-states.
...
 Type std logic

Simple
Entities and 1 From now on use type std logic rather than type bit.
Architectures

Dr DC Hendry
2 Type std logic is standardised by IEEE to support both
simulation and synthesis.
Entity
Declarations 3 Signals of type std logic can take nine values to
GENERICs
represent for example:
Types BIT and
BIT VECTOR U uninitialised - default value.
Architecture
Bodies
X an unknown value.
Architecture
Declarations
0 logic 0.
Concurrent
Statements
1 logic 1.
The IEEE - a dont care value.
1164 Package
Z high impedance state, used to synthesise
tri-states.
...
4 Vectors of std logic may be (with additional types) used
to synthesise arithmetic components.