Instrumentation and Measurement

Technology Conference - IMTC 2007

Warsaw, Poland, May 1-3, 2007

Improved Performances Linearization Technique for CMOS Differential Structure

Cosmin Popa
University Polytehnica of Bucharest

Abstract - An original differential structure using exclusively MOS implemented in CMOS technology a simple technique based
devices working in the saturation region will be further presented. on square-root circuits for improving the CMOS differential
Performing the great advantages of an excellent linearity (for an stage linearity, which compensates the quadratic
extended range of the input voltage), obtained by compensating the characteristic of the MOS transistor in saturation.
quadratic characteristic of the MOS transistor operating in the The original proposed differential amplifier is based on a
saturation region by an original square-root circuit, the proposed
circuit is designed for low-voltage low-power operation. The quasi-symmetrical structure, using exclusively MOS devices
frequency response of the new differential structure is strongly operating in the saturation region for improving the circuit
increased by operating all the MOS devices in the saturation region. frequency response. In order to improve the differential
The circuit is implemented in 0.35um CMOS technology, the structure linearity, the quadratic characteristic of the
SPICE simulations confirming the theoretical estimated results (a saturation-operated MOS devices will be compensated by
linearity error under a percent for an extended input range of two original current-mode square-root circuits.
0.5V and a supply voltage corresponding to low-voltage
requirements, VCC = 3 V). II. THEORETICAL ANALYSIS
A. Classical CMOS diferential amplifier
Keywords - Differential amplifier, linearity, square-root circuit
The most common approach of a differential amplifier in
I. INTRODUCTION CMOS technology is based on strong-inverted MOS
transistors (usually working in the saturation region), having
The differential amplifier is an important stage of a very the most important advantage of a much better frequency
large area of applications, including high-performances response with respect to the weak-inverted MOS differential
analog/mixed ICs, such as operational amplifiers, voltage amplifiers. As a result of the quadratic characteristic of a
comparators, voltage regulators, video amplifiers, modulators MOS transistor operating in saturation, the transfer
and demodulators or A/D and D/A converters. Replacing characteristic of the classical CMOS differential amplifier
bipolar transistors with MOS transistors, it was solved the will be strongly nonlinear, its linearity being in reasonable
problem of relatively large values of the input bias and input limits only for a very limited range of the differential input
offset currents and of the small value of the input impedance, voltage.
with the disadvantage of reducing the voltage gain due to the The drain currents of the classical CMOS differential
quadratic characteristic of the MOS transistor working in amplifier will have the following nonlinear dependence on
saturation. the differential input voltage, vid:
Besides all these parameters, the linearity of the circuit still 4 112
K 2 Vid
remains poor because of the fundamental nonlinear Io + Io (Kv,d (1)
characteristic of both bipolar and MOS transistors, resulting 2dl,2 2
421)
4I6
the possibility of achieving a relatively good linearity only
for a restricted input voltage range (the amplitude of the input having a fifth-order limited Taylor expansion around vid = 0,
voltage for the classic differential amplifier using MOS expressed by:
transistors in saturation have to be below a few hundreds of I K12112 K312 K512
mV ). In conclusion, it results the necessity of implementing 1d1,2(Vid) + 1 d K Vi 3 3K152 V +
a linearization technique for decreasing the superior-order
nonlinearities of the MOS differential stage and for 2)
increasing the available range for the input voltage Io being the polarization current for the differential
amplitudes. It exists in literature many circuit techniques used amplifier. The total harmonic ditortions coefficient of the
to improve the MOS differential amplifier linearity. It was elementary CMOS differential amplifier is proportional to the
presented in [1], [2] a third and fifth-order harmonics square of the differential input voltage amplitude:
cancellation with good results and a relatively simple circuit 2
implementation. A constant-sum of the gate-source voltages THD_ VID K (3)
circuit connection was described in [3] and it allows an
8 IO
important reduction of the total harmonic distortions
coefficient of the circuit. In [4], it was presented and

1-4244-0589-0/07/$20.00 2007 IEEE 1

 The graphical dependence Id1,2 (vid ) is presented in Considering a square-root dependence of the output
Figure 1. currents of XI circuits, Ix' and Iy' on their input currents,
Ix and Iy, Io being a reference current (these
'dl- d2 (A) dependencies will be further demonstrated):
Im
Ix'=2oIx/ (5)
and:
Iy =2 IOI2 (6)
the expression of the output current expression for the
linearized differential amplifier will be given by the
t following expression:
(VVGX - VGSY)
IXY = V2K10 (7)
vid (V) VGSX and VGSY being the gate-source voltages of Tx and
-06 -0.2 02 06 I
-1
Ty transistors. It results a linear transfer characteristic of the
Figure 1: The graphical dependence Id],2 (vid ) circuit from Figure 2:
Ixy=gm(Vx-Vy) (8)
where gm is the circuit transconductance:
In order to improve the circuit linearity, especially for large
values of the differential input voltage (THD from relation gm = 2KI (9)
(3) has relatively large values for vid of about hundreds of So, in a first-order analysis, the dependence of the output
m V ), a linearization technique has to be implemented. current of the differential circuit on its differential input
voltage will be perfectly linear.
B. The original linearized differential amplifier
C. The second-order effects
The original idea for improving the linearity of the classical
differential amplifier is to compensate the quadratic The linearity (8) of the transfer characteristic for the
characteristic of the MOS transistor working in the saturation differential amplifier from Figure 2 is slightly affected by the
region by two identical square-root current-mode circuits. second-order effects that affect the MOS transistor operation,
The result will be a more linear transfer characteristic of the modeled by the following relations: short channel effect (10)
circuit, quantitative evaluated by an important reduction of and mobility degradation (11)).
the total harmonic distortion of the original differential
amplifier. The proposed method is presented in Figure 2. ID = (VGS- T)(1+ DS) (10)
Ko-~~~~~~~~
1x~~~~~~~~~~~~~~
(11)
vcc [1+OG(VGS VT)]+ OD VDS) -

Considering that the design condition A= OD is fulfilled,

the gate-source voltage of a MOS transistor Aworking in
saturation at a drain current ID will be:

Ix'oI lIx +
\;IXx
+ I
O y
,~~~~~~IX VGS =VT + OG K
D
K (12)
The last term represents the error which affects the
IX+IyX
quadratic characteristic of the MOS transistor operated in
saturation, caused by the previous presented second-order
effects. The result will be a small accuracy degradation ofthe
entire circuit linearity, quantitative evaluated by the superior-
Figure 2: The original linearization technique order terms in the transfer characteristic of the differential
for the classical CMOS differential amplifier amplifier:
OC

Ixy = ak(VX-Vy) (13)

The output current of the linearized differential amplifier k=i
from Figure 2, Ixy, could be expressed as: Because of the circuit symmetry, the odd-order terms from
Ixy = IX '-Iy' (4) the previous relation are usually cancel out, so the main
circuit nonlinearity caused by the second-order effects will be

2
represented by the third-order error term from the previous
relation, having much smaller value than the linear term.
D. The current-mode square-root circuit
The square-root circuit from Figure 2 represents also a
perfect symmetrical structure (Figure 3), using MOS
transistors and a FGMOS device working in saturation for
reducing the silicon occupied area and for improving the
circuit frequency response.
0Io
-Vcc
Figure 3: The current-mode square-root circuit
The output current expression has a linear dependence on
the drain currents of Tx y, To and T transistors:
IX1y = I - Ix,y- Io (14)
For a saturation operation of T transistor and an aspect
ration fourth time greater than all the others transistors from
the circuit, the drain current of the FGMOS transistor will
have the following expression:
4K VGSX,Y + VGSO
22
where VGSX Y and VGSO represents the gate-source
of Tx y and TO transistors, equals, respectively, to:
VGSOUT =VT + 2IY
VGSO =VT+
For the four previous relations it results the expression of
the output current of the square-root circuit from Figure 3:
IXY'= ( Io
-Ix,y- (18)
equivalent to a square-root dependence of the output current
on the two input currents:
IX y' = 2VI,yI, (19)
III. SIMULATED RESULTS
The SPICE simulation Ixy (Vx - Vy ) based on 0.35 jim
CMOS technology parameters for the original differential
amplifier is presented in Figure 4, showing a linearity error
under a percent for an extended input range of Vx, Vy < 1 V.
The supply voltage corresponds to low-power requirements,
Vcc=3 V.
Vcc
- [I
%v -
', (YJ
Figure 4: The SPICE simulation Ixy (Vx - Vy )
for the original differential amplifier
The circuit layout implemented in the same technology is
presented in Figure 5.
(15) IV. CONCLUSIONS
An original differential structure using exclusively MOS
voltages devices working in the saturation region has been presented.
Performing the great advantages of an excellent linearity (for
an extended range of the input voltage), obtained by
(16) compensating the quadratic characteristic of the MOS
transistor operating in the saturation region by an original
square-root circuit, the proposed circuit is designed for low-
(17) voltage low-power operation. The frequency response of the
new differential structure is strongly increased by operating
all the MOS devices in the saturation region. The circuit is
implemented in 0.35ym CMOS technology, the SPICE
simulations confirming the theoretical estimated results (a
linearity error under a percent for an extended input range of
0.5V and a supply voltage corresponding to low-voltage
requirements, Vcc = 3 V ).
3
 REFERENCES
[1] Popa C., "Linearity Improvement Design Technique for a
CMOS Differential Amplifier". Scientific Bulletin, University
"Politehnica" of Bucharest, 2000, volume 62, number 4, series C, pp.
51-60.
[2] Popa C., "Linear Rail-to-rail CMOS Input Stage". The 13th
International Conference on Control System and Computer Science,
University "Politehnica" of Bucharest, 2001, pp. 536-539.
[3] Hung C., Ismail M., Halonen K. and Porra V., "Low-voltage Rail-to-
rail CMOS Differential Difference Amplifier". IEEE Proceedings of
International Symposium on Circuits and Systems, 1997, pp. 145-148.
[4] Hyogo A., Fukutomi Y. and Sekine K., "Low Voltage Four-quadrant
Analog Multiplier Using Square-root Circuit Based on CMOS
Pair". IEEE Proceedings of International Symposium on Circuits and
Systems, 1999, pp. 274-276.