Memory Devices

CONTENT

S.No Name of Chapter Page

No.
Introduction 1
1. Memory Devices 1
1.1 ROM 4
1.2 PROM 4
1.3 EPROM 5
1.4 EEPROM 6
1.5 SRAM 7
1.6 BSRAM 7
1.7 DRAM 8
2. SRAM AND DRAM 9
2.1 SRAM 9
2.2 SRAM Operation 12
2.2.1 Standby 12
2.2.2 Reading 12
2.2.3 Writing 13
2.3 Types of SRAM 14
2.3.1 Asynchronous SRAM 14
2.3.2 By Transistor type 14
2.3.3 By Function 15
2.3.4 By Feature 15
2.3.5 By flip-flop type 15
2.4 DRAM 16
2.5 Operation Principle 18
2.6 Difference between SRAM and DRAM 19
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3. CMOS AND NMOS DEVICES 20
3.1 NMOS 21
3.2 NMOS Devices 21
3.3 NMOS Structure 22
3.4 NMOS Operation 25
4. CMOS Devices 26
4.1 CMOS Structure 26
4.2 CMOS Operation 28
5. Reference 30

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INTRODUTION
Semiconductor memory is an electronic data storage device, often used as
computer memory, implemented on a semiconductor-based integrated circuit.
There are many different types of implementations using various technologies.

Most types of semiconductor memory have the property of random access which
means that it takes the same amount of time to access any memory location, so
data can be efficiently accessed in any random order. This contrasts with data
storage media such as hard disks and CDs which read and write data consecutively
and therefore the data can only be accessed in the same sequence it was written.
Semiconductor memory also has much faster access times than other types of data
storage; a byte of data can be written to or read from semiconductor memory
within a few nanoseconds, while access time for rotating storage such as hard disks
is in the range of milliseconds. For these reasons it is used for main computer
memory (primary storage), to hold data the computer is currently working on,
among other uses.

Shift registers, processor registers, data buffers and other small digital registers that
have no memory address decoding mechanism are not considered as memory
although they also store digital data.

In a semiconductor memory chip, each bit of binary data is stored in a tiny circuit
called a memory cell consisting of one to several transistors. The memory cells are
laid out in rectangular arrays on the surface of the chip. The 1-bit memory cells are
grouped in small units called words which are accessed together as a single
memory address. Memory is manufactured in word length that is usually a power
of two, typically N=1, 2, 4 or 8 bits.

Data is accessed by means of a binary number called a memory address applied to

the chip's address pins, which specifies which word in the chip is to be accessed. If
the memory address consists of M bits, the number of addresses on the chip is 2 M,
each containing an N bit word.

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Consequently, the amount of data stored in each chip is N2M bits.The memory
storage capacity for M number of address lines is given by 2M, which is usually in
power of two: 2, 4, 8, 16, 32, 64, 128, 256 and 512 and measured in kibibits,
mebibits, gibibits or tebibits, etc. As of 2014 the largest semiconductor memory
chips hold a few gibibits of data, but higher capacity memory is constantly being
developed. By combining several integrated circuits, memory can be arranged into
a larger word length and/or address space than what is offered by each chip, often
but not necessarily a power of two.

The two basic operations performed by a memory chip are "read", in which the
data contents of a memory word is read out (nondestructively), and "write" in
which data is stored in a memory word, replacing any data that was previously
stored there. To increase data rate, in some of the latest types of memory chips
such as DDR SDRAM multiple words are accessed with each read or write
operation.

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1. MEMORY DEVICS

Memories are devices that can store digital data or information in terms of
bits (binary digits). Many memory chips were designed and developed by
using NMOS. The unit cell of the memory types are shown in circuit
schematics.

Here we discuss about some Types of Memories:-

1.1 ROM

1.2 PROM

1.3 EPROM

1.4 EEPROM

1.5 SRAM

1.6 BSRAM

1.7 DRAM

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1. 1 ROM
The read only memory
is also called mask ROM.
During fabrication stage, the
information is inscribed (and
cannot be altered) in the form
of presence or absence of a link
between the word (access) line
and the bit line. This causes the
presence or absence of a read
out signal on the bit line when
the word line is activated. The
essential part of the ROM is the way the link is provided. Since the
link determines the cell size (and thus the cost per bit). Fast high
devices ROMs are in great demands of personal computers.

1.2 PROM
The
Programmable
read only memory
(PROM) is one of
the ROMs that are
field-programmable
but lack “erase”
capability. PROM
uses cells with a
fuse that can be
blown open
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electrically or a p-n diodes that can be short circuited by an
avalanching pulse. A bipolar PROM has 64-K bit p-n diode cells,
and MOS PROMs have higher density but slower speed.

1.3 EPROM
EPROM stands for the Erasable Programmable read only
memory. In the EPROM cell, the presence or absence of charge in
the floating gate of a double poly gate MOSFET determines the
logic states programming is done by injecting energetic carries
generated by drain p-n junction avalanche breakdown, thereby
increasing the threshold voltage Vth of the memory transistor. The
EPROM is, therefore also called the FAMOS (floating gate
avalanche injection MOS)
device. When ultraviolet is
shone on the device, the
charge in the floating gate
is released, there by erasing
the memory. EPROMs are
therefore packaged with a
glass window to permit the
erasing operation to occur.
The original p-channel FAMOS cell, which has two transistors in
series—one for storage and other for access, has been replaces by
n-channel, single transistor cells. The original programming voltage
of 30V has been reduced to 12V. The most advanced 1-Mbit
EPROMs today have a cells size of 19-29 µm2 and an access time
of 80-140 ns.

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1.4 EEPROM
EEPROM designates the electrically erasable
programmable read only memory, and it is the most sophisticated
in its principle of operation. For a ROM to be electrically erasable,
it must have the means to inject and extract charge carriers into and
from a floating gate. The first proposal for an EEPROM used the
electrons trapping states at the nitride-oxide interfere in a metal-
nitrate-oxide-silicon
(MONS) structure with a
very thin (about to 2nm)
oxide. The recent
dominant technology of
EEPROM uses a floating
gate separated from a
silicon by an oxide (about
150 Å thick).
Programming and erasing
in either type of
EEPROM is achieved by
forcing the channel current to flow between the gate and substrate
with the control biased and negative, respectively.

Both EPROM and EEPROM store charge on a conductive region in

the middle of a MOS- GATE oxide, and are therefore critically
depended on MOS structure, specially high field carrier transport in
both silicon and oxide. Because carrier in the floating island stay
there even after the power supply is turned of, EPROM and
EEPROM are also non-volatile memories.

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1.5 SRAM
The Random access
memory is one of the
largest memory. In a RAM
memories cells are
organized in metrics form
they can be accessed in
random order to read or
write data. A static
random access memory
can retain stored data
indefinitely and it can be implemented as a flip-flop circuit to store
one bit of information. Since SRAMs use flip-flop circuit in the
memory cells, they are most basic of all semi conductor memories.
Achieve devices for access and drive are either MOS transistors or
bipolar transistors.

1.6 BSRAM
The Bipolar SRAM is the
fastest of all the semi conductor
memory type but MOS SRAM is
the fastest among MOS
memories. Fig. shows the
equivalent circuit diagram for
bipolar SRAMs.
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1.7 DRAM
The First Dynamic
Random Access Memory used
one half of the static memory
cell, or three transistors- one for
the driver, another for the load,
and the third for the access.
This device has evolved to
today’s one transistor,

one capacitor DRAM cell, in

which the single transistor is
used as the access to the
capacitive reservoir. Since the
stored charge is gradually lost
because of the space charge
generation-recombination process. Cells have to be read and
restleshed at predetermined intervals on the order of milliseconds
(hence, the name dynamic). The DRAM readout signal is small, on
the order of 150-200 mV, and is subject to various kinds of noise
source.

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2. SRAM AND DRAM

SRAM is static random access memory that retains data bits in its
memory as long as power is being supplied. Unlike DRAM, which
stores bits in cells consisting of a capacitor and a transistor, SRAM does
not have to be periodically refreshed.

Here we discuss about the SRAM, SRAM operation, type of SRAM. We

also discuss the DRAM and their Operation and also the difference
between them.

2.1 SRAM

Fig 2.1: a six-transistor CMOS SRAM cell

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A typical SRAM cell is made up of six MOSFETs. Each bit in an SRAM

is stored on four transistors (M1,M2,M3,M4) that form two cross-
coupled inverters. This storage cell has two stable states which are used
to denote 0 and 1. Two additional access transistors serve to control the
access to a storage cell during read and write operations. A typical
SRAM uses six MOSFETs to store each memory bit. In addition to such
6T SRAM, other kinds of SRAM chips use 8T, 10T, or more transistors
per bit.

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Fig 2.2 :Four transistor SRAM provides advantages in density at the cost of manufacturing
complexity. The resistors must have small dimensions and large values.

This is sometimes used to implement more than one (read and/or write)
port, which may be useful in certain types of video memory and register
files implemented with multi-ported SRAM circuitry.

Generally, the fewer transistors needed per cell, the smaller each cell can
be. Since the cost of processing a silicon wafer is relatively fixed, using
smaller cells and so packing more bits on one wafer reduces the cost per
bit of memory.

Memory cells that use fewer than four transistors are possible – but, such
3T or 1T cells are DRAM, not SRAM (even the so-called 1T-SRAM.

Access to the cell is enabled by the word line (WL in figure) which
controls the two access transistors M5 and M6 which, in turn, control
whether the cell should be connected to the bit lines: BL and BL. They
are used to transfer data for both read and write operations. Although it
is not strictly necessary to have two bit lines, both the signal and its
inverse are typically provided in order to improve noise margins.

During read accesses, the bit lines are actively driven high and low by
the inverters in the SRAM cell. This improves SRAM bandwidth
compared to DRAMs – in a DRAM, the bit line is connected to storage
capacitors and charge sharing causes the bit line to swing upwards or
downwards. The symmetric structure of SRAMs also allows for
differential signaling, which makes small voltage swings more easily
detectable. Another difference with DRAM that contributes to making
SRAM faster is that commercial chips accept all address bits at a time.
By comparison, commodity DRAMs have the address multiplexed in

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two halves, i.e. higher bits followed by lower bits, over the same
package pins in order to keep their size and cost down.

The size of an SRAM with m address lines and n data lines is 2m words,
or 2m × n bits. The most common word size is 8 bits, meaning that a
single byte can be read or written to each of 2 m different words within
the SRAM chip. Several common SRAM chips have 11 address lines
(thus a capacity of 2m = 2,048 = 2k words) and an 8-bit word, so they are
referred to as "2k × 8 SRAM".

2.2 SRAM OPERATION

An SRAM cell has three different states. It can be in: standby (the
circuit is idle), reading (the data has been requested) and writing
(updating the contents). The SRAM to operate in read mode and write
mode should have “readability” and “write stability” respectively.
The three different states work as follows:

2.2.1 Standby

If the word line is not asserted, the access transistors M5 and M6

disconnect the cell from the bit lines. The two cross-coupled inverters
formed by M1 – M4 will continue to reinforce each other as long as they
are connected to the supply.

2.2.2 Reading

Assume that the content of the memory is a 1, stored at Q. The read

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cycle is started by precharging both the bit lines to a logical 1, then
asserting the word line WL, enabling both the access transistors. The
second step occurs when the values stored in Q and Q are transferred to
the bit lines by leaving BL at its precharged value and discharging BL
through M1 and M5 to a logical 0 (i. e. eventually discharging through
the transistor M1 as it is turned on because the Q is logically set to 1).
On the BL side, the transistors M4 and M6 pull the bit line toward VDD,
a logical 1 (i. e. eventually being charged by the transistor M4 as it is
turned on because Q is logically set to 0). If the content of the memory
was a 0, the opposite would happen and BL would be pulled toward 1
and BL toward 0. Then these BL and BL will have a small difference of
delta between them and then these lines reach a sense amplifier, which
will sense which line has higher voltage and thus will tell whether there
was 1 stored or 0. The higher the sensitivity of sense amplifier, the faster
the speed of read operation is.

2.2.3 Writing

The start of a write cycle begins by applying the value to be written to

the bit lines. If we wish to write a 0, we would apply a 0 to the bit lines,
i.e. setting BL to 1 and BL to 0. This is similar to applying a reset pulse
to an SR-latch, which causes the flip flop to change state. A 1 is written
by inverting the values of the bit lines. WL is then asserted and the value
that is to be stored is latched in. Note that the reason this works is that
the bit line input-drivers are designed to be much stronger than the
relatively weak transistors in the cell itself, so that they can easily
override the previous state of the cross-coupled inverters. Careful sizing
of the transistors in an SRAM cell is needed to ensure proper operation.

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2.3 Types of SRAM

Non-volatile SRAM Non-volatile SRAMs, or SRAMs, have standard
SRAM functionality, but they save the data when the power supply is
lost, ensuring preservation of critical information. nvSRAMs are used in
a wide range of situations—networking, aerospace, and medical, among
many others —where the preservation of data is critical and where
batteries are impractical.

2.3.1 Asynchronous SRAM

Asynchronous SRAM are available from 4 Kb to 64 Mb. The fast
access time of SRAM makes asynchronous SRAM appropriate as main
memory for small cache-less embedded processors used in everything
from industrial electronics and measurement systems to hard disks and
networking equipment, among many other applications. They are used in
various applications like switches and routers, IP-Phones, IC-Testers,
DSLAM Cards, to Automotive Electronics.

2.3.2 By transistor type

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 Bipolar junction transistor (used in TTL and ECL) — very fast but
consumes a lot of power
 MOSFET (used in CMOS) — low power and very common today

2.3.3 By function
 Asynchronous — independent of clock frequency; data in
and data out are controlled by address transition
 Synchronous — all timings are initiated by the clock
edge(s). Address, data in and other control signals are
associated with the clock signals
2.3.4 By feature
 ZBT (ZBT stands for zero bus turnaround) — the turnaround is the
number of clock cycles it takes to change access to the SRAM
from write to read and vice versa. The turnaround for ZBT SRAMs
or the latency between read and write cycle is zero.
 Sync Burst (sync Burst SRAM or synchronous-burst SRAM) —
features synchronous burst write access to the SRAM to increase
write operation to the SRAM
 DDR SRAM — Synchronous, single read/write port, double data
rate I/O
 Quad Data Rate SRAM — Synchronous, separate read & write
ports, quadruple data rate I/O

2.3.5 By flip-flop type

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 Binary SRAM
 Ternary SRAM

2.4 DRAM

Dynamic random-access
memory (DRAM) is a type of
random-access memory that
stores each bit of data in a
separate capacitor within an
integrated circuit. The
capacitor can either be charged
or discharged; these two states
are taken to represent the two
values of a bit, conventionally
called 0 and 1. Since even "nonconducting" transistors always leak a
small amount, the capacitors will slowly discharge, and the information
eventually fades unless the capacitor charge is refreshed periodically.
Because of this refresh requirement, it is a dynamic memory as opposed
to static random-access memory (SRAM) and other static types of
memory. Unlike flash memory, DRAM is volatile memory (vs. non-
volatile memory), since it loses its data quickly when power is removed.
However, DRAM does exhibit limited data eminence.
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DRAM is widely used in digital electronics where low-cost and

high-capacity memory is required. One of the largest applications for
DRAM is the main memory (colloquially called the "RAM") in modern
computers; and as the main memories of components used in these
computers such as graphics cards (where the "main memory" is called
the graphics memory). In contrast, SRAM, which is faster and more
expensive than DRAM, is typically used where speed is of greater
concern than cost, such as the cache memories in processors.

The advantage of DRAM is its structural simplicity: only one

transistor and a capacitor are required per bit, compared to four or six
transistors in SRAM. This allows DRAM to reach very high densities.
The transistors and capacitors used are extremely small; billions can fit
on a single memory chip. Due to the dynamic nature of its memory cells,
DRAM consumes relatively large amounts of power, with different ways
for managing the power consumption.

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2.5 OPERATION PRINCIPLE

DRAM is usually arranged in a rectangular array of charge storage cells

consisting of one capacitor and transistor per data bit. The figure to the
right shows a simple example with a four-by-four cell matrix. Some
DRAM matrices are many thousands of cells in height and width.

The long horizontal lines connecting each row are known as word-lines.
Each column of cells is composed of two bit-lines, each connected to
every other storage cell in the column (the illustration to the right does
not include this important detail). They are generally known as the "+"
and "−" bit lines.

A sense amplifier is essentially a pair of cross-connected inverters

between the bit-lines. The first inverter is connected with input from the
+ bit-line and output to the − bit-line. The second inverter's input is from
the − bit-line with output to the + bit-line. This results in positive
feedback which stabilizes after one bit-line is fully at its highest voltage
and the other bit-line is at the lowest possible voltage.

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2.6 DIFFERENCE BETWEEN SRAM AND DRAM

SRAM DRAM
Stores bits in memory cells Memory cells are composed of
composed of flip flops. capacitors and transistors.

Each cell which can store a single Each cell requires a capacitor
bit requires six transistor. (which stores bit as charge) and a
transistor.

Does not need access time Needs to be refreshed every few

compared to DRAM, therefore used milliseconds to retain data because
as caches mostly. the charge of capacitor leaks.

Low density/ less memory per chip Slower access time compared to
due to more circuitry required for a SRAM as it cannot be read while
single cell. being refreshed.

More power consumption then High chip density/ more memory

DRAM because of low chip per chip compared to SRAM due to
density. less circuitry for a single cell.

More costly in terms of cost per bit Less power consumption then
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compared to DRAM due to low SRAM because use of simple
chip density. circuitry.

CMOS AND NMOS DEVICES

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3.1 NMOS

In MOS transistors allows a much greater packing density on

a semiconductor chip then is possible with bipolar junction transistors.
The MOSFET can be sub divided into two groups.

1. The n-channel MOSFET is commonly referred to as an

NMOS.

2. The complimentary MOSFET is usually called a CMOS. The

CMOS provides n-channel and p-channel MOSFETs on the
same chip.

3.2 NMOS DEVICES

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The Metal-oxide-semiconductor field effect used in very
large scale integration circuits. In the 1960s the p-channel MOS was
originally used in integrated circuit. n-channel MOS (NMOS) devices,
however have dominated the IC market since the 1970s because there
electron mobility is higher then that of holes.

3.3 NMOS STRUCTURE

In this two enhancement mode (normally mode device
NMD). A field oxide (FOX) surrounds the transistors and the gate and
source of DMD are connected that the burred connect. And intermediate
dielectric layer separates the over lying metal layer from the underline
layer. In the JFET the high input resistance is obtained from the reversed
biased p-n junctions. In the MOSFET the extremely high input
resistance is made possible by insulator. There are two basics structures
for MOSFET. The depletion type and the induced type. The major
difference between them is that with the terminals of the device is open
circuited, the depletion type has a conducting channel that links the drain
to the source. The induced type a channel of opposite type to that of the
drain that of the drain and the source linking the two regions.

When the device has p-type source and drain region it is called the p-
channel MOSFET or P-MOS.

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The structure of enhancement and depletion modes refer to the
relative increase or decrease of the majority. Carrier density in the
channel connecting the source to the drain. If a given gate bias tends to
increase the majority carrier density in the channel, the device is set to
be operated in the enhancement mode (normally off). If the gate in an
NMOS is biased by a positive voltage with respect to the substrate is
applied in order to diminish.

Fig 3.3.1 :

The electrons density in the n-channel then is said to be operated in the

depletion mode. For a p-channel MOSFET when the negative gate
potential with respect to the substrate is biased, the device is operated in
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the enhancement mode and when the positive gate voltage is applied the
device is operated in the depletion mode.

Fig 3.3.2 : Cross-sectional view Fig3.3.3:N-channel Depletion type MOSFET

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Fig 3.3.4 : Cross-sectional View Fig 3.3.5 : n-channel Induced type MOSFET

When a MOS is operated in enhancement mode, the drain circuit is

higher. When however the MOS is operated in the depletion mode the
drain current is lower because the majority carrier density is lower.

3.4 NMOS OPERATION

Two enhancement mode devices (EMD) are in series
with a depletion mode device (DMD) and the three transistors
are connected between the positive power supply VDD and
ground Vss reference. The DMD is normally on at we Vss=0
and acts as current source for the two EMDs. Gate A and B of
the two EMDs serve as inputs to the logic circuit, and the
DMD’s gate – source connection is the output electrode of the
logic circuit.

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4.CMOS DEVICES
The complimentary MOS (CMOS) is made of both NMOS and
PMOS devices, and its power consumption is quite low. In some CMOS
design the NMOS circuit is incorporated in domino-CMOS to take
advantage of the NMOS’s high speed and the CMOS’s low power.

4.1 CMOS STRUCTURE

There are three structure of n-tub p-tub and twine tub. When tub is
formed in a p-type substrate the device is called an n-tub. Just as when in
an n-type substance it is called a p-tub. If an n-tub and p-tub are combine

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on the same subtract the device is referred to as a twine tub. A tub is also
called a well, and it can be produce by extra diffusion steps.

Fig 4.1 : CMOS Structure

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4.2 CMOS OPERATION

The p-channel transistor is formed in the n-type structure, and the
n-channel transistor is grown in the p-region. Which in turn is formed in
the n-type substrate. The p region acts as the n-channel transistors
substrate and it is commonly referred to as a tub or well. The gates of the
n-channel and p-channel transistors are connected and serves as the
input to the inverter. The common drain of each devices are the output
of the inverter. The dependence of the output voltage V on the input
voltage V of the CMOS inverter. V1=0 the n-channel transistor is OFF,
while the p-channel transistor is heavily ON. Therefore the output
voltage is Vin =Vout . As the input voltage V is increased above zero, the
n-channel transistor eventually is turned ON, while the p-channel
transistor finally turns OFF.

The key feature of a CMOS gate is that in either logic states one of
the two transistors is OFF and the current conducted between VDD and
VSS is negligible. A significant current is conducted through the CMOS
circuit only when both transistors are ON at the same switching time.

The low power consumption of CMOS is one of its most important

contributions. The performance and simplification of circuit design are
other attractive features of the CMOS devices. CMOS provide the circuit
designer with flexibility in designing circuits that are either static CMOS
(channel transistor for every n-channel transistor) or dynamic CMOS.

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Fig 4.2.1: Circuit diagram Fig 4.2.2 : Device cross-section

Fig 4.2.3 : Vo > Vs Fig 4.2.4 : Current curve

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