F

t{oDtcoH 2 USER HANUAL

F
t-
llalce the following connections:
F
rx cH.o
TX CLOCK
to
to
RX CH.0
RX CTOCK
F
TX OUTPUT to RX INPUT F
This is l{ode I of operation. ln thjs mode, TX CH.0 is used to tell the
F
Receiver which transmitted samples belong to Channel 0, and TX F
CLOCK is used to clock the Receiver in synchronism with the
Transmitter.
F
F
I at the end of th'is
The board interconnecttons are shown in Figure
chapter.
F
F
Display TX 0UTPUT (t.p.20) and the Receiver's CH,0 low pass filter
10
input (t.p.42) on the oscilloscope, to show that the samples F
corresponding to Analog Channel 0 have been extracted from the
transmitted time-division multiplexed stream of samples^
F
F
ttI l. Display the input of the Receiver's CH.O low pass filter (t.p.42) and
the Receiver's CH.O output (t.p.43) on the oscilloscope, to show that
F
the 250H2 sinewave has been reconstructed by low pass filtering. E
t2 The present position of the DUTY CYCLE CONTR0L switch ('5')
F
indicates that the duration of each :ample is 508 of the 'time slot' E
allocated to each channel. Variation of the 0UTY CYCLE C0NTROL
switch setting allows this proportion to be changed from 0!B to 0098 E
in 1fifr steps. Display TX $UTPUT (t.p.20) and Receiver CH.0 output E
(t.p.A3) on the oscilloscope. Vary the position of the DUTY CYCLE
CONTROL switch, noting how TX 0UTPUT changes, and how the
E
amplitude of the signal at the Receiver's CH.0 output increases as the E
sampling duty cycle in6easos. The variation of Receiver output
amplitude with sampl'ing duty cycle was covered in the l-{0DlC0l"1 I E
User llanual, and is due in this case to the fact that the N0DlCON ? tr
Receiver Iow pass filters are not preceded by Samp)e/Hold circuits.
tr
l3 Return the DUTY CYCLE CONTROL switch to the position'5"
Remove the probe on Receiver CH.0 output (t.p.43), and put it on each
F
of the other Receiver outputs in turn (t.p.45, 47,49\, to show that r-
each of the original sinewaves has been correctly reconstructed.
tr
lf

I E
E
L-
tr lloDtcom 2 USER T1ANUAL

L,
L
L
14. llode I of operation reguires three Iinks to be made between
Transmitter and Receiver. This can be reduced to two Iinks by
removing the TX CLOCK-RX CLOCK Iink, and deriving the Receiven's
clock from the TX CH.O signal. This new mode of operation is
tr. rlO0E ?. To demonstrate this mode, remove the TX CH. 0-RX CH.0 and
tr fX CLOCK-RX CL0CK links, and add the following new links between
the lransmitter Timing Logic, Phase Locked Timing Circuit and
E.
r_ ,r
Receiver Timing Logic blocks:

L=
L
I-r to PLL I/P
TX EH.O
SYNC to RX CH.O
CLK to RX CLOCK
t_
lr

H ln addition, ensure that the slider of the switch in the Phase Locked

L
t:.r
Timing Circuit block is in the Right-Hand position.

l_
I-^r
The board interconnections are shown in Figure 2.

l:
I:r 15 The Phase Locked Loop is now locked onto the TX CH.0 signal, and
L
ll--r
produces two outputs:

l_-
l:r SYNC: This is of the same freguency as the TX CH.O signal, and is used
L
t-1
to tell the Receiver which transmitted samples belong to

L
r-r
Channel 0.

L
!-r
CLK: This signal has four times the freguency of the TX CH.0 s'ignal,
and is used to clock the samples into the Receiver.
L'
t-i
L
I:I
SYNC and CLK can be examined on test points 29 and 27 respectively.

L'
:--r
16 Show that all four sinewaves can still be reconstructed in ltode 2, by

L'
I--{
display'ing Receiver CH.0, CH.l, CH.Z and CH.3 outputs in turn on the
oscilloscope (t.p. 43, 45, 47,49).
L'
I-r
L' 11 The number of Iinks between Transmitter and Receiver can be further
reduced to a single link by dedicating analog Channel 0 to carry

rL'
t-r
l- synchronisation ('sync') pulses. This is l.lode 3 of operation. To
demonstrate this mode, REN0VE the fsllowing links:
I--r *250H2
to the TRANSIIlTTER block's CH.0 input.
l--. TX CH.O to PLL I/P.
L=
l----
L-
I'--r I
L-
\
l- -_r
t'l0Dtcom 2 USER T1AHUAL

Then MAKE the following connection:

SYNC TEVEL to the IRANSI1lTTER block's CH.0 input.

ln addition, put the slider of the sw'itch in the Phase Locked Timing
Circuit block into the Left-Hand position.

The board interconnections are shown in Figure 3.

lB. Display TX 0UTPUT (t,p.?$) and Transmitter CH.l input (t.p.l3) on the
oscilloscope, using the latter for'scope triggering purposes. Vary the
SYNC LEVEL preset, and note how the sync pulses change in
amplitude. Return this preset to its fully Clockwise position. At
the Receiver, thgse pulses are detected by a voltage comparator,
whose threshold level is selected to distinguish between signal
samples and the higher amplitude sync pulses. The output of the
comparator is the stream of extracted sync pulses (t.p.22). These
sync pulses are input to the Phase-Locked Loop, which generates
SVNC and CLK signals as for Ilode 2.

l9 Examination of Receiver CH. l, CH.Z and Cll.] outputs (t.p. 45, 47 and
49) shows that the three original sinewaves have once again been
reconstructed. Recoiver CH.0 output (t.p.43) is a D.C. leve'|, related to
the level of the transmitted sync pulses.

t0
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