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Design and Analysis of Linear Feedback Shift

Register(LFSR) Using Gate Diffusion Input(GDI)


Technique

Radhika Sharma Balwinder Singh


ACS Division, Centre for Development of Advanced ACS Division, Centre for Development of Advanced
Computing (C-DAC) Mohali Computing (C-DAC) Mohali
radhika.gemini11@gmail.com balwinder.cdacmohali@gmail.com

Abstract— In chip manufacturing technology, reduction in LFSR is used in BIST for generating pseudo random
chip size possess great concern for power dissipation. Low power sequences. Advantage of pseudo random testing is that it has
testing has become an important issue as power dissipation very simple hardware which can be implemented for on chip
during testing mode is very high as compare to normal mode. test generation. Low power LFSR has gained importance
LFSR is used in testing of ASIC chips by generating pseudo because besides BIST, it has wide usage in encryption
random patterns. This paper deals with design of low power circuitry, data compression circuitry and cryptography.
LFSR by using GDI technique. GDI technique is one of the low
power technique used for implementing various digital circuits. Power dissipation in digital circuit is mainly by three
This technique uses only two transistors to design fast and low main sources [3]. In the below equation (1) , Pswitching
power circuits with improvement in power characteristics. LFSR constitutes dynamic power dissipation while Psc + Pleakage
has been implemented by conventional and GDI technique in constitutes static power dissipation. Static power contributes
Cadence Virtuoso at 90nm technology. Comparative analysis is negligible to the power dissipation, therefore only dynamic
carried out between the two methods showing upto 45.4 % and power dissipation is considered for analysis. Average power
20 % reduction in power and area respectively in GDI technique. Pavg is given by:
Simulation and variation of power with frequency and voltage is
also discussed. Pavg = Psc + Pleakage+ Pswitching (1)

Keywords— Analysis, GDI, LFSR, Low power =IscVdd+IleakageVdd+.5α CLV2ddFclk (2)


In equation (2) first term Isc represents short circuit current
I. INTRODUCTION which is result of simultaneous switching of both PMOS and
In today’s era energy performance requirements have made NMOS. Second term Ileakage represents leakage current due to
the engineers to design circuit with least power dissipation. subthreshold effects and substrate injection. Finally last term
With the advancement in technology scaling, billions of represents switching component of the power where Vdd is
transistors are integrated on a single chip. Although it has supply voltage, α is node transition activity factor, Fclk is the
increased the functionality, but at the same time has led to clock frequency , and CL is load capacitance.
increase in testing time. Power dissipation is a critical
parameter in testing as circuit dissipates more power during II. RELATED WORK
testing than its normal functioning.[1] Higher power Many methods are proposed to solve problem of power
dissipation raises chip temperature and draws more current dissipation during testing. Some of the previous works related
from power supply. Excessive power dissipation can lead to to optimize power during testing are discussed in this section.
circuit damage, hence affecting the reliability of system and One method [4] is to use more test vectors to reduce
can result in increase in the product cost. It is proved that even transitions, as power dissipation occurs due to lack of
an 10ºC rise in working temperature of the circuit leads to correlation between patterns during testing.[5] discussed
100% rise in failure rate [2]. Implementing low power design is implementation of LFSR using pass transistors for low power
a continuous challenge faced by ASIC/SOC designers. Low dissipation.[6] discussed the low power design of magnitude
power dissipation during testing is a captious issue in today’s comparator using GDI. Another method is to use low power
VLSI system. External testing has many drawbacks such as stump BIST where clock gating and scan triggering technique
ATE (automatic test equipment) is expensive, inefficient (due is used to reduce power dissipation [7]. Another technique is
to low fault coverage) and test application time is also more. dual speed LFSR to reduce heat dissipation during testing. It
BIST gives assured solution to these VLSI testing problems. comprises of two LFSR, a normal LFSR and a slow LFSR.
Built In Self Test (BIST) is a design technique in which there is Slow LFSR speed is 1/w of normal clock. It lowers the
self testing of the circuit. It merges the concept of “Built in transition density, which in turn reduce heat dissipation [8]. T
test” and “Self test”. flip flop is implemented using modified GDI technique which
resulted in less power delay product and energy delay product

978-1-5090-0893-3/16/$31.00 ©2016 IEEE


as compare to conventional T flip flop[9].Carry select adder is ( + 1) 0 1 … 0 ( )
implemented using GDI technique[10]. ( + 1) 0 0 … 0 ( )
= ⋮ ⋮ ⋮ ⋮
⋮ ⋮
( + 1) 1 ℎ … ℎ ( )
III. LFSR
Linear Feedback Shift Register is a connection of flip flops This matrix in the form of equation can be written in the
arranged in series where input of present flip flop is the output form of equation (3):
of the previous flip flop. It is formed by combining Xor gates
in the feedback of series of flip flops. Initial value of LFSR is X(t+1) = Ts X(t) (3)
called as seed value which is a combination of 1’s and 0’s. It is X(t+1) is the output of the present flip flop while X(t) is the
very important to choose that seed value which produces low output of the previous flip flop. Leaving behind first column
power dissipation as Seed value determines further random and last row, Ts is an identity matrix. The above matrix
values .LFSR enters a repeating cycle due to its finite possible indicates that X0 gets input from X1. X1 gets input from X2 and
states. There are two types of LFSR [11]- so on. First element in last row is 1 to indicate that Xn-1 always
I. Standard/external LFSR gets input from X0.

II. Modular/internal LFSR Xn-1(t+1) = X0(t)+h1X1(t)+h2X2(t)+…….hn-1Xn-1 (4)


In equation (4) hi represents feedback coefficient. Therefore
LFSR can be represented by a characteristic polynomial given
by:
F(x) = 1+h1x1+h2x2+h3x3+………..hnxn-1+xn (5)
In equation (5) ,1 ensures that there is always a connection
between last and first flip flop.
As already discussed LFSR is made by combining D flip
flop and Xor gate. Therefore structure of conventional D flip
flop and Xor gate is discussed as following:
A. Conventional DFF
Fig-1: Standard LFSR Fig 5 shows Implementation of DFF using NAND gate .Preset
and clr pin is added to initialize value for LFSR.

Fig-2: Modular LFSR


Fig 5: Conventional D Flip flop

Fig-1 and Fig-2 represent standard LFSR and modular


LFSR respectively. Delay from last flip flop to the first is less B. Conventional CMOS Xor gate
in modular LFSR as compare to standard LFSR. In modular Figure 4 represents basic design of conventional Xor gate
LFSR delay due to various Xor gates in the feedback is not based on CMOS technology.
present, there is direct connection between last and first flip
flop.
A properly designed LFSR can generate nearly exhaustive set
of patterns as it can cycle through distinct 2n-1 states [except 0
in all flip flops]. Such a designed LFSR is known as maximal
length LFSR. To make connection with Xor gate make the
coefficient hi 1 else 0.
LFSR in terms of matrix can be written as
Basic GDI cell resembles standard CMOS inverter but
there are differences between the two.
• Unlike CMOS,GDI cell contains four terminals:
P(outer node of PMOS), N(outer node of NMOS) ,G(common
gate input of NMOS and PMOS),output may be used as input
or output port.
• PMOS bulk is connected to P terminal and NMOS
bulk is connected N terminal unlike CMOS inverter.

B. GDI based Xor

Gate diffusion input technique is used in Fig 6 to design Xor


Fig 4: Conventional Xor gate[13]. It results in less power dissipation as well as lowest
transistor count as compare to conventional Xor gate.

IV. LOW POWER LFSR DESIGN


A. Gate Diffusion Input Technique
Various combinatorial synchronous functions can be
designed using gate diffusion input technique by using only
two transistors, hence making this technique a low power
design technique [12]. This technique is suitable for
implementing low power and fast circuits with minimum
number of transistors, simultaneously leading to improvement Fig 6: GDI based Xor
in static power characteristics and logic level swings.
C. GDI based D Flip Flop

Fig 7 shows Implementation of D flip flop using GDI. Circuit


components are divided into
i. Body gates: are controlled by clock signal and are
responsible for the state of the circuit. Clock create
two alternative paths; one for holding state of the
latch and other for transparent state.
ii. Inverters(x): used to complement the values and
to buffer internal signals for swing restoration.
iii. Preset input: used to set initial value of LFSR.
Fig 3: GDI basic cell
Reduced power dissipation, area and power delay product is
obtained as compare to other DFF design techniques [14]
Table1 illustrates different input configuration of GDI cell
results in different logic functions.
Table 1: logic functions implemented with GDI
P G N Function Output
1 A O NOT
B A C MUX +
0 A B AND AB
B A 1 OR A+B
1 A B F2 +
B A 0 F1

Fig 7: GDI based D Flip flop


D. GDI based LFSR
Fig 8 shows Implementation of Linear feedback shift register
using GDI technique. It is combination of GDI based DFF and
GDI based Xor gate. This structure is suitable for high speed,
low power and low area circuits.

Fig 10: Simulation of 4 bit LFSR

Fig 8: GDI based LFSR Table 2: Comparison of CMOS and GDI based DFF

E. GDI based LFSR layout PARAMETER CMOS GDI

Fig 9 shows Layout of GDI based LFSR where DFF and Xor Power(µw) 14.2 7.31
is implemented using GDI technique. Transistors 40 25
Area(µm2) 128.88 103.5

Table 3: Comparison of CMOS and GDI based LFSR at 1.9 GHz

PARAMETER CMOS GDI

Power(µw) 63.64 34.72


Transistors 174 104
Area(µm2) 1028 817.95

150
Power(µw)

Fig 9: Layout of GDI based LFSR 100

50

V. RESULTS AND DISCUSSIONS 0


Analysis of 4 bit LFSR is examined in this section. The 850 1000 1900 2400 3200
analysis is done at 90nm technology using cadence virtuoso Frequency(Mhz)
tool. Fig 10 represents the output waveform of LFSR showing
the different patterns obtained for testing the circuit. Table 2
CMOS GDI
and table 3 shows the comparison of performance of DFF and
LFSR in terms of area, number of transistors and power using
conventional and GDI technique. The performance of the Fig 11: Power variation with change in frequency
circuit in figure 11 is determined in regard of power dissipation
at frequency ranging from 850 MHz to 3.2 GHz whereas in fig
12 the performance of the circuit is determined at a biasing
voltage ranging from 0.7 volt to 1.15 volt .Both the graphs
show increase in power dissipation with increase in supply
voltage and frequency of operation. Fig 13 shows the number
of transistors required to design CMOS and GDI based LFSR.
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Power(µw)

60
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0.7 0.75 0.8 0.9 1 1.1 1.15
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LFSR 581
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VI. CONCLUSION Networks, pp.187-191.
In this paper we have implemented LFSR by CMOS and GDI [14] Morgenshtein, A.; Fish, A.; Wagner, I.A., "An efficient implementation
technology at 90nm in Cadence Virtuoso. Simulations as well of D-Flip-Flop using the GDI technique," in Circuits and Systems, 2004.
ISCAS '04. Proceedings of the 2004 International Symposium on, Vol.2,
as different parameter comparison were carried out between No., pp.II-673-6 Vol.2,23-26 May 2004
CMOS and GDI based LFSR. Results are compared in table 2.
Based on transistor level simulation, GDI technology reduces
power dissipation and hardware by 45.4% and 20%
respectively. Therefore, as scaling of devices is increasing, the
proposed LFSR design can be used in low power testing.

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