Topic A

Design and Application Guide for

High Speed Power MOSFET
Gate Drive Circuits
by Laszlo Balogh

Power Supply Design Seminar

Power MOSFET Advantages

• MOSFETs and BJTs are charge controlled devices, both
must be driven just as “hard” to achieve comparable
switching times.
• MOSFETs have reduced drive requirements compared to
BJTs due to the isolation of the control electrode.
• MOSFETs require less amount of controlling charge which
result in greatly reduced storage time.
• The resistive nature and positive TC of the channel
impedance allow easy paralleling of several devices.

The promise of MOSFET technology:

• cheaper, simpler and more efficient drive circuits.
(we will see!?)

2 -1
 MOSFET Technologies
SOURCE SOURCE SOURCE

GATE GATE DRAIN

GATE n+ n+ OXIDE
p p n+ n+
n+ n+
p
n
p+ p+
n- EPI layer p
Substrate
n- EPI layer n+ Substrate DRAIN
n+ Substrate DRAIN

(a) (b) (c)

Vertical DMOS Trench DMOS Lateral DMOS

• that’s where all • increased cell density • lowest capacitances
started • lower capacitances • fast switching
• polysilicon gate • lower RDS(on) • limited voltage rating
• self-aligning process • more difficult to • limited current rating
• high density manufacture • low area utilization
• low capacitances (all electrodes are on
the top side of the
silicon)
Fig.1.

MOSFET Model
D D D

G G G

S S S
(a) (b) (c)

(a) Simplified Device Model - silicon structure

(b) Breakdown Model - dv/dt induced turn-on
(c) Switching Model - to estimate switching performance and
device limitations

Fig.2.

2 -2
 Critical Parameters
• CGS - overlap of the source and channel region by the gate
electrode.
• CGD - overlap of the JFET silicon region by the gate
electrode and the capacitance of the depletion region.
• CDS - capacitance of the body diode.
• RG,I - material resistance in the gate signal distribution
(gate mesh resistance), polysilicon gate R > metal gate R
• VTH - measured at 250uA, and 25C, (-7mV/C)
• gfs - transconductance, active (linear) state, gfs=dID/dVGS
• LS - source inductance, inside the package
• LD - drain inductance, inside the package
• Other circuit components: LLK, RSNS, RGATE, Driver’s
output impedance (RHI, RLO, RDRV)

Switch-Mode Applications
• Switch between lowest and highest resistance states of the
MOSFET in the shortest possible time. (reduce switching
losses)
• Switching performance of a MOSFET is determined by the
time required to establish voltage changes across
capacitances. (Charge carriers can travel across the channel
in 20ps to 200ps depending on the size of the cells.)
• Achieve the lowest possible RDSON within the limitations
of the device. (reduce conduction loss)

2 -3
 Clamped Inductive Switching
• Simple schematic is valid for all
IDC power conversion topologies to
model switching operation.
RGATE
• Turn-off speed is inversely
proportional to the gate current of
VDRV VOUT the device.
• Turn-on speed is limited by the
switching characteristic of the
clamp diode (rectifier element).
• Because of the fundamental nature
of the diode operation, the switch
ends up with most of the switching
losses.

Fig.3.

Turn-On Procedure

Step 1.
Vgs
Charge CGS to the threshold level.
Vth

Ig VDRV

D
LD
CGD

RHI RGATE RG,I

Vds
G CDS
IG
CGS
LS

Ids S

Fig.4.(a)

2 -4
 Turn-On Procedure

Step 2.
Vgs
Charge CGS from VTH to VGS,MIN
Vth required to carry ID. (linear region)
VDRV
Ig
ID
D
LD
CGD

RHI RGATE RG,I

Vds
G CDS
IG
CGS
LS

S
Ids

Fig.4.(b)

Turn-On Procedure

Step 3.
Vgs
Discharge CGD and CDS
Vth as VDS falls close to GND.
VDRV
Ig
ID
D
LD
IG CGD
RHI RGATE RG,I
Vds
G CDS

CGS
LS

S
Ids

Fig.4.(c)

2 -5
 Turn-On Procedure

Step 4.
Vgs
Apply overdrive by charging CISS to the
Vth
final gate voltage.

VDRV
Ig
ID
D
LD
CGD
RHI RGATE RG,I
Vds
G CDS
IG
CGS
LS

S
Ids

Fig.4.(d)

Turn-Off Procedure

Step 1.
Vgs
Discharge CISS from the final gate voltage
Vth
to VGS,MIN required to carry ID.

VDRV
Ig
ID
D
LD
CGD
RLO RGATE RG,I
Vds
G CDS
IG
CGS
LS

S
Ids

Fig.5.(a)

2 -6
 Turn-Off Procedure

Step 2.
Vgs
Charge CGD and CDS as VDS rises to the
Vth
final turn-off voltage.

VDRV
Ig
ID
D
LD
IG CGD
RLO RGATE RG,I
Vds
G CDS

CGS
LS

S
Ids

Fig.5.(b)

Turn-Off Procedure

Step 3.
Vgs
Discharge CGS from VGS to VTH to turn-
Vth
off the channel. (linear region)

VDRV
Ig
ID
D
LD
CGD
RLO RGATE RG,I
Vds
G CDS
IG
CGS
LS

S
Ids

Fig.5.(c)

2 -7
 Turn-Off Procedure

Step 4.
Vgs
Discharge CGS to GND.
Vth

VDRV
Ig

D
LD
CGD
RLO RGATE RG,I
Vds
G CDS
IG
CGS
LS

S
Ids

Fig.5.(d)

Switching Speed, Switching Losses

• Step 1 corresponds to turn-on / turn-off delay.
• Step 2 + Step 3 gives switching time.
• Step 4 happens after switching is complete.
• Simulate, analyze mathematically or measure to determine
current / voltage fall and rise times and possible overlap
between the respective waveforms.
DO IL
VO

IL LD+LLK
LLK CGD (LDL)
2x DIDEAL RHI RHI+RGATE+RG,I
DUT VO VDRV
(RGON) CDS
RGATE
RLO RSNS
VDRV
CGS
LS

2 -8
 Gate Drive Power Losses
Vgs, Gate-to-Source Voltage (V) • Gate drive losses accrue during the entire gate
charge / discharge cycles.
VDRV
• Power loss is independent from how quickly
the charge is delivered.
VDS
• Gate charge curves give relatively accurate
worst case estimate.
QG
PGATE = Q G ⋅ VDRV ⋅ f DRV I AVE = Q G ⋅ f DRV
Qg, Total Gate Charge (nC)

VBIAS IAVE
• The equations give the average VDRV
current and the power drawn from L∞
CDRV
the bias circuitry but does not give
you the actual power dissipation in RHI RGATE RG,I
the driver!
1 R HI ⋅ Q G ⋅ VDRV ⋅ f DRV
PDRV,ON = ⋅
2 R HI + R GATE + R G,I

Fig.6.

Effects Of Parasitic Components

LS and RSNS: Oscillation at the gate terminal:
• exhibits a negative feedback when • CG,E = CGS+CGD at low voltages
ID is changing. (use the curves).
• limits dI/dt through negative • LG,E = LS+LLOOP between driver,
feedback when ID is changing bypass capacitor and MOSFET
• longer switching times increase • RG,E = RDRV+RG,I+RGATE.
switching losses at both switching • Only RGATE is accessible.
action
RG,E LG,E
LD and LLK: L G,E
• limits dI/dt ZC = VDRV CG,E
C G,E
• allows VDS to fall before ID=ILOAD
at turn-on
• causes VDS to overshoot VO at L G,E
turn-off
R GATE ≥ 2 ⋅ − (R G,I + R DRV )
C G,E
• acts as turn-on snubber but
increases switching losses at turn- • Make the trade-off between speed,
off reliability, cost and complexity!

Fig.7.

2 -9
 Direct Gate Drive
V (V )
• Optimizing the layout is DRV BIAS

difficult
VCC
• PWM controllers have limited PWM
drive currents controller RGATE
• High current spikes disrupt OUT
analog circuits
• Power dissipation in PWM
GND
controller
• Series inductance(s) reduces distance!
switching speed, causes ringing. • Ground plane eliminates only
• Bipolar output stage needs half of the loop inductance!
protection against reverse • Low forward voltage drop
currents occurring during Schottky diodes must be placed
oscillations in the gate loop. very close to the IC pins and to
the HF bypass capacitor.

Fig.8. & Fig.9.

Sizing The Bypass Capacitor

The scientific approach:
• Two current components cause ripple across the bypass
capacitor:
1.) Quiescent current of the driver
– IQ is 10x higher when inputs are high → ripple voltage is a
function of the duty ratio and switching frequency.
2.) Gate charge current
– QG is delivered at turn-on → proportional ripple appears across
the bypass capacitor
• Capacitor value should be determined based on the
allowable voltage ripple on the drive voltage.
I Q,HI ⋅ D MAX QG
C DRV = +
∆VDRV ⋅ f SW ∆VDRV

2 - 10
 Gate Driver Totem-Poles
VBIAS VDRV VBIAS VDRV

R R
VCC VCC
PWM PWM
controller RGATE controller RGATE
OUT OUT
RB

GND GND
distance! distance!

• Controllers are happy! All the benefits listed for bipolar

• No voltage gain.
• High currents flow locally, have
their own bypass capacitor.
• Transistors provide good clamping
of the gate terminal to their local
bypass capacitor.
totem-pole,
+ Significant voltage gain.
+ Exhibits shoot through current
because drive voltage overlap.
+ Bi-directional current capability.
– Needs inverted PWM signal.

Fig.10. & Fig.11.

Speed Enhancement Circuits

• Increase turn-off dv/dt, and turn-off dI/dt
• Speed enhancement circuits lower the drive impedance or
increase the turn-off voltage swing.
• Turn-off speed-up circuits also prevent dv/dt induced turn-
on.
V
• Significant reduction in
tD(OFF)
DRV

VCC • Incremental improvement

Driver
R
on switching times and
dv/dt immunity.
GATE
OUT

D OFF
• Works when:
GND VD,FW
IG >
R GATE

Fig.12.

2 - 11
 Turn-Off Circuits
VDRV VDRV

VCC VCC DON

DON
Driver Driver
RGATE
RGATE
OUT QOFF OUT QOFF

QINV
GND GND

• Most popular circuit for fast turn-off. • Self biasing mechanism holds
It is a simplified totem-pole! MOSFET off during power up.
• Reduces the effect of driver output • Inversion is needed to drive the
impedance, external gate resistor discharge transistor.
• Shunts, gate drive loop inductance, • QINV draws current during ON
current sense resistor. state, helps protect the driver
• Halves driver’s total power dissipation. against reverse current.
• QOFF never saturates • Holds gate closer to GND than its
• QOFF clamps gate at turn-on. PNP counterpart.

Fig.13. & Fig.14.

dv/dt Protection
dv I V − 0.007 ⋅ (TJ − 25) • Capacitive divider of CGD and CGS
= G = TH provides some protection at very low
dt C GD R EFF ⋅ C GD
VDRV
voltages.
• Start-up dv/dt protection
VCC
• MOSFET has a natural dv/dt limit based
Driver
RGATE on RG,I and CGD.
OUT
• Actual dv/dt limit depends on the gate
RLO
drive circuit.
GND
• Examples: Typical values:
dv VTH, MIN 2V V
= = = 1000
VDRV
dt (R G,I + R GATE + R LO ) ⋅ CGD (1Ω + 5Ω + 4Ω) ⋅ 200pF µs
VCC
DON
Driver
RGATE dv VTH, MIN − VBE 2V − 0.7 V V
= = = 5963
dt (R + R GATE + R LO ) ⋅ C 5Ω + 4Ω
OUT QOFF
(1Ω + ) ⋅ 200pF µs
G, I GD
RLO β 100
GND

2 - 12
 Driving Synchronous Rectifiers

QFW
V IL
QSR

• The MOSFET synchronous rectifier is a special case of ground

referenced switches.
• In synchronous rectification, the MOSFET must be driven in
accordance to another controlled switch (QFW MOSFET).
• Typically low voltage swing of VDS means that capacitors exhibit
larger values.
• Current direction and amplitude do not change after switch has been
turned on.

Fig.16.

Synchronous Rectifiers - dv/dt, Gate Charge

• Turn-on AND turn-off dv/dt is forced
QFW by the dv/dt of the other switch.
QSR IL • Need to provide lower impedance
V
RLO,SR
- pull-down to prevent turning the
+ synchronous MOSFET back on.

VDRV,FW − VGS,MIN,FW VTH,SR

<
C RSS, FW ⋅ R HI,FW C RSS,SR ⋅ R LO,SR
QFW
QSR IL • Using same devices, and same drive
V RLO,SR + amplitude:
-
1
R LO,SR < ⋅ R HI,FW
2
• Miller charge is delivered by the
power stage, but flows through the
driver’s output impedance.

Fig.17.

2 - 13
 High Side Driver Applications
Device Type: Design checklist:
• P-Channel MOSFET • Power requirements (efficiency
• N-Channel MOSFET of the drive circuit)
Driver Type: • Bias requirements
• Speed limitations
• Direct drive (low voltage)
ground referenced • Maximum duty-cycle limitation
• Level shifted drive schemes • dv/dt implications
• Bootstrap techniques • Start-Up conditions
• Using floating bias supplies • Transient operation
• Bypass capacitor size
• Layout, grounding
considerations

Driving P-Channel MOSFETs

VDRV=VIN VIN

VBIAS
VCC
PWM R1
controller VCC RGATE
RGATE
OUT PWM
controller
OUT QINV
RB
GND
R2
GND
• P-channel drivers are referenced to an
AC ground potential and does not • Works with regular PWM signal.
have to swing between large potential
differences. • Turn-on speed is fast.
• VIN<VGS,MAX • Small continuous current flows in
the inverter during on time.
• Needs inverted PWM output.
• Gate drive power and inverter
• Avoid open collector drivers. current is coming from VIN.
• Gate current does not flow in the • VIN ramp up time at power on has
ground plane, speed, maximum dv/dt to be matched to the dv/dt
might be impeded by parasitic L’s. immunity of the gate drive.
Fig.18. & Fig.20(a).

2 - 14
 N-Channel High Side Direct Drive
VDRV VIN
Close up of the switching transition:
Optional 2
VCC
PWM 3
controller RGATE
VDRV
OUT
1
1
GND

• VIN<VDRV-VGS,MIN
VIN+VGS,Miller
• Gate current flows through the load.
2
• Source terminal can pull OUT pin below
GND if not protected.
Optional turn-off circuit: 3 VIN
• PNP is turned off when source rings below
-VGS,Miller FWD recovery &
• Reduced noise tolerance during off state. VGS= Current transfer

• Turn-off gate current flows locally. 2 - 3

Fig.21. & Fig.22.

Bootstrap Implementations
VDRV VIN VDRV VIN
DBST
PWM controller
VCC
RGATE VCC DBST
PWM
controller VBST CBST
Level-Shift

OUT CBST
VOUT OUT RGATE
QLS
SRC
GND
GND

• The IC voltage capability does • Most of the bootstrap

not limit the input voltage. components can be integrated in
• Level-shift circuit conducts the PWM controllers.
current during off time. • Negative voltage on the source
• Minimum current consumption pin directly effects the IC.
during ON. • Large negative voltage on the
• Might have problem at no load or SRC pin can cause over voltage
DICM. (VBST=VBIAS-VOUT) on the bootstrap capacitor.

Fig.23. & Fig.24

2 - 15
 Protecting The SRC Pin
VDRV VIN
PWM controller
or driver output
DBST
VCC

VBST CBST

Level-Shift
OUT RGATE
SRC

GND

• Place the gate resistor in the source connection.

• Add Schottky diode between SRC and GND pins.
• Source can swing several volts below GND.
• VBST is protected against over voltage.
• CBST is charged through RGATE! Watch for DMAX!

Fig.27.

High Side Driver Biasing Scheme

VBIAS VDRV VIN
DBST

VCC VCC VB CBST

PWM CDRV
OUT CIN
controller CBIAS RGATE
OUT IN VS
VOUT
High Side
GND COUT
Driver
GND

• The high side driver must be bypassed on both sides.

• CBST is charged by high current spikes from CDRV.
• CDRV>>CBST (10x - rule of thumb)
• Bootstrap diode needs to be ultrafast type. Reverse
recovery charge loads CBST at every turn-on process.

Fig.28.

2 - 16
 Start-Up and Load Transient
VBIAS VIN
DBST DSTART RSTART

VCC CBST
VCC VB DZ R
PWM GATE
controller OUT Battery
OUT IN VS
High Side
GND
Driver
GND

• Source is above GND when rectifier is reverse biased.

• Typical problem in battery chargers and at no load.
• Might be a problem at load transient.
• Diode, resistor, zener solve the problem if there is enough
voltage difference between input and output.

Fig.29.

AC Coupled Gate Drives

VDRV 1
Normalized Steady State DC
Voltage (VC/VDRV) Across CC

0.8
VCC
PWM +VDRV VDRV-VCL 0.6
controller -VCL
0V
OUT 0.4 VCL
CC VDRV
IC,AVE=0 Zener Clamp
-VCL RGS
0.2
GND
0
0 0.2 0.4 0.6 0.8 1
Duty Ratio
• AC coupling provides simple level shift for
the gate drive signal. • The coupling capacitor voltage is the
• Results in slower turn-on but faster turn-off function of the duty ratio.
and higher dv/dt immunity. (VC=D⋅VDRV)
• RGS is essential to develop voltage across • VC will develop across CC over time.
the coupling capacitor. (τ=RGS⋅CC)
• RGS also serves as pull-down during start up. • Reduced negative bias at low duty-
• The clamp network is usually needed if the cycle!
duty cycle can go significantly above 50%.
Fig.31. & Fig.32.

2 - 17
 Transformer Coupled Gate Drives
• Provides isolation
• Works across high potential differences
• Reliable
BUT:
• Must understand magnetics, transformer design and
operation.
– Leakage inductance must be minimized
– Faraday’s Law requires VL=0V over a period of time
– Core saturation limit (BSAT) defines maximum volt-second product
– Capacitive currents flow between the winding
• More components
• Not necessarily more expensive or bigger

Single Ended, Transformer Coupled Gate Drive

VDRV
• AC coupling is needed due to
the unipolar drive signal. VCC +VDRV-VC

PWM +VDRV -VC

• The DC voltage across the controller 0V VC
coupling capacitor (VC) OUT
+ -

develops the same way as in RC CC

RGS
AC coupled direct drive.
GND
• Actual gate drive voltage, i.e.
switching performance, changes
with duty cycle. VOUT

• Duty-cycle changes will excite the LC tank on VT

the primary side of the gate drive transformer. IM
• LC series resonance has to be damped. IR
• Notice the driver’s output current direction.
IG

IOUT

Fig.33. & Fig.34.

2 - 18
 DC Restoration
VDRV

+VDRV-VC
VCC
+VDRV -VC +VDRV-VD
PWM
controller 0V VC VC-VD -VD
+ -
+ -
OUT
RC CC1 CC2
DC2 RGS
GND

• For wide duty-cycle applications, such as the buck converter, DC

restoration has to be added.
• Gate drive amplitude becomes independent of the duty ratio.
• CC1 and CC2 develops the same voltage (VC1=VC2=D⋅VDRV)
• Diode clamp on secondary restores DC component.
• Negative turn-off bias is easily generated by adding a Zener to the
circuit.

Fig.35.

Gate Drive Transformer Design

VTR ⋅ t • Low power, high peak current
NP = transformer design.
∆B ⋅ A e
• Use ferrite cores only.
1 • Calculate maximum Volt-
Second product.
VDRV·TDRV
VTR· t

0.8
DC coupled
• Consider extreme operating
0.6 (double ended) conditions when choosing ∆B.
Normalized V·s Product

0.4
AC coupled • Minimize AC resistance.
(single ended)
• Maximize magnetizing
0.2
inductance to minimize
0
magnetizing current and droop.
0 0.2 0.4 0.6 0.8 1
Duty Ratio • Minimize leakage inductance:
– reduced drive impedance
– shorter drive delay

Fig.36.

2 - 19
 Circuits With Dual Function Transformer
• Single transformer carries control signal and bias power to the gate driver.
VDRV
VDRV

+VDRV-VC Low Side IC

VCC +VDRV-2 VD
VCC
PWM -VC +VDRV-2 VD High Side IC
+VDRV
controller PWM
0V AM
OUT + -
+ -
VC VC-VD
OSC

GND

fCARRIER = fSWITCH fCARRIER >> fSWITCH

• DC restore circuit is necessary. • Transformer is smaller due to
• First few drive pulses charge high frequency operation.
the capacitor. • Control is through amplitude
• Driver needs UVLO. modulation.
• Requires dedicated IC pair.

Fig.37. & Fig.38.

Double Ended Transformer Coupled Gate Drive

• Typical applications in half-bridge and full-bridge circuits, using push-
pull type controllers.
• Dual polarity, symmetrical drive signal is readily available.
VIN Things to consider:
VDRV • Do not use AC coupling!
RGATE
VDRV
VCC
I DC = ⋅ (D A − D B )
OUTA 2 ⋅ R EFF
RGATE
Driver
• Duty cycles differ during transient.
OUTB
GND
• Self bias the gate when the
transformer is not polarized.
• Local turn-off circuit is desired.
• Winding arrangement can be very
important.

Fig.39. & Fig.40.

2 - 20
 Summary
• Understanding the MOSFET’s switching behavior is
essential to design reliable, high performance gate drive
circuits.
• A systematic design approach was demonstrated.
• Mix and match of the described techniques to satisfy the
application requirements.
• Apply the same analyses to evaluate many other possible
gate drive circuits.
• Low drive impedance is imperative for high speed
switching and dv/dt immunity in MOSFET gate drive.

• Check out several numerical examples in

Appendix A through F.

2 - 21