CS2504, Spring'2007

©Dimitris Nikolopoulos

Faster multiplication

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 CS2504, Spring'2007
©Dimitris Nikolopoulos

Faster multiplication

Parallel shift
 Partial sum stored in upper 32 bits
 Multiplier in lower 32 bits
 Multiplier shifted out bit by bit
 Partial sum shifts in place of multiplier
 Do not need to extend multiplicand!
 Everything happens in place
 Faster, simpler hardware!

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 CS2504, Spring'2007
©Dimitris Nikolopoulos

Signed multiplication


Convert operands to positive numbers

Remember original digits

Multiply using original algorithm for 31
iterations

Then add new sign
 Caution: shifting the product sum needs to sign
extend the product sign

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 CS2504, Spring'2007
©Dimitris Nikolopoulos

Even faster multipliers (Moore's law)

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 CS2504, Spring'2007
©Dimitris Nikolopoulos

Even faster multipliers


Why is the multiplier with 32 adders faster?
 Original multiplier needs a clock per bit
 Optimized multiplier needs:

An and operation (parallel)

32 adders (pipelined)

Each adder receives output of previous multiplier
 Least significant bit goes to result
 31 upper bits plus carry out go to next multiplier
 Pipeline latency:

Cost of first multiply slow

Following multiplies fast (presumably one per cycle)
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 CS2504, Spring'2007
©Dimitris Nikolopoulos

Multiplication in MIPS


mult, multu

Two registers, Hi-Lo, operating as an
extended 64-bit register

mflo, fetches 32 bits from Lo

mfhi, fetches 32 bits from Hi

Again no automatic check for overflow
 Need code
 Use mfhi to do the known overflow tests

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 CS2504, Spring'2007
©Dimitris Nikolopoulos

Grammar school division

1001 Quotient
Divisor 1000 1001010 Dividend
-1000
1010
-1000
10 Remainder

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 CS2504, Spring'2007
©Dimitris Nikolopoulos

Hardware division

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 CS2504, Spring'2007
©Dimitris Nikolopoulos

Hardware division


Assume 4-bit division

Divisor=00100000, Remainder=0000 0111

Q=nan, D=0010 0000 (8 bits),R=0000 0111

Step 1:
 R-D=0000 0111- 0010 0000 < 0
 Q=0, R=0000 0111 (restore remainder),
 D=0001 0000 (shift divisor)

Step 2:
 R-D=0000 0111-0001 0000 < 0
 Q=00, R=0000 0111, D = 0000 1000
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 CS2504, Spring'2007
©Dimitris Nikolopoulos

Hardware division

 Assume 4-bit division

 Divisor=00100000, Remainder=0000 0111
 Q=0000, D=0010 0000 (8 bits),R=0000 0111
 Step 3:

R-D=0000 0111-0000 1000 < 0

Q=000, R=0000 0111 (restore remainder), D=0000 0100
(shift divisor)
 Step 4:

R-d=0000 0111-0000 0100 > 0

Q=0001, R=0000 0011, D = 0000 0010

...
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 CS2504, Spring'2007
©Dimitris Nikolopoulos

Hardware division flow

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 CS2504, Spring'2007
©Dimitris Nikolopoulos

Faster hardware division

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 CS2504, Spring'2007
©Dimitris Nikolopoulos

Signed division


Dividend=Quotient x Divisor + Remainder

Dividend and Quotient signs need to agree

Signed division algorithm
 Calculate quotient as usual
 Negate quotient if signs of dividend and divisor
disagree

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 CS2504, Spring'2007
©Dimitris Nikolopoulos

Floating point in hardware


Use scientific notation
 314.569 is 3.14569 x 102
 This is also called a normalized number
 Binary numbers represented in the same manner:

1.00010 x 211

Floating point arithmetic:
 Binary point (equivalent to decimal point) is not
fixed as in integers
 Notation simplifies exchange of data
 Notation simplifies floating point algorithms
 Notation increases accuracy, leading zeros
eliminated, bits used for more digits beyond the
point
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 CS2504, Spring'2007
©Dimitris Nikolopoulos

Floating point numbers


We need to represent fraction and exponent

Remember, we are using fixed word sizes!

More bits for fraction improves precision

More bits for exponent increases the range

MIPS uses sign and magnitude representation:
 1 bit for the sign
 8 bits for the exponent field
 23 bits for the fraction
 (-1)s x F X 2E
 Can represent numbers as small as 2 x 10-38 or as large
as 2 x 1038
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