k0_data_array

clk
clk
4:2 index[2:0] data[31:0]
full_address[7:0]
wrdata[31:0]
wrdata[31:0]
wren

data_array_0

k1_data_array

clk

4:2 index[2:0] data[31:0]

wrdata[31:0]

wren

data_array_1

k2_data_array

clk

4:2 index[2:0] data[31:0]

wrdata[31:0] mux_4
wren
enable
data_array_2
sel[1:0]

w0[31:0] output[31:0]
k3_data_array data[31:0]
w1[31:0]

clk w2[31:0]

4:2 index[2:0] data[31:0] w3[31:0]

wrdata[31:0] mux
wren
Byte_Selector
data_array_3

Data[31:0] Byte[7:0]
k0_tag_valid byte[7:0]
1:0 Sel[1:0]

clk Byte_Mux
4:2 index[2:0]

invalidate
invalidate
reset_n output[3:0]
reset_n
validate
validate lru_logic
7:5 wrdata[2:0]

wren clk

tag_valid_array_0 enable

4:2 index[2:0] LRUblk[1:0]

LRUblk[1:0]
k[1:0]

reset

lru_array
k1_tag_valid miss_hit hit

clk 7:5 tag[2:0]

4:2 index[2:0] w0[3:0] hit

invalidate w1[3:0] k[1:0]

reset_n output[3:0] w2[3:0]

validate w3[3:0]

7:5 wrdata[2:0] miss_hit_logic

wren

tag_valid_array_1

k2_tag_valid

clk

4:2 index[2:0]

invalidate

reset_n output[3:0]

validate

7:5 wrdata[2:0]

wren

tag_valid_array_2

k3_tag_valid

clk

4:2 index[2:0]

invalidate
reset_n output[3:0]

validate

7:5 wrdata[2:0]

wren

tag_valid_array_3