Lenovo G580 Compal La-7981p r1.0 Schematics

A B C D E
1 1
2
Compal Confidential 2
QIWG5/QIWG6 DIS M/B Schematics Document

Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
nVIDIA N13X
2012-02-01
3 3
LA-7981P
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7981P
Date: Wednesday, February 15, 2012 Sheet 1 of 60
A B C D E
A B C D E
Compal confidential ZZZ ZZZ1 ZZZ2 ZZZ3 ZZZ4 QIWG5

File Name : QIWG5/QIWG6 LA7981 LS7981P CardReader/B
G5_DAZ@ G5_DA@ G5_DA@ G5_DA@ G5_DA@
LS7982P USB/B
DAZ_PCB
DAZ0N100101
DA_PCB
DA80000Q010
DA_PCB
DA400016P10
DA_PCB
DA400016Q10
DA_PCB
DA400018T10
LS7983P PWR/B
Page23-32
ZZZ5 ZZZ7 ZZZ6 ZZZ8 ZZZ9 ZZZ10 ZZZ11
1
nVIDIA N13M-GE LA7981 QIWG6 1
nVIDIA N13P-GL
G6_DAZ@ G6_DA@ G6_DA@ G6_DA@ G6_DA@ G6_DA@ G6_DA@ LS7981P CardReader/B
DAZ_PCB DA_PCB DA_PCB DA_PCB DA_PCB DA_PCB DA_PCB
Intel DAZ0N200101 DA80000Q010 DA400016P10 DA400016Q10 DA400016R10 DA400016S10 DA400018T10 LS7982P USB/B
LS7983P PWR/B
Ivy Bridge LS7984P LED/B
VRAM 128*16 PCI-E x16 DDR3 SO-DIMM *2 LS7985P ODD/B
DDR3*8 Socket-rPGA988B BANK 0, 1, 2, 3 Page12-13
37.5mm*37.5mm
Dual Channel Up to 8GB
HDMI Page35 Page5-11DDR3 1066MHz(1.5V)
DDR3 1333MHz(1.5V)
Connector DDR3 1600MHz(1.5V)
100MHz
Page34 2.7GT/s FDI *8 DMI *4
CRT
2 Connector Intel Audio Codec 2 channel speaker
Page41
2
AZALIA Conexant
LVDS Page33 Panther Point CX20671-21Z
Int. MIC x1 Page41
Connector HM75 / HM76
Page41
Audio Jacks Page43
FCBGA 989
USB3.0 *2(Left) 25mm*25mm USB2.0 *14
Camera Conn.Page33
PCI-E x1 *6
Option Page45
SATA *6 BlueTooth Conn.
Page40
USB3.0 Page14-22
Renesas
SPIROM Mini Card Slot *1
Page36
uPD720202
BIOS Page14
3 LPC BUS Card Reader Page43 3
Arthros
Page42 Reltek
AR8161(GLAN) EC RTS5178 for SDR50
SDXC/MMC
AR8162(10/100) ENE KB9012
Page37
USB2.0 *2(Right)
Page38 Page 43;44
RJ-45
Connector Touch Pad Int. KBD USB2.0 *2(Left)
Page43 Page45
Page43
PCI Express PCI-E(WLAN) SATA HDD Page40
Mini Card Slot *1 Thermal Sensor (Port 0/Port 1 support SATA3)
EMC1403 Page39
SATA ODD
WLAN Page36 Page40
4 4

Block Diagram
Custom 1.0
LA-7981P
A B C D E
A B C D E
SIGNAL
Voltage Rails BOARD ID Table STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Board ID PCB Revision Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+5VS
0 0.1 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+3VS
1
power 2 S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
plane +1.5VS
+V1.05S_VCCP
3 S4 (Suspend to Disk)
1
LOW LOW LOW HIGH ON OFF OFF OFF 1
+5VALW +1.5V +VCC_CORE

4
5 S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+B +VGA_CORE
+3VALW +VCC_GFXCORE_AXG
6
+1.8VS
7 Vcc 3.3V +/- 5% Board ID / SKU ID Table for AD channel
State +0.75VS
Ra/Rc/Re 100K +/- 5%
Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max Porject Phase
+1.05VS
G-series
0 0 0 V 0 V 0 V MP
G-series
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V PVT
G-series
2 18K +/- 5% 0.436 V 0.503 V 0.538 V DVT
G-series
3 33K +/- 5% 0.712 V 0.819 V 0.875 V EVT
Y-series
4 56K +/- 5% 1.036 V 1.185 V 1.264 V EVT
Y-series
S0
5 100K +/- 5% 1.453 V 1.650 V 1.759 V DVT
O O O O 6 200K +/- 5% 1.935 V 2.200 V 2.341 V Y-series
PVT
Y-series
7 NC 2.500 V 3.300 V 3.300 V MP
USB Port Table
S3
O O O X 3 External
2 USB 2.0 Port BOM Structure Table 2
USB Port
S5 S4/AC BTO Item BOM Structure
O O X X 0
UHCI0
1 USB Port (Right Side CR-BD)
S5 S4/ Battery only
O X X X 2 USB Port (Left Side) USB3.0
UHCI1 GPU:N13P-GL N13P@
S5 S4/AC & Battery
3 USB Port (Left Side) USB3.0
X X X X EHCI1 GPU:N13M-GE N13M@
don't exist USB3.0
4
UHCI2 HDMI HDMI@
Address 5 Camera
EC SM Bus1 address EC SM Bus2 address Interna-Intel-USB3.0 IU3@
6
UHCI3 External-NEC-USB3.0 EU3@
7
Device Device Address Blue Tooth BT@
Smart Battery 0001 011X b Thermal Sensor F75303M 1001_101xb
8
UHCI4 Connector ME@
9 USB/B (Right Side USB-BD)
45 LEVEL 45@
10 Mini Card(WLAN)
PCH SM Bus address EHCI2 UHCI5 10/100 LAN 8162@
11 Card Reader
GIGA LAN GIGA@
12
Device Address UHCI6 LAN LDO Mode LDO@
DDR DIMM0 1001 000Xb
13 Blue Tooth
LAN Switch mode SWR@
DDR DIMM2 1001 010Xb Cameara CMOS@
3 3
For QIWG5 (14") 14@

NV-GPU SM Bus address For QIWG6 (15") 15@
Unpop @
Device Address G5/G6/G9(Low/Mid END) nonBBH@
Internal thermal sensor 1001 111Xb (0x9E)
G9 High-END BBH@
G9 G9 @
G5/G6/G9(Low/Mid END) 15_nonBBH@
SMBUS Control Table

Thermal
WLAN Sensor
SOURCE VGA BATT KB9012 SODIMM WWAN PCH
SMB_EC_CK1
SMB_EC_DA1
KB9012 X V
+3VALW
X X X X X
+3VALW
SMB_EC_CK2
SMB_EC_DA2
KB9012 X X X X X X V
+3VS
+3VALW
SMBCLK
X X X V V X X
4 4
PCH
SMBDATA +3VALW +3VS +3VS
SML0CLK
SML0DATA
PCH
+3VALW
X X X X X X X
SML1CLK
SML1DATA
PCH
+3VALW +3VS
V X V
+3VS
X X V
+3VS
X Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
Notes List
B 1.0
LA-7981P
A B C D E
5 4 3 2 1
Hot plug detect for IFP link C
VGA and GDDR3 Voltage Rails (N13x GPIO) Performance Mode P0 TDP at Tj = 102 C* (GDDR3)
FBVDDQ PCI Express I/O and I/O and Other
GPIO I/O ACTIVE Function Description GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.8V) (1.05V) (3.3V)
GPIO0 OUT - GPU VID4 Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)
D D
GPIO1 OUT - GPU VID3 N13P-GL
64bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
1GB
GPIO2 OUT H Panel Back-Light brightness(PWM capable) GDDR3
GPIO3 OUT H Panel Power Enable

Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
GPIO4 OUT H Panel Back-Light On/Off (PWM)
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
GPIO5 OUT - GPU VID1 ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
GPIO6 OUT - GPU VID2
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
GPIO7 OUT N/A STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
GPIO8 I/O - Thermal Catastrophic Over Temperature
STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO9 OUT - Thermal Alert STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
CHANGE_GEN3
GPIO10 OUT - Memory VREF Control
GPIO11 OUT - GPU VID0 Device ID

C C
N13P-GL
GPIO12 IN AC Power Detect Input (10K pull low) (28nm) ??
GPIO13 OUT - GPU VID5 N13M-GE

(28nm) ???
GPIO14 OUT N/A
GPIO15 IN Hot plug detect for IFP link C

GPU FB Memory (GDDR3) ROM_SO ROM_SCLK ROM_SI STRAP2 STRAP1 STRAP0
GPIO16 OUT N/A
Samsung K4G10325FG-HC04
GPIO17 IN N/A 2500MHz
32Mx32 PD 10K PD 15K PD 20K PU 20K PD 35K PU 45K
GPIO18 IN Hot Plug Detect for IFPE
Hynix H5GQ1H24BFR-T2C
GPIO19 IN N/A 2500MHz
N13P-GL 32Mx32 PD 10K PD 15K PD 15K PU 20K PD 35K PU 45K
N13M-GE
Samsung K4G20325FG-HC04
2500MHz
B
+3VS_VGA B
Hynix H5GQ2H24MFR-T2C
+VGA_CORE 2500MHz
tNVVDD >0
+1.5VS_VGA
X76
tFBVDDQ >0
+1.05VS_VGA
tPEX_VDD >0
1. all power rail ramp up time should be larger than 40us
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
A A
Tpower-off <10ms

1.all GPU power rails should be turned off within 10ms
VGA Notes List
Custom 0.2
LA-7981P
Date: Tuesday, February 14, 2012 Sheet 4 of 60
5 4 3 2 1
5 4 3 2 1
PEG_ICOMPI and RCOMPO signals should be

shorted and routed
with - max length = 500 mils - typical
+V1.05S_VCCP impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
1
max length = 500 mils
R1
D
24.9_0402_1% - typical impedance = 14.5 mohms D
JCPU1A
2
J22 PEG_COMP
PEG_ICOMPI
PEG_ICOMPO J21
<16> DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22
<16> DMI_CRX_PTX_N1 B25 DMI_RX#[1]
<16> DMI_CRX_PTX_N2 A25 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] <23>
<16> DMI_CRX_PTX_N3 B24 K33 PCIE_CRX_GTX_N15
DMI_RX#[3] PEG_RX#[0] PCIE_CRX_GTX_N14
PEG_RX#[1] M35
<16> DMI_CRX_PTX_P0 B28 L34 PCIE_CRX_GTX_N13
DMI_RX[0] PEG_RX#[2] PCIE_CRX_GTX_N12
<16> DMI_CRX_PTX_P1 B26 DMI_RX[1] PEG_RX#[3] J35 PEG Static Lane Reversal - CFG2 is for the 16x
<16> DMI_CRX_PTX_P2 A24 J32 PCIE_CRX_GTX_N11
DMI
DMI_RX[2] PEG_RX#[4] PCIE_CRX_GTX_N10
<16> DMI_CRX_PTX_P3 B23 DMI_RX[3] PEG_RX#[5] H34
H31 PCIE_CRX_GTX_N9 1: Normal Operation; Lane # definition matches
PEG_RX#[6] PCIE_CRX_GTX_N8
<16> DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33 CFG2 socket pin map definition
E22 G30 PCIE_CRX_GTX_N7
<16> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
F21 F35 PCIE_CRX_GTX_N6
<16> DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
D21 E34 PCIE_CRX_GTX_N5 0:Lane Reversed
<16>
<16>
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0 G22
DMI_TX#[3]
DMI_TX[0]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
E32
D33
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3 *
D22 D31 PCIE_CRX_GTX_N2
<16> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
F20 B33 PCIE_CRX_GTX_N1
PCI EXPRESS* - GRAPHICS

C21 C32 PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P[0..15] <23>
J33 PCIE_CRX_GTX_P15
PEG_RX[0] PCIE_CRX_GTX_P14
PEG_RX[1] L35
K34 PCIE_CRX_GTX_P13
<16> FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35
C H19 H32 PCIE_CRX_GTX_P11 C
<16> FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
E19 G34 PCIE_CRX_GTX_P10
F18 G31 PCIE_CRX_GTX_P9
Intel(R) FDI
B21 F33 PCIE_CRX_GTX_P8
C20 F30 PCIE_CRX_GTX_P7
D18 E35 PCIE_CRX_GTX_P6
E17 E33 PCIE_CRX_GTX_P5
F32 PCIE_CRX_GTX_P4
PEG_RX[12] D34
A22 E31 PCIE_CRX_GTX_P2
<16> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
G19 C33 PCIE_CRX_GTX_P1
E20 B32 PCIE_CRX_GTX_P0
<16> FDI_CTX_PRX_P3 G18 FDI0_TX[3] PCIE_CTX_GRX_N[0..15] <23>
B20 M29 PCIE_CTX_GRX_C_N15 C1 1 N13P@
2 0.1U_0402_10V7K PCIE_CTX_GRX_N15
<16> FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32 PCIE_CTX_GRX_C_N14 C2 1 N13P@
D19 M31 PCIE_CTX_GRX_C_N13 C3 1 N13P@
F17 L32 PCIE_CTX_GRX_C_N12 C4 1 N13P@
L29 PCIE_CTX_GRX_C_N11 C5 1 N13P@
PEG_TX#[4] PCIE_CTX_GRX_C_N10 C6 N13P@ PCIE_CTX_GRX_N10
<16> FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 1 2 0.1U_0402_10V7K
+V1.05S_VCCP J17 K28 PCIE_CTX_GRX_C_N9 C7 1 N13P@
<16> FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6]
J30 PCIE_CTX_GRX_C_N8 C8 1 N13P@
PEG_TX#[7] PCIE_CTX_GRX_C_N7 C9
<16> FDI_INT H20 FDI_INT PEG_TX#[8] J28 1 2 0.1U_0402_10V7K PCIE_CTX_GRX_N7
H29 PCIE_CTX_GRX_C_N6 C10 1 2 0.1U_0402_10V7K PCIE_CTX_GRX_N6
PEG_TX#[9]
1
<16> FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_C_N5 C11 1 2 0.1U_0402_10V7K PCIE_CTX_GRX_N5

R7 FDI0_LSYNC PEG_TX#[10] PCIE_CTX_GRX_C_N4 C12
<16> FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29 1 2 0.1U_0402_10V7K PCIE_CTX_GRX_N4
24.9_0402_1% F27 PCIE_CTX_GRX_C_N3 C13 1 2 0.1U_0402_10V7K PCIE_CTX_GRX_N3
PEG_TX#[12] PCIE_CTX_GRX_C_N2 C14
PEG_TX#[13] D28 1 2 0.1U_0402_10V7K PCIE_CTX_GRX_N2
F26 PCIE_CTX_GRX_C_N1 C15 1 2 0.1U_0402_10V7K PCIE_CTX_GRX_N1
2
PEG_TX#[14] PCIE_CTX_GRX_C_N0 C16 PCIE_CTX_GRX_N0

PEG_TX#[15] E25 1 2 0.1U_0402_10V7K
EDP_COMP A18
B eDP_COMPIO PCIE_CTX_GRX_P[0..15] <23> B
eDP_COMPIO and ICOMPO signals A17 M28 PCIE_CTX_GRX_C_P15 C17 1 N13P@
2 0.1U_0402_10V7K PCIE_CTX_GRX_P15
eDP_HPD eDP_ICOMPO PEG_TX[0] PCIE_CTX_GRX_C_P14 C18 N13P@
B16 M33 1 2 0.1U_0402_10V7K PCIE_CTX_GRX_P14
should be shorted near balls eDP_HPD# PEG_TX[1]
M30 PCIE_CTX_GRX_C_P13 C19 1 N13P@
PEG_TX[2] PCIE_CTX_GRX_C_P12 C20 N13P@ PCIE_CTX_GRX_P12
and routed with typical PEG_TX[3] L31 1 2 0.1U_0402_10V7K
C15 L28 PCIE_CTX_GRX_C_P11 C21 1 N13P@
impedance <25 mohms D15
eDP_AUX PEG_TX[4]
K30 PCIE_CTX_GRX_C_P10 C22 1 N13P@
eDP_AUX# PEG_TX[5] PCIE_CTX_GRX_C_P9 C23 N13P@
K27 1 2 0.1U_0402_10V7K PCIE_CTX_GRX_P9
eDP
PEG_TX[6] PCIE_CTX_GRX_C_P8 C24 N13P@

PEG_TX[7] J29 1 2 0.1U_0402_10V7K PCIE_CTX_GRX_P8
C17 J27 PCIE_CTX_GRX_C_P7 C25 1 2 0.1U_0402_10V7K PCIE_CTX_GRX_P7
eDP_TX[0] PEG_TX[8] PCIE_CTX_GRX_C_P6 C26
F16 eDP_TX[1] PEG_TX[9] H28 1 2 0.1U_0402_10V7K PCIE_CTX_GRX_P6
C16 G28 PCIE_CTX_GRX_C_P5 C27 1 2 0.1U_0402_10V7K PCIE_CTX_GRX_P5
eDP_TX[2] PEG_TX[10] PCIE_CTX_GRX_C_P4 C28
G15 eDP_TX[3] PEG_TX[11] E28 1 2 0.1U_0402_10V7K PCIE_CTX_GRX_P4
F28 PCIE_CTX_GRX_C_P3 C29 1 2 0.1U_0402_10V7K PCIE_CTX_GRX_P3
PEG_TX[12] PCIE_CTX_GRX_C_P2 C30 PCIE_CTX_GRX_P2
C18 eDP_TX#[0] PEG_TX[13] D27 1 2 0.1U_0402_10V7K
E16 E26 PCIE_CTX_GRX_C_P1 C31 1 2 0.1U_0402_10V7K PCIE_CTX_GRX_P1
eDP_TX#[1] PEG_TX[14] PCIE_CTX_GRX_C_P0 C32
D16 eDP_TX#[2] PEG_TX[15] D25 1 2 0.1U_0402_10V7K PCIE_CTX_GRX_P0
F15 eDP_TX#[3]
TYCO_2013620-2_IVY BRIDGE
A A
Security Classification Compal Secret Data

PROCESSOR(1/7) DMI,FDI,PEG
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
JCPU1B
D R10;R11 put on U4 side D
@ R10
A28 CLK_CPU_DMI_R 0_0402_5% 1 2
BCLK CLK_CPU_DMII#_R 0_0402_5% CLK_CPU_DMI <15>
C26 A27 1 2
MISC
CLOCKS
<19> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <15>
@
R11
AN34
SKTOCC# R12
DPLL_REF_CLK
A16 2 1 1K_0402_5%
+V1.05S_VCCP A15 2 R13 1 1K_0402_5%
DPLL_REF_CLK# +V1.05S_VCCP
T48 H_CATERR# AL33 CATERR#

R9 1
62_0402_5%
THERMAL
AN33 R8 H_DRAMRST#
<19,42> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
2
R15
DDR3
MISC
56_0402_5%
<42,48> H_PROCHOT# H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 2 R16 1 140_0402_1%
PROCHOT# SM_RCOMP[0] SM_RCOMP1 2 R17
SM_RCOMP[1] A5 1 25.5_0402_1%
A4 SM_RCOMP2 2 R18 1 200_0402_1%
SM_RCOMP[2]
<19> H_THRMTRIP# AN32 THERMTRIP# DDR3 Compensation Signals
+V1.05S_VCCP
AP29 XDP_PRDY# T97
PRDY# XDP_PREQ# T98
PREQ# AP27
XDP_TMS R20 2 1 51_0402_5%
AR26 XDP_TCK XDP_TDI R21 2 1 51_0402_5% PU/PD for JTAG signals
C @ R22 TCK XDP_TMS XDP_TDO R23 @ C
AR27 2 1 51_0402_5%
PWR MANAGEMENT
TMS
JTAG & BPM

1 2 H_PM_SYNC_R AM34 AP30 XDP_TRST#
<16> H_PM_SYNC PM_SYNC TRST# XDP_TCK R24 2 1 51_0402_5%
0_0402_5% AR28 XDP_TDI XDP_TRST# R25 2 1 51_0402_5%
TDI XDP_TDO
TDO AP26
0_0402_5%1 R26 2 H_CPUPWRGD_R AP33
<19> H_CPUPWRGD UNCOREPWRGOOD
2
R29 AL35 XDP_DBRESET# R28 2 1 1K_0402_5% +3VS

DBR#
1 R27 1 2 PM_DRAM_PWRGD_R V8
@ C549 130_0402_5% SM_DRAMPWROK
10K_0402_5%
AT28 XDP_BPM#0 T49
100P_0402_50V8J BPM#[0] XDP_BPM#1 T90
AR29
1
2 BPM#[1] XDP_BPM#2 T91

EMI Reserve BUF_CPU_RST# AR33
BPM#[2]
AR30
AT30 XDP_BPM#3 T92
RESET# BPM#[3] XDP_BPM#4 T93
AP32
BPM#[4] XDP_BPM#5 T94
AR31
AT31
AR32
BPM#[7]
+3VALW
1 Buffered reset to CPU

C33
0.1U_0402_16V4Z
+1.5V_CPU_VDDQ
2 +3VS
B B
1
<16> SYS_PWROK 1 R880@ 2

0_0402_5% R30
U1 200_0402_5% +V1.05S_VCCP
1
C34
5
0.1U_0402_16V4Z
2
1 R161 2 1
P
+3VS B 2
10K_0402_5% 4 PM_SYS_PWRGD_BUF R32
O 75_0402_5%
<16> PM_DRAM_PWRGD 2
A
G
5
74AHC1G09GW_TSSOP5 R34 U2
3
@ 43_0402_1% 1 3V
P
R33 BUF_CPU_RST# BUFO_CPU_RST# 4 NC
1 2 Y
39_0402_5% 2 PCH_PLTRST#
A PCH_PLTRST# <18>
G
1
SN74LVC1G07DCKR_SC70-5
1 2
3
D R35 @
<10> RUN_ON_CPU1.5VS3# 2 Q1 @ 0_0402_5%
G 2N7002H_SOT23-3
2
S
3
A A

PROCESSOR(2/7) PM,XDP,CLK
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
JCPU1C JCPU1D
<13> DDR_B_D[0..63]
<12> DDR_A_D[0..63] SA_CLK[0] AB6 M_CLK_DDR0 <12> SB_CLK[0] AE2 M_CLK_DDR2 <13>
SA_CLK#[0] AA6 M_CLK_DDR#0 <12> SB_CLK#[0] AD2 M_CLK_DDR#2 <13>
DDR_A_D0 C5 V9 DDR_B_D0 C9 R9
DDR_A_D1 SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA <12> DDR_B_D1 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <13>
D5 SA_DQ[1] A7 SB_DQ[1]
DDR_A_D2 D3 DDR_B_D2 D10
DDR_A_D3 SA_DQ[2] DDR_B_D3 SB_DQ[2]
D2 C8
D6 AA5 M_CLK_DDR1 <12> A9 AE1 M_CLK_DDR3 <13>
D DDR_A_D5 SA_DQ[4] SA_CLK[1] DDR_B_D5 SB_DQ[4] SB_CLK[1] D
C6 AB5 M_CLK_DDR#1 <12> A8 AD1 M_CLK_DDR#3 <13>
DDR_A_D6 SA_DQ[5] SA_CLK#[1] DDR_B_D6 SB_DQ[5] SB_CLK#[1]
C2 V10 DDR_CKE1_DIMMA <12> D9 R10 DDR_CKE3_DIMMB <13>
DDR_A_D7 SA_DQ[6] SA_CKE[1] DDR_B_D7 SB_DQ[6] SB_CKE[1]
C3 D8
F10 G4
F8 F4
G10 AB4 F1 AB2
DDR_A_D11 SA_DQ[10] RSVD_TP[1] DDR_B_D11 SB_DQ[10] RSVD_TP[11]
G9 AA4 G1 AA2
F9 W9 G5 T9
F7 F5
G8 F2
G7 G2
K4 SA_DQ[16] RSVD_TP[4] AB3 J7 SB_DQ[16] RSVD_TP[14] AA1
DDR_A_D17 K5 AA3 DDR_B_D17 J8 AB1
K1 SA_DQ[18] RSVD_TP[6] W10 K10 SB_DQ[18] RSVD_TP[16] T10
DDR_A_D19 J1 DDR_B_D19 K9
J5 SA_DQ[20] J9 SB_DQ[20]
DDR_A_D21 J4 DDR_B_D21 J10
J2 SA_DQ[22] SA_CS#[0] AK3 DDR_CS0_DIMMA# <12> K8 SB_DQ[22] SB_CS#[0] AD3 DDR_CS2_DIMMB# <13>
DDR_A_D23 K2 AL3 DDR_B_D23 K7 AE3
DDR_A_D24 SA_DQ[23] SA_CS#[1] DDR_CS1_DIMMA# <12> DDR_B_D24 SB_DQ[23] SB_CS#[1] DDR_CS3_DIMMB# <13>
M8 SA_DQ[24] RSVD_TP[7] AG1 M5 SB_DQ[24] RSVD_TP[17] AD6
DDR_A_D25 N10 AH1 DDR_B_D25 N4 AE6
N8 SA_DQ[26] N2 SB_DQ[26]
DDR_A_D27 N7 DDR_B_D27 N1
M10 SA_DQ[28] M4 SB_DQ[28]
DDR_A_D29 M9 AH3 DDR_B_D29 N5 AE4
DDR_A_D30 SA_DQ[29] SA_ODT[0] M_ODT0 <12> DDR_B_D30 SB_DQ[29] SB_ODT[0] M_ODT2 <13>
N9 AG3 M_ODT1 <12> M2 AD4 M_ODT3 <13>
DDR SYSTEM MEMORY B

DDR_A_D31 SA_DQ[30] SA_ODT[1] DDR_B_D31 SB_DQ[30] SB_ODT[1]
DDR SYSTEM MEMORY A

M7 SA_DQ[31] RSVD_TP[9] AG2 M1 SB_DQ[31] RSVD_TP[19] AD5
DDR_A_D32 AG6 AH2 DDR_B_D32 AM5 AE5
AG5 SA_DQ[33] AM6 SB_DQ[33]
DDR_A_D34 AK6 DDR_B_D34 AR3
AK5 SA_DQ[35] AP3 SB_DQ[35]
DDR_A_D36 AH5 DDR_B_D36 AN3
C DDR_A_D37 SA_DQ[36] DDR_A_DQS#0 DDR_A_DQS#[0..7] <12> DDR_B_D37 SB_DQ[36] DDR_B_DQS#0 DDR_B_DQS#[0..7] <13> C
AH6 SA_DQ[37] SA_DQS#[0] C4 AN2 SB_DQ[37] SB_DQS#[0] D7
DDR_A_D38 AJ5 G6 DDR_A_DQS#1 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D39 SA_DQ[38] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ6 SA_DQ[39] SA_DQS#[2] J3 AP2 SB_DQ[39] SB_DQS#[2] K6
DDR_A_D40 AJ8 M6 DDR_A_DQS#3 DDR_B_D40 AP5 N3 DDR_B_DQS#3
AK8 SA_DQ[41] SA_DQS#[4] AL6 AN9 SB_DQ[41] SB_DQS#[4] AN5
DDR_A_D42 AJ9 AM8 DDR_A_DQS#5 DDR_B_D42 AT5 AP9 DDR_B_DQS#5
AK9 SA_DQ[43] SA_DQS#[6] AR12 AT6 SB_DQ[43] SB_DQS#[6] AK12
DDR_A_D44 AH8 AM15 DDR_A_DQS#7 DDR_B_D44 AP6 AP15 DDR_B_DQS#7
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH9 AN8
AL9 AR6
AL8 AR5
AP11 DDR_A_DQS[0..7] <12> AR9 DDR_B_DQS[0..7] <13>
DDR_A_D49 SA_DQ[48] DDR_A_DQS0 DDR_B_D49 SB_DQ[48] DDR_B_DQS0
AN11 D4 AJ11 C7
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AL12 F6 AT8 G3
AM12 K3 AT9 J6
AM11 N6 AH11 M3
AL11 AL5 AR8 AN6
AP12 AM9 AJ12 AP8
AN12 AR11 AH12 AK11
AJ14 AM14 AT11 AP14
DDR_A_D57 SA_DQ[56] SA_DQS[7] DDR_B_D57 SB_DQ[56] SB_DQS[7]
AH14 AN14
AL15 AR14
AK15 AT14
AL14 DDR_A_MA[0..15] <12> AT12 DDR_B_MA[0..15] <13>
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D61 SB_DQ[60] DDR_B_MA0
AK14 AD10 AN15 AA8
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AJ15 W1 AR15 T7
DDR_A_D63 SA_DQ[62] SA_MA[1] DDR_A_MA2 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2
AH15 W2 AT15 R7
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_DQ[63] SB_MA[2] DDR_B_MA3
W7 T6
SA_MA[3] DDR_A_MA4 SB_MA[3] DDR_B_MA4
V3 T2
V2 T4
W3 T3
<12> DDR_A_BS0 AE10 W6 <13> DDR_B_BS0 AA9 R2
B SA_BS[0] SA_MA[7] DDR_A_MA8 SB_BS[0] SB_MA[7] DDR_B_MA8 B
<12> DDR_A_BS1 AF10 V1 <13> DDR_B_BS1 AA7 T5
SA_BS[1] SA_MA[8] DDR_A_MA9 SB_BS[1] SB_MA[8] DDR_B_MA9
<12> DDR_A_BS2 V6 W5 <13> DDR_B_BS2 R6 R3
SA_BS[2] SA_MA[9] DDR_A_MA10 SB_BS[2] SB_MA[9] DDR_B_MA10
AD8 AB7
V4 R1
W4 T1
<12> DDR_A_CAS# AE8 AF8 <13> DDR_B_CAS# AA10 AB10
SA_CAS# SA_MA[13] DDR_A_MA14 SB_CAS# SB_MA[13] DDR_B_MA14
<12> DDR_A_RAS# AD9 V5 <13> DDR_B_RAS# AB8 R5
SA_RAS# SA_MA[14] DDR_A_MA15 SB_RAS# SB_MA[14] DDR_B_MA15
<12> DDR_A_WE# AF9 V7 <13> DDR_B_WE# AB9 R4
SA_WE# SA_MA[15] SB_WE# SB_MA[15]
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE
+1.5V
R02
@ R36 1 2 @ DRAMRST_CNTRL
<15> DRAMRST_CNTRL_PCH DRAMRST_CNTRL <10>
1
0_0402_5%
1 2 R37 R40 0_0402_5%
1K_0402_5%
R38
2
1K_0402_5%
S
<6> H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 DDR3_DRAMRST# <12,13>

2
Q2
R39 LBSS138LT1G_SOT-23-3
G
2
4.99K_0402_1%
1
A A
DRAMRST_CNTRL
1
C35
Eiffel used 0.01u Security Classification Compal Secret Data Compal Electronics, Inc.
0.047U 16V K X7R 0402 Module design used 0.047u
2
PROCESSOR(3/7) DDRIII
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor
CFG2
1
R41
1K_0402_1%
2
D D
Interl request AH26 short GND

JCPU1E check on EVT phase PEG Static Lane Reversal - CFG2 is for the 16x
1: Normal Operation; Lane # definition matches

VCC_DIE_SENSE
AH27 PAD T13 CFG2 socket pin map definition
AK28 CFG[0] VSS_DIE_SENSE AH26 1 2 @
AK29 CFG[1]
CFG2 AL26 R60 0_0402_5% 0:Lane Reversed
CFG4
CFG5
AL27
AK26
CFG[2]
CFG[3]
CFG[4] RSVD28 L7
R02
* CFG4
AL29 CFG[5] RSVD29 AG7
CFG6 AL30 AE7
CFG[6] RSVD30
1
CFG7 AM31 AK2
CFG[7] RSVD31
AM32 CFG[8]
AM30 W8 @ R42
CFG
CFG[9] RSVD32 1K_0402_1%
AM28 CFG[10]
+VCC_GFXCORE_AXG AM26
2
CFG[11]
AN28 CFG[12] RSVD33 AT26
+VCC_CORE AN31 AM33
CFG[13] RSVD34
AN26 CFG[14] RSVD35 AJ27
2
AM27 CFG[15]
R252 AK31 CFG[16]
49.9_0402_1% AN29 CFG[17]
2
Display Port Presence Strap

R253
1
49.9_0402_1% RSVD37 T8
C C
J16 1 : Disabled; No Physical Display Port
VCC_AXG_VAL_SENSE AJ31
RSVD38
H16 CFG4 * attached to Embedded Display Port
1
R82 1 @ VSS_AXG_VAL_SENSE VAXG_VAL_SENSE RSVD39

2 100_0402_1% AH31 VSSAXG_VAL_SENSE RSVD40 G16
VCC_VAL_SENSE AJ33
VSS_VAL_SENSE VCC_VAL_SENSE
R88 1 @ 2 100_0402_1% AH33 VSS_VAL_SENSE 0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
Need PWR add new circuit on 1.05V(refer CRB) AJ26 AR35
RSVD5 RSVD_NCTF1
AT34
RESERVED
RSVD_NCTF2
AT33
VSS_AXG_VAL_SENSE RSVD_NCTF3 CFG6
AP35
RSVD_NCTF4
AR34
RSVD_NCTF5 CFG5
VSS_VAL_SENSE
1
F25
Check F24
RSVD8
RSVD9
N13M@ R43 @ R44
2
F23 1K_0402_1% 1K_0402_1%

R255 R257 RSVD10
D24 B34
RSVD11 RSVD_NCTF6
49.9_0402_1% 49.9_0402_1% G25 A33
2
RSVD12 RSVD_NCTF7
G24 A34
RSVD13 RSVD_NCTF8
E23 B35
1
RSVD14 RSVD_NCTF9
D23 C35
RSVD15 RSVD_NCTF10
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30 AJ32
RSVD20 RSVD51
INTEL 12/28 recommand B31
RSVD21 RSVD52
AK32 PCIE Port Bifurcation Straps
A30
to add RC120, RC121, RC122, RC123 C29
RSVD22
RSVD23
Please place as close as JCPU1 11: (Default) x16 - Device 1 functions 1 and 2 disabled
B
J20
RSVD24
BCLK_ITP
BCLK_ITP#
AN35
AM35 CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2 B
B18 disabled
RSVD25
01: Reserved - (Device 1 function 1 disabled ; function
J15 AT2
2 enabled)
RSVD27 RSVD_NCTF11
RSVD_NCTF12
AT1 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
AR1
RSVD_NCTF13
B1 CFG7
KEY
1
@R45
@ R45
1K_0402_1%
2
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB

CFG7 de assertion
A
0: PEG Wait for BIOS for training A

PROCESSOR(4/7) RSVD,CFG
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
JCPU1F POWER +V1.05S_VCCP

+VCC_CORE
QC=94A 8.5A
DC=53A
AG35 VCC1
AG34 AH13
VCC2 VCCIO1
AG33 AH10
VCC3 VCCIO2
AG32 AG10
D VCC4 VCCIO3 D
AG31 AC10
VCC5 VCCIO4
AG30 Y10
VCC6 VCCIO5
AG29 U10
VCC7 VCCIO6
AG28 P10
VCC8 VCCIO7
AG27 L10
VCC9 VCCIO8
AG26 J14
VCC10 VCCIO9
AF35 J13
VCC11 VCCIO10
AF34 J12
VCC12 VCCIO11
AF33 J11
VCC13 VCCIO12
AF32 H14
VCC14 VCCIO13
AF31 H12
VCC15 VCCIO14
AF30 VCC16 VCCIO15 H11
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13
AF27 G12
PEG AND DDR

VCC19 VCCIO18
AF26 VCC20 VCCIO19 F14
AD35 VCC21 VCCIO20 F13
AD32 VCC24 VCCIO23 E14
AD30 VCC26
AD28 VCC28 VCCIO26 D14
AC35 VCC31 VCCIO29 D11
AC34 VCC32 VCCIO30 C14
AC30 VCC36 VCCIO34 B14
C C
AC29 VCC37 VCCIO35 B12
AC28 VCC38 VCCIO36 A14
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 VCC43 VCCIO40 J23
AA32
VCC44 +V1.05S_VCCP
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35 1
CORE SUPPLY
VCC51
Y34
VCC52 C99
Y33
VCC53 0.1U_0402_10V6K
Y32
VCC54
1
Y31 2
VCC55 R46
Y30
VCC56
Y29 75_0402_5%
VCC57
Y28
VCC58
Y27 VR_SVID_CLK series-resistors close to VR
2
VCC59
Y26
VCC60
V35
VCC61 H_CPU_SVIDALRT#
V34 AJ29 1 R47 2 43_0402_5%
SVID
VCC62 VIDALERT# VR_SVID_ALRT# <55>

V33 AJ30 H_CPU_SVIDCLK 0_0402_5% 1 2 R48 @
VCC63 VIDSCLK VR_SVID_CLK <55>
V32 AJ28 H_CPU_SVIDDAT 0_0402_5% 1 2 R49 @
VCC64 VIDSOUT VR_SVID_DAT <55>
V31
VCC65
V30
VCC66
V29
VCC67
R50 2 1 130_0402_5% +V1.05S_VCCP 0.1uF on power side
V28
B VCC68 B
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
U28
VCC77 VCC_SENCE 100ohm +-1% pull-up to VCC near processor
VCC78
U27
VCC79
U26
VCC80 +VCC_CORE
R35
VCC81
R34
VCC82
R33
VCC83
1
R32
R31
R30
VCC84
VCC85
Trace Impedance =27-33 ohm R51
100_0402_1%
R29
R28
VCC86
VCC87
Trace Length Matc < 25 mils
SENSE LINES
2
VCC88
R27 AJ35 VCCSENSE_R 1 2 R52 @ 0_0402_5%
VCCSENSE <55>
VCC89 VCC_SENSE
R26 AJ34 VSSSENSE_R 1 2 R53 @ 0_0402_5%
VSSSENSE <55>
VCC90 VSS_SENSE
P35
VCC91
P34
VCC92
1
P33
VCC93
P32 B10 VCCIO_SENSE <52,53> 1 R66 @2 R54
VCC94 VCCIO_SENSE VSSIO_SENSE_L R74 2VSSIO_SENSE 100_0402_1%
P31 A10 1 100_0402_1%
VCC95 VSS_SENSE_VCCIO 10_0402_1%
P30
VCC96
P29 @
2
VCC97
P28
VCC98 R74 & R79 put together +V1.05S_VCCP
P27
VCC99 R79
P26 VCC100
A A
VSSIO_SENSE_L <53> 2 1
10_0402_1%
VSS_SENCE 100ohm +-1% pull-down to GND near processor
TYCO_2013620-2_IVY BRIDGE Security Classification Compal Secret Data

PROCESSOR(5/7) PWR,BYPASS
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
+1.5V +1.5V_CPU_VDDQ
@ J1 Q6
1
D LBSS138LT1G_SOT-23-3
1 2
1 2 DRAMRST_CNTRL
1
@ R668 PAD-OPEN 4x4m @ @ +VREF_DQ_DIMMA G DRAMRST_CNTRL <7>
R55 C92 +VREF_DQ_DIMMB R670@
1 2 S
3
<46,53,54> SUSP 220_0402_5% 0.1U_0402_10V6K 1 2 0_0402_5%~D +V_DDR_REFA_R
0_0402_5% 2
1 2 0_0402_5%~D +V_DDR_REFB_R
U3 R671@
1 2
DMN3030LSS-13_SOP8L-8
1
+3VALW +VSB @ D
8 1 AP4800
1
Q3 RUN_ON_CPU1.5VS3# D
7 2 Id=9.6A 2
D 6 3 2N7002_SOT23 G DRAMRST_CNTRL 2 R353 R64 D
1
5 S G 1K_0402_1% 1K_0402_1%
3
1
R03 R56 S @ @
2
@ R667 82K_0402_5% Q9
4
100K_0402_5% LBSS138LT1G_SOT-23-3
2
2
R885 R02 M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3 1 2
1
15K_0402_1% 1
1
D D +VCC_GFXCORE_AXG
1 2 2 Q7 @ 2 Q4 R57 C97
<42,46,53> CPU1.5V_S3_GATE
0_0402_5% @ R58 G 2N7002_SOT23 G 2N7002_SOT23 330K_0402_5% 0.047U_0603_25V7K
1
S S @ 2
2
1 2 R616
<25,42,46,51,52,53,54> SUSP#
0_0402_5% @ R59 10_0402_1%
2
RUN_ON_CPU1.5VS3# <6> VCC_AXG_SENSE <55>
POWER RUN_ON_CPU1.5VS3
1
Check
+VCC_GFXCORE_AXG JCPU1G R89 @
Q5-orignal part
100_0402_1% AP2302GN-HF_SOT23-3
AT24 AK35 SB523020210 +1.5V
SENSE
LINES
2
VAXG1 VAXG_SENSE +1.5V_CPU_VDDQ
AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE <55>
AT21 VAXG3
2
G
AT20 PMV45EN_SOT23-3
VAXG4 R626 Q5 @
AT18 VAXG5
1
AT17 VAXG6
10_0402_1% 3 1
D
AR24 VAXG7
AR23 +V_SM_VREF should R67 R62 @
2
VAXG8 1K_0402_1% 1K_0402_1%
AR21 VAXG9
AR20 have 20 mil trace width
2
VAXG10
AR18 AL1 +V_SM_VREF_CNT 1 R61 @2 +V_SM_VREF
C VAXG11 SM_VREF 0_0402_5% C
AR17 VAXG12
1
AP24 1
VREF
VAXG13
AP23 VAXG14
AP21 C98 R78 R63 @
VAXG15 +V_DDR_REFA_R 0.1U_0402_10V6K 1K_0402_1% 1K_0402_1%
AP20 VAXG16 SA_DIMM_VREFDQ B4
+V_DDR_REFB_R 2
AP18 D1
2
VAXG17 SB_DIMM_VREFDQ
AP17 VAXG18
AN24
VAXG19
AN23
VAXG20
AN21
VAXG21 +1.5V_CPU_VDDQ
AN20
VAXG22
AN18
DDR3 -1.5V RAILS

VAXG23 +1.5V +1.5V_CPU_VDDQ
AN17
VAXG24
AM24 AF7
GRAPHICS
VAXG25 VDDQ1 C396 @
AM23 AF4
VAXG26 VDDQ2 0.1U_0402_10V6K
AM21 AF1 1
VAXG27 VDDQ3
AM20 AC7 1 1 1 1 1 1 1 2
VAXG28 VDDQ4
10U_0603_6.3V6M
C117
10U_0603_6.3V6M
C118
10U_0603_6.3V6M
C119
10U_0603_6.3V6M
C120
10U_0603_6.3V6M
C121
10U_0603_6.3V6M
C122
AM18 AC4 + C123
VAXG29 VDDQ5 330U_2.5V_M C129 @
AM17 AC1
VAXG30 VDDQ6 0.1U_0402_10V6K
AL24 Y7
VAXG31 VDDQ7 2 2 2 2 2 2 2
AL23 Y4 1 2
VAXG32 VDDQ8
AL21 Y1
VAXG33 VDDQ9 C96
AL20 U7
VAXG34 VDDQ10 0.1U_0402_10V6K
AL18 U4
VAXG35 VDDQ11
AL17 U1 1 2
VAXG36 VDDQ12
AK24 P7
VAXG37 VDDQ13 C95
AK23 P4
VAXG38 VDDQ14 0.1U_0402_10V6K
AK21 P1
VAXG39 VDDQ15
AK20 1 2
VAXG40
AK18
VAXG41
AK17
VAXG42
AJ24
VAXG43
AJ23
VAXG44
AJ21
VAXG45 10U +VCCSA
B AJ20 B
VAXG46
AJ18
VAXG47
AJ17 M27 +VCCSA
VAXG48 VCCSA1
SA RAIL
AH24 M26 1 1 1 1 1
VAXG49 VCCSA2
10U_0603_6.3V6M
C124
10U_0603_6.3V6M
C125
10U_0603_6.3V6M
C126
10U_0603_6.3V6M
C127
AH23 L26
VAXG50 VCCSA3 + C128 @
AH21 J26
VAXG51 VCCSA4 330U_D2_2.5VY_R9M
AH20 J25
VAXG52 VCCSA5 2 2 2 2
AH18 J24
VAXG53 VCCSA6 2
AH17 H26
VAXG54 VCCSA7
H25
VCCSA8
1.8V RAIL
H23 +VCCSA_SENSE <52> +3VS

+1.8VS 10U VCCSA_SENSE +3VALW
R69 0_0805_5% 1.5A 1 @ 2
1 2 +1.8VS_VCCPLL B6 R68 0_0402_5%
VCCPLL1
2
A6 C22
MISC
VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 <52>

22U_0805_6.3V6M
C154
22U_0805_6.3V6M
C345
10U_0603_6.3V6M
C130
1U_0402_6.3V6K
C131
1U_0402_6.3V6K
C132
@ 1 1 1 1 1 A2 C24 R75 R76 @

VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 <52>
10K_0402_5% 10K_0402_5%
@ @
1
2 2 2 2 2 A19 H_VCCP_SEL 1 2 @
VCCIO_SEL VCCP_PWRCTRL <52>
R77 0_0402_5%
TYCO_2013620-2_IVY BRIDGE R02
A IVY Bridge drives VCCIO_SEL low A
VCCP_PWRCTRL:0
Sandy Bridge is NC for A19
VCCP_PWRCTRL:1

PROCESSOR(6/7) PWR
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
JCPU1H JCPU1I
AT35 VSS1 VSS81 AJ22

AT32 VSS2 VSS82 AJ19
AT29 VSS3 VSS83 AJ16 T35 VSS161 VSS234 F22
AT27 VSS4 VSS84 AJ13 T34 VSS162 VSS235 F19
AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30
D AT10 VSS10 VSS90 AJ1 T28 VSS168 VSS241 E15 D
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13
AT4 VSS12 VSS92 AH34 T26 VSS170 VSS243 E10
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9
AR25 VSS14 VSS94 AH30 P8 VSS172 VSS245 E8
AR10 VSS19 VSS100 AH19 N35 VSS177 VSS250 E3
AR2 VSS22 VSS103 AH4 N32 VSS180 VSS253 D35
AP34 VSS23 VSS104 AG9 N31 VSS181 VSS254 D32
AP25 VSS26 VSS107 AF6 N28 VSS184 VSS257 D20
AP22 VSS27 VSS108 AF5 N27 VSS185 VSS258 D17
AP19 VSS28 VSS109 AF3 N26 VSS186 VSS259 C34
AP16 VSS29 VSS110 AF2 M34 VSS187 VSS260 C31
AP13 VSS30 VSS111 AE35 L33 VSS188 VSS261 C28
C
AP1 VSS34 VSS115 AE31 L8 VSS192 VSS265 C10 C
AN30 VSS35 VSS116 AE30 L6 VSS193 VSS266 C1
AN27 VSS36 VSS117 AE29 L5 VSS194 VSS267 B22
AN25 AE28 L4 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 VSS40 VSS121 AE9 L1 VSS198 VSS271 B13
AN13 VSS41 VSS122 AD7 K35 VSS199 VSS272 B11
AN10 VSS42 VSS123 AC9 K32 VSS200 VSS273 B9
AM29 VSS45 VSS126 AC5 J34 VSS203 VSS276 B5
AM25 VSS46 VSS127 AC3 J31 VSS204 VSS277 B3
AM22 VSS47 VSS128 AC2 H33 VSS205 VSS278 B2
AM19 VSS48 VSS129 AB35 H30 VSS206 VSS279 A35
AM2 VSS55 VSS136 AB28 H10 VSS213
AM1 VSS56 VSS137 AB27 H9 VSS214
AL34 VSS57 VSS138 AB26 H8 VSS215
AL31 VSS58 VSS139 Y9 H7 VSS216
B AL28 VSS59 VSS140 Y8 H6 VSS217
B
AL13 VSS64 VSS145 W35 H1 VSS222
AL10 VSS65 VSS146 W34 G35 VSS223
AK33 VSS69 VSS150 W30 G23 VSS227
AK22 VSS73 VSS154 W26 F34 VSS231
AK19 VSS74 VSS155 U9 F31 VSS232
AK16 VSS75 VSS156 U8 F29 VSS233
AK13 VSS76 VSS157 U6
AK10 VSS77 VSS158 U5
AK7 VSS78 VSS159 U3
AK4 VSS79 VSS160 U2
AJ25 VSS80
A A
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

PROCESSOR(7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
+1.5V
+VREF_DQ_DIMMA +1.5V +1.5V
1
3A@1.5V
<7> DDR_A_D[0..63]
R70
1K_0402_1% DDR3 SO-DIMM A <7> DDR_A_DQS[0..7]
JDIMM1
<7> DDR_A_DQS#[0..7]
2
+VREF_DQ_DIMMA 1 2
VREF_DQ VSS1 DDR_A_D4
3 VSS2 DQ4 4 <7> DDR_A_MA[0..15]
2.2U_0603_6.3V4Z
0.1U_0402_10V6K
DDR_A_D0 5 6 DDR_A_D5
1 DQ0 DQ5
C134
C133
1 1 DDR_A_D1 7 8
DQ1 VSS3 DDR_A_DQS#0
9 VSS4 DQS#0 10
R71 DDR_A_DM0 11 12 DDR_A_DQS0
1K_0402_1% DM0 DQS0
13 VSS5 VSS6 14
D 2 2 DDR_A_D2 DDR_A_D6 D
15 16
2
DDR_A_D3 DQ2 DQ6 DDR_A_D7

17 DQ3 DQ7 18
19 VSS7 VSS8 20
23 DQ9 DQ13 24
25 VSS9 VSS10 26
DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 DQS1 RESET# 30 DDR3_DRAMRST# <7,13>
31 VSS11 VSS12 32
35 DQ11 DQ15 36
37 VSS13 VSS14 38
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
69 DQ27 DQ31 70
71 VSS25 VSS26 72
C DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA C
<7> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <7>
75 VDD1 VDD2 76
77 78 DDR_A_MA15
DDR_A_BS2 NC1 A15 DDR_A_MA14
<7> DDR_A_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD9 VDD10 100 OSCAN (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
<7> M_CLK_DDR0 M_CLK_DDR0 101 102 M_CLK_DDR1
CK0 CK1 M_CLK_DDR1 <7>
<7> M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1
CK0# CK1# M_CLK_DDR#1 <7>
DDR_A_MA10
105 VDD11 VDD12 106
DDR_A_BS1 +1.5V Layout Note: (10uF_0603_6.3V)*8
107 A10/AP BA1 108 DDR_A_BS1 <7>
<7> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS#
DDR_A_RAS# <7>
Place near DIMM
BA0 RAS#
111 112
<7> DDR_A_WE# DDR_A_WE# 113
VDD13 VDD14
114 DDR_CS0_DIMMA# (0.1uF_402_10V)*4
WE# S0# DDR_CS0_DIMMA# <7>
1
<7> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 <7>
117 118 R72
DDR_A_MA13 VDD15 VDD16 M_ODT1 1K_0402_1%
119 A13 ODT1 120 M_ODT1 <7>
<7> DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122
S1# NC2 +1.5V
123 124
2
VDD17 VDD18 +VREF_CA
125 NCTEST VREF_CA 126
127 VSS27 VSS28 128
0.1U_0402_10V6K
2.2U_0603_6.3V4Z
DDR_A_D32 DDR_A_D36
129 DQ32 DQ36 130 EVT Check
1
C135
C136
DDR_A_D33 131 132 DDR_A_D37 1 1 1
DQ33 DQ37
10U_0603_6.3V6M
C137
10U_0603_6.3V6M
C138
10U_0603_6.3V6M
C139
10U_0603_6.3V6M
C140
10U_0603_6.3V6M
C141
10U_0603_6.3V6M
C142
10U_0603_6.3V6M
C143
10U_0603_6.3V6M
C144
0.1U_0402_10V6K
C145
0.1U_0402_10V6K
C146
0.1U_0402_10V6K
C147
0.1U_0402_10V6K
C148
133 VSS29 VSS30 134 1 1 1 1 1 1 1 1 1 1 1 1
DDR_A_DQS#4 135 136 DDR_A_DM4 R73 + C149 @
B DDR_A_DQS4 DQS#4 DM4 1K_0402_1% 220U_6.3V_M B
137 DQS4 VSS31 138
DDR_A_D38 2 2 @ @
139 140
2
DDR_A_D34 VSS32 DQ38 DDR_A_D39 2 2 2 2 2 2 2 2 2 2 2 2 2
141 DQ34 DQ39 142
DDR_A_D35 143 144
DQ35 VSS33 DDR_A_D44
145 VSS34 DQ44 146
DDR_A_D40 147 148 DDR_A_D45
DDR_A_D41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDR_A_DQS#5
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
153 DM5 DQS5 154
155 VSS37 VSS38 156 VDDQ(1.5V) =
DDR_A_D42 157 158 DDR_A_D46
159 DQ43 DQ47 160 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
161 VSS39 VSS40 162
DDR_A_D48 163 164 DDR_A_D52 6*0603 10uf (PER CONNECTOR) Layout Note:
165 DQ49 DQ53 166
167 168 Place near DIMM
DDR_A_DQS#6 VSS41 VSS42 DDR_A_DM6
169 DQS#6 DM6 170 VTT(0.75V) =
DDR_A_DQS6 171 172 7/28 Update connect GND directly
DQS6 VSS43 DDR_A_D54
173 VSS44 DQ54 174 3*0805 10uf 4*0402 1uf
DDR_A_D50 175 176 DDR_A_D55
DDR_A_D51 DQ50 DQ55 +0.75VS
177 DQ51 VSS45 178 VREF =
179 180 DDR_A_D60 DDR_A_DM0
DDR_A_D56 VSS46 DQ60 DDR_A_D61 DDR_A_DM1
181 DQ56 DQ61 182 1*0402 0.1uf 1*0402 2.2uf
DDR_A_D57 183 184 DDR_A_DM2
DQ57 VSS47 DDR_A_DQS#7 @ @ DDR_A_DM3
185 VSS48 DQS#7 186 VDDSPD (3.3V)=
1U_0402_6.3V6K
C150
1U_0402_6.3V6K
C151
1U_0402_6.3V6K
C152
1U_0402_6.3V6K
C153
DDR_A_DM7 187 188 DDR_A_DQS7 DDR_A_DM4
DM7 DQS7 DDR_A_DM5
189 VSS49 VSS50 190 1*0402 0.1uf 1*0402 2.2uf 1 1 1 1
DDR_A_D58 191 192 DDR_A_D62 DDR_A_DM6
DDR_A_D59 DQ58 DQ62 DDR_A_D63 DDR_A_DM7
193 DQ59 DQ63 194
1 R81 2 195 VSS51 VSS52 196
10K_0402_5% 2 2 2 2
197 SA0 EVENT# 198
199 200 SMB_DATA_S3 Layout Note:
+3VS VDDSPD SDA SMB_DATA_S3 <13,15,36>
2.2U_0603_6.3V4Z
0.1U_0402_10V6K
A 201 202 SMB_CLK_S3 A

SA1 SCL SMB_CLK_S3 <13,15,36>
Place near DIMM
C155
C156
1 1 203 VTT1 VTT2 204 +0.75VS

1 10K_0402_5%
R83
205 206 0.65A@0.75V

G1 G2
2 2 FOX_AS0A626-U4SN-7F
ME@
2

DDRIII-SODIMM SLOT1
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
+1.5V
+VREF_DQ_DIMMB 3A@1.5V
<7> DDR_B_D[0..63]
1
+1.5V +1.5V
<7> DDR_B_DQS[0..7]
R84
1K_0402_1% JDIMM2
<7> DDR_B_DQS#[0..7]
+VREF_DQ_DIMMB 1 2
VREF_DQ VSS1 DDR_B_D4
3 4 <7> DDR_B_MA[0..15]
2
DDR_B_D0 VSS2 DQ4 DDR_B_D5
5 DQ0 DQ5 6
DDR_B_D1 7 8
DQ1 VSS3
2.2U_0603_6.3V4Z
0.1U_0402_10V6K
9 10 DDR_B_DQS#0
1
DDR_B_DM0 VSS4 DQS#0 DDR_B_DQS0
1 1 11 DM0 DQS0 12
13 VSS5 VSS6 14
C158
C157
R85 DDR_B_D2 15 16 DDR_B_D6
1K_0402_1% DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
D 2 2 D
19 20
2
DDR_B_D8 VSS7 VSS8 DDR_B_D12

21 DQ8 DQ12 22
DDR_B_D9 23 24 DDR_B_D13
DQ9 DQ13
25 VSS9 VSS10 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 DQS1 RESET# 30 DDR3_DRAMRST# <7,12>
31 VSS11 VSS12 32
For Arranale only +VREF_DQ_DIMMB DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
supply from a external 1.5V voltage divide 37 38
DDR_B_D16 VSS13 VSS14 DDR_B_D20
circuit. 39 DQ16 DQ20 40
DQ17 DQ21
43 VSS15 VSS16 44
DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_B_D22
DDR_B_D18 VSS18 DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS19 DDR_B_D28
55 VSS20 DQ28 56
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_B_DQS#3
63 DM3 DQS3 64
65 VSS23 VSS24 66
69 DQ27 DQ31 70
71 VSS25 VSS26 72
<7> DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB

CKE0 CKE1 DDR_CKE3_DIMMB <7>
75 VDD1 VDD2 76
C 77 78 DDR_B_MA15 C
DDR_B_BS2 NC1 A15 DDR_B_MA14
<7> DDR_B_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD9 VDD10 100
<7> M_CLK_DDR2 M_CLK_DDR2 101 102 M_CLK_DDR3
CK0 CK1 M_CLK_DDR3 <7>
<7> M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
CK0# CK1# M_CLK_DDR#3 <7>
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <7> +1.5V
DDR_B_BS0 109 110 DDR_B_RAS# Layout Note:
<7> DDR_B_BS0
111
BA0 RAS#
112
DDR_B_RAS# <7> (10uF_0603_6.3V)*8
DDR_B_WE# VDD13 VDD14 DDR_CS2_DIMMB# Place near DIMM
<7> DDR_B_WE# 113 WE# S0# 114 DDR_CS2_DIMMB# <7>
1
DDR_B_CAS# 115 116 M_ODT2
<7> DDR_B_CAS#
117
CAS# ODT0
118
M_ODT2 <7>
R86 (0.1uF_402_10V)*4
DDR_B_MA13 VDD15 VDD16 M_ODT3 1K_0402_1%
119 A13 ODT1 120 M_ODT3 <7>
<7> DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122
S1# NC2
123 124
2
VDD17 VDD18 +VREF_CB
125 NCTEST VREF_CA 126
+1.5V
0.1U_0402_10V6K
2.2U_0603_6.3V4Z
127 VSS27 VSS28 128
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36
1
C159
C160
DDR_B_D33 131 132 DDR_B_D37 1 1
DQ33 DQ37
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
133 VSS29 VSS30 134
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
DDR_B_DQS#4 135 136 DDR_B_DM4 R87
DQS#4 DM4
C161
C162
C163
C164
C165
C166
C167
C168
C169
C170
C171
C172
DDR_B_DQS4 137 138 1K_0402_1% 1 1 1 1 1 1 1 1 1 1 1 1
DQS4 VSS31 DDR_B_D38 2 2
139 140
2
B DDR_B_D34 VSS32 DQ38 DDR_B_D39 B
141 DQ34 DQ39 142
DDR_B_D35 143 144 @ @
DQ35 VSS33 DDR_B_D44 2 2 2 2 2 2 2 2 2 2 2 2
145 VSS34 DQ44 146
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDR_B_DQS#5
153 DM5 DQS5 154 VDDQ(1.5V) =
155 VSS37 VSS38 156
DDR_B_D42 157 158 DDR_B_D46 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
159 DQ43 DQ47 160
161 VSS39 VSS40 162 6*0603 10uf (PER CONNECTOR)
DDR_B_D48 163 164 DDR_B_D52
165 DQ49 DQ53 166 Layout Note:
167 VSS41 VSS42 168 VTT(0.75V) =
DDR_B_DQS#6 169 DQS#6 DM6 170 DDR_B_DM6 Place near DIMM
DDR_B_DQS6 171 172 3*0805 10uf 4*0402 1uf
DQS6 VSS43 DDR_B_D54
173 VSS44 DQ54 174
DDR_B_D50 175 176 DDR_B_D55
DDR_B_D51 DQ50 DQ55
177 DQ51 VSS45 178
DDR_B_D60 +0.75VS
179 VSS46 DQ60 180 1*0402 0.1uf 1*0402 2.2uf
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61 DDR_B_DM0
183 DQ57 VSS47 184 VDDSPD (3.3V)=
185 186 DDR_B_DQS#7 DDR_B_DM1
DDR_B_DM7 VSS48 DQS#7 DDR_B_DQS7 @ @ DDR_B_DM2
187 DM7 DQS7 188 1*0402 0.1uf 1*0402 2.2uf
1U_0402_6.3V6K
C173
1U_0402_6.3V6K
C174
1U_0402_6.3V6K
C175
1U_0402_6.3V6K
C176
189 190 DDR_B_DM3
DDR_B_D58 VSS49 VSS50 DDR_B_D62 DDR_B_DM4
191 DQ58 DQ62 192 1 1 1 1
DDR_B_D59 193 194 DDR_B_D63 DDR_B_DM5
DQ59 DQ63 DDR_B_DM6
195 VSS51 VSS52 196
1 R95 2 197 SA0 EVENT# 198 DDR_B_DM7
10K_0402_5% SMB_DATA_S3 2 2 2 2
199 VDDSPD SDA 200 SMB_DATA_S3 <12,15,36>
1 2 201 202 SMB_CLK_S3
+3VS SA1 SCL SMB_CLK_S3 <12,15,36>
2.2U_0603_6.3V4Z
0.1U_0402_10V6K
R97 10K_0402_5% 203 204 +0.75VS

VTT1 VTT2
C177
C178
A
1 1 0.65A@0.75V Layout Note: A
205 G1 G2 206
Place near DIMM
FOX_AS0A626-U8SN-7F
2 2 ME@

DDRIII-SODIMM SLOT2
0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
PCH_RTCX1
W=20mils W=20mils 1 2 PCH_RTCX2

R98 10M_0402_5%
+RTCVCC +RTCBATT
Y1
R99 1 2
1K_0402_5% 32.768KHZ_12.5PF_CM31532768DZFT
1 2 1 1
C181
1
1 C180 18P_0402_50V8J
C179 CLRP1 18P_0402_50V8J
1U_0603_10V4Z SHORT PADS 2 2
2
2
D D
CMOS U4A
SHORT PADS
CLRP2
+RTCVCC
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 <36,42>
1
R101 1 2 1M_0402_5% SM_INTRUDER# A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 <36,42>
LPC
C183 PCH_RTCX2 C20 B37 LPC_AD2 EC and Mini card debug port
PCH_INTVRMEN RTCX2 FWH2 / LAD2 LPC_AD3 LPC_AD2 <36,42>
R102 1 2 330K_0402_5% 1U_0603_10V4Z C37
2
2 FWH3 / LAD3 LPC_AD3 <36,42>
1 2 PCH_RTCRST# D20
R103 20K_0402_5% RTCRST# LPC_FRAME#
INTVRMEN 1 2 PCH_SRTCRST# G22
FWH4 / LFRAME# D36 LPC_FRAME# <36,42>
SRTCRST# +3VS
： Integrated VRM enable
H： R100 20K_0402_5% E36
* 1 LDRQ0#
1
SHORT PADS
CLRP3
： Integrated VRM disable SM_INTRUDER#
RTC
L： K22 K36 R104 2 1 10K_0402_5%
C182 INTRUDER# LDRQ1# / GPIO23
(INTVRMEN should always be pull high.) 1U_0603_10V4Z PCH_INTVRMEN C17 V5 SERIRQ SERIRQ <42>
2
2 INTVRMEN SERIRQ
AM3 SATA_DTX_C_IRX_N0
+3VS SATA0RXN SATA_DTX_C_IRX_N0 <40>
HDA_BIT_CLK N34 AM1 SATA_DTX_C_IRX_P0
HDA_BCLK SATA0RXP SATA_DTX_C_IRX_P0 <40>
SATA_ITX_C_DRX_N0 0.01U_0402_25V7K 2 1 C184 SATA_ITX_DRX_N0
SATA 6G
SATA0TXN AP7 SATA_ITX_DRX_N0 <40> HDD
R105 1 @ 2 1K_0402_5% HDA_SPKR HDA_SYNC L34 AP5 SATA_ITX_C_DRX_P0 0.01U_0402_25V7K 2 1 C185 SATA_ITX_DRX_P0 SATA_ITX_DRX_P0 <40>
HDA_SYNC SATA0TXP
HIGH= Enable ( No Reboot ) HDA_SPKR T10 AM10 CAP on Conn, side
<41> HDA_SPKR SPKR SATA1RXN
LOW= Disable (Default) AM8
* HDA_RST# K34 HDA_RST#
SATA1RXP
SATA1TXN AP11
SATA1TXP AP10
C +3V_PCH HDA_SDIN0 E34 AD7 SATA_DTX_C_IRX_N2 C
<41> HDA_SDIN0 HDA_SDIN0 SATA2RXN SATA_DTX_C_IRX_N2 <40>
AD5 SATA_DTX_C_IRX_P2 SATA_DTX_C_IRX_P2 <40> ODD
R106 2 @ 1 1K_0402_5% HDA_SDOUT SATA2RXP SATA_ITX_C_DRX_N2
G34 HDA_SDIN1 SATA2TXN AH5 SATA_ITX_C_DRX_N2 <40>
AH4 SATA_ITX_C_DRX_P2 SATA_ITX_C_DRX_P2 <40>
SATA2TXP
Low = Disabled (Default) C34
* HDA_SDIN2
IHDA
High = Enabled [Flash Descriptor Security Overide] SATA3RXN AB8
A34 HDA_SDIN3 SATA3RXP AB10
R109 AF3
0_0402_5% SATA3TXN
AF1
ME_FLASH 1 HDA_SDOUT SATA3TXP
<42> ME_FLASH 2 A36
+3V_PCH HDA_SDO
SATA
Y7
SATA4RXN
Y5
R108 HDA_SYNC PCH_GPIO33 SATA4RXP
2 1 1K_0402_5% R107 1 @ 2 1K_0402_1% C36
HDA_DOCK_EN# / GPIO33 SATA4TXN
AD3
AD1
10K_0402_5% 2 R264 @1 SATA4TXP
+3V_PCH N32
HDA_DOCK_RST# / GPIO13
This signal has a weak internal pull-down Y3
SATA5RXN
On Die PLL VR is supplied by Y1
SATA5RXP
1.5V when smapled high AB3
PCH_JTAG_TCK SATA5TXN
2 R110 1 J3 AB1
* 1.8V when sampled low
Needs to be pulled High for Chief River platfrom
JTAG_TCK SATA5TXP
51_0402_5% PCH_JTAG_TMS H7 Y11 R111
JTAG_TMS SATAICOMPO 37.4_0402_1% +1.05VS_VCC_SATA
JTAG
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
+5VS JTAG_TDI SATAICOMPI
8MB SPI ROM FOR ME

R112 PCH_JTAG_TDO H1
33_0402_5% JTAG_TDO R113 +1.05VS_SATA3
AB12
HDA_BIT_CLK SATA3RCOMPO 49.9_0402_1%
<41> HDA_BITCLK_AUDIO 1 2
& Non-share ROM.
2
G
R114 Q10 AB13 SATA3_COMP 1 2

33_0402_5% LBSS138LT1G_SOT-23-3 SATA3COMPI
1 2 HDA_SYNC_R 3 1 HDA_SYNC
<41> HDA_SYNC_AUDIO
R116 SPI_CLK_PCH_R RBIAS_SATA3
S
T3 AH1 1 2
33_0402_5% SPI_CLK SATA3RBIAS R115 +3VS
2
B HDA_RST# SPI_SB_CS0# 750_0402_1% B

<41> HDA_RST_AUDIO# 1 2 Y14
SPI_CS0#
R118 R878 R291
33_0402_5% 1M_0402_5% R175 @ SPI_SB_CS1# T1 0_0402_5% U6
SPI_CS1#
SPI
1 2 HDA_SDOUT 1 2 P3 SATALED# 2 R117 1 10K_0402_5% SPI_SB_CS1# 1 2 CS1# 1 8 R199

<41> HDA_SDOUT_AUDIO SATALED# +3VS CS# VCC
SPI_SO_R 1 2 SPI_SO1 2 SPI_HOLD#1 0_0402_5%
7
1
SPI_SI PCH_GPIO21 SPI_WP#1 SO HOLD# SPI_CLK1

0_0402_5% V4 V14 2 R119 1 10K_0402_5% +3VS 3 6 1 2 SPI_CLK_PCH_R
SPI_MOSI SATA0GP / GPIO21 WP# SCLK SPI_SI1
R188 4 5 1 2 SPI_SI
SPI_SO_R BBS_BIT0_R GND SI
check with vender U3 P1 2 R187 1 10K_0402_5% +3VS 33_0402_5% R196
+3V_PCH +3V_PCH +3V_PCH SPI_MISO SATA1GP / GPIO19 33_0402_5%
Del Q10 check with codec 16M W25Q16BVSSIG SOIC 8P
PANTHER-POINT_FCBGA989
VDDIO using 3VALW
1
@ @ @ +3VS
R121 R122 R123
200_0402_5% 200_0402_5% 200_0402_5%
SPI_CLK_PCH_R R266 1 2 SPI_WP#1
3.3K_0402_5%
U6 Rersver 4M+2M Solution
2
PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI

1
R221 1 2 SPI_HOLD#1 +3VS

1
@ @ @ R124 3.3K_0402_5%
R125 R126 R128 33_0402_5% R127 1 2 SPI_WP# C191
100_0402_1% 100_0402_1% 100_0402_1% @ 3.3K_0402_5% 1 2
R124;c190 close to U4.T3 pin R130
2
R129 1 2 SPI_HOLD# 0_0402_5% U5 0.1U_0402_16V4Z

2
3.3K_0402_5% SPI_SB_CS0# 1 2 CS# 1 8 R132

C190 SPI_SO_R SPI_SO_L CS# VCC SPI_HOLD# 0_0402_5%
DPDG1.1 1 2 2
SO HOLD#
7
22P_0402_50V8J SPI_WP# 3 6 SPI_CLK_PCH 1 2 SPI_CLK_PCH_R
33_0402_5% WP# SCLK SPI_SI_R
@ 4
GND SI
5 1 2 SPI_SI
R131 R133
32M W25Q32BVSSIG SOIC 8P 33_0402_5%
A A

PCH (1/9) SATA,HDA,SPI, LPC, XDP
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
U4B
Q60A
2N7002DW-T/R7_SOT363-6
PCIE_PRX_DTX_N1 BG34 6 1 SMB_CLK_S3
<37> PCIE_PRX_DTX_N1 PERN1 SMB_CLK_S3 <12,13,36>
LAN <37> PCIE_PRX_DTX_P1 PCIE_PRX_DTX_P1 BJ34 E12 PCH_GPI011 2 R134 1 +3V_PCH
C192 PCIE_PTX_DRX_N1 PERP1 SMBALERT# / GPIO11
1 2 0.1U_0402_10V7K AV32 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
<37> PCIE_PTX_C_DRX_N1
C193 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P1 AU32
PETN1
H14 PCH_SMBCLK 1 R136 2 1 2 R137 DIMM1
2
<37> PCIE_PTX_C_DRX_P1 PETP1 SMBCLK
<36> PCIE_PRX_DTX_N2 PCIE_PRX_DTX_N2 BE34 PERN2 SMBDATA C9 PCH_SMBDATA

+3V_PCH
1 2 1
+3VS
2 DIMM2
5
PCIE_PRX_DTX_P2 BF34 R135 R138
WLAN
<36> PCIE_PRX_DTX_P2
<36> PCIE_PTX_C_DRX_N2
C194 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N2 BB32
PERP2
PETN2
2.2K_0402_5% 2.2K_0402_5% MINI CARD
C195 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P2 AY32 3 4 SMB_DATA_S3
<36> PCIE_PTX_C_DRX_P2 PETP2 SMB_DATA_S3 <12,13,36>
SMBUS
A12 DRAMRST_CNTRL_PCH
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <7>
BG36 2N7002DW-T/R7_SOT363-6
PERN3 PCH_SML0CLK
BJ36 C8 Q60B
D PERP3 SML0CLK D
AV34 2 R139 1 +3V_PCH
PETN3 PCH_SML0DATA 1K_0402_5%
AU34 G12
PETP3 SML0DATA Q61A
PCIE_PRX_DTX_N4 BF36 2 R140 1 10K_0402_5% 2N7002DW-T/R7_SOT363-6
<45> PCIE_PRX_DTX_N4 PERN4 +3V_PCH
PCIE_PRX_DTX_P4 BE36 6 1 EC_SMB_CK2
<45> PCIE_PRX_DTX_P4 PERP4 EC_SMB_CK2 <23,39,42>
USB3.0 C309 EU3@ 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N4 AY34 C13 PCH_HOT#
<45> PCIE_PTX_C_DRX_N4 PCIE_PTX_DRX_P4 PETN4 SML1ALERT# / PCHHOT# / GPIO74 PCH_HOT# <42>
C308 EU3@ 1 2 0.1U_0402_10V7K BB34 2.2K_0402_5%
<45> PCIE_PTX_C_DRX_P4 PETP4
E14 SML1CLK 1 R141 2 VGA
2
SML1CLK / GPIO58
PCI-E*
CAP on Conn, side BG37
BH37
PERN5
PERP5 SML1DATA / GPIO75
M16 SML1DATA
+3V_PCH
1 2
+3VS EC
5
AY36 R142
BB36
PETN5
PETP5
2.2K_0402_5% thermal sensor
3 4 EC_SMB_DA2
EC_SMB_DA2 <23,39,42>
BJ38 PERN6
BG38 2N7002DW-T/R7_SOT363-6
PERP6
Controller
AU36 PETN6 CL_CLK1 M7 Q61B
AV36 +3V_PCH
PETP6 +3V_PCH
Link
BG40 PERN7 CL_DATA1 T11
2
BJ40 PERP7
AY40 PETN7
2
BB40 P10 R143
PETP7 CL_RST1# R544 R545
10K_0402_5%
BE38 2.2K_0402_5% 2.2K_0402_5%
1
PERN8 R144 0_0402_5%
BC38 PERP8
AW38 1 2
1
PETN8 CLK_REQ_VGA# <23> PCH_SML0CLK
AY38 PETP8
PEG_A_CLKRQ# / GPIO47 M10 PEG_CLKREQ#_R 1 R145 2 10K_0402_5% PCH_SML0DATA

R153 1 2 0_0402_5% CLK_PCIE_LAN#_R Y40 @
<37> CLK_PCIE_LAN# CLK_PCIE_LAN_R CLKOUT_PCIE0N
LAN R154 1 2 0_0402_5% Y39
<37> CLK_PCIE_LAN CLKOUT_PCIE0P CLK_PCIE_VGA#_R R146 1 CLK_PCIE_VGA#
CLKOUT_PEG_A_N AB37 2 0_0402_5% CLK_PCIE_VGA# <23>
C R151 1 CLKREQ_LAN#_R CLK_PCIE_VGA_R R148 1 CLK_PCIE_VGA C
2 0_0402_5% 2 0_0402_5%
CLOCKS
<37> CLKREQ_LAN# J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38 CLK_PCIE_VGA <23>
+3V_PCH R152 2 1 10K_0402_5%
R149 1 2 0_0402_5% CLK_PCIE_WLAN1#_R AB49 AV22 CLK_CPU_DMI#

<36> CLK_PCIE_WLAN1# CLK_PCIE_WLAN1_R CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI CLK_CPU_DMI# <6>
R150 1 2 0_0402_5% AB47 AU22
<36> CLK_PCIE_WLAN1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <6>
WLAN
<36> CLKREQ_WLAN# R156 1 2 0_0402_5% CLKREQ_WLAN#_R M1
R158 2 PCIECLKRQ1# / GPIO18
+3VS 1 10K_0402_5% AM12
CLKOUT_DP_N
AM13
CLKOUT_DP_P
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P CLK_BUF_CPU_DMI# R155 1 10K_0402_5%
BF18 2
R147 PCH_GPIO20 CLKIN_DMI_N CLK_BUF_CPU_DMI
+3VS 2 1 10K_0402_5% V10
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
BE18 R157 1 2 10K_0402_5%
R334 1 EU3@ 2 0_0402_5% CLK_USB30# Y37 BJ30 CLKIN_DMI2# R159 1 2 10K_0402_5%

<45> CLK_PCIE_USB30# CLKOUT_PCIE3N CLKIN_GND1_N
R330 1 EU3@ 2 0_0402_5% CLK_USB30 Y36 BG30 CLKIN_DMI2 R160 1 2 10K_0402_5%
<45> CLK_PCIE_USB30 CLKOUT_PCIE3P CLKIN_GND1_P
USB3.0
R326 1 EU3@ 2 0_0402_5% CLKREQ_USB30#_R A8
<45> CLKREQ_USB30# PCIECLKRQ3# / GPIO25
R301 2 1 10K_0402_5% G24 CLK_BUF_DREF_96M# R162 1 2 10K_0402_5%
+3V_PCH CLKIN_DOT_96N
E24 CLK_BUF_DREF_96M R163 1 2 10K_0402_5%
CLKIN_DOT_96P
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P CLK_BUF_PCIE_SATA# R164 1 10K_0402_5%
AK7 2
R165 PCH_GPIO26 CLKIN_SATA_N CLK_BUF_PCIE_SATA R166 1
+3V_PCH 2 1 10K_0402_5% L12 AK5 2 10K_0402_5%
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
V45 K45 CLK_BUF_ICH_14M R167 1 2 10K_0402_5%

CLKOUT_PCIE5N REFCLK14IN
V46
CLKOUT_PCIE5P
R168 2 1 10K_0402_5% PCH_GPIO44 L14 H45 CLK_PCI_LPBACK
+3V_PCH PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK <18>
B XTAL25_IN B
AB42 V47 XTAL25_IN
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT XTAL25_OUT
AB40 V49 1 2
CLKOUT_PEG_B_P XTAL25_OUT R169 1M_0402_5%
R170 2 1 10K_0402_5% PCH_GPIO56 E6 R171 +1.05VS_VCCDIFFCLKN
+3V_PCH PEG_B_CLKRQ# / GPIO56 90.9_0402_1% 3 4
XCLK_RCOMP OSC NC
Y47 1 2
XCLK_RCOMP
V40 2 1
CLKOUT_PCIE6N NC OSC
V42
CLKOUT_PCIE6P Y2
R172 2 110K_0402_5% PCH_GPIO45 T13 1 25MHZ_10PF_7V25000014 1
+3V_PCH PCIECLKRQ6# / GPIO45 27M_SSC C196 C197
V38 K43 12P_0402_50V8J R02 12P_0402_50V8J
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS
V37
CLKOUT_PCIE7P 2 2
F47
R174 PCH_GPIO46 CLKOUTFLEX1 / GPIO65
+3V_PCH 2 1 10K_0402_5% K12
PCIECLKRQ7# / GPIO46 LAN_48M
H47 1 R207 @2 22_0402_5% PCH_LAN_48M
CLKOUTFLEX2 / GPIO66
AK14
PCIE_CLK_8N AK13 CLKOUT_ITPXDP_N PCH_GPIO67
K49 PCH_GPIO67 <19>
PCIE_CLK_8P CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67
BIOS Request SKU ID
A A

PCH (2/9) PCIE, SMBUS, CLK
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
D D
U4C
DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

<5> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <5>
U15 DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
MC74VHC1G08DFT2G SC70 5P DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
3
<5> DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3 FDI_CTX_PRX_N3 <5>

DMI3RXN FDI_RXN3 FDI_CTX_PRX_N4
1 BC12
G
<55> VGATE A FDI_RXN4 FDI_CTX_PRX_N4 <5>

Y 4 SYS_PWROK SYS_PWROK <6> <5> DMI_CTX_PRX_P0
DMI_CTX_PRX_P0 BE24 DMI0RXP FDI_RXN5 BJ12 FDI_CTX_PRX_N5
FDI_CTX_PRX_N5 <5>
PCH_PWROK 2 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
B <5> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <5>
P
<5> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 FDI_CTX_PRX_N7 <5>

DMI_CTX_PRX_P3 DMI2RXP FDI_RXN7
<5> DMI_CTX_PRX_P3 BJ20
5
DMI3RXP
1
BG14 FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 <5>

R180 @ DMI_CRX_PTX_N0 FDI_RXP0 FDI_CTX_PRX_P1
<5> DMI_CRX_PTX_N0 AW24 DMI0TXN FDI_RXP1 BB14 FDI_CTX_PRX_P1 <5>
100K_0402_1% DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
<5> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <5>
+3VS DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 <5>
<5> DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P4
AV18 BE12 FDI_CTX_PRX_P4 <5>
2
<5> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4
DMI
FDI
BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 <5>
DMI_CRX_PTX_P0 FDI_RXP5 FDI_CTX_PRX_P6
<5> DMI_CRX_PTX_P0 AY24 DMI0TXP FDI_RXP6 BJ10 FDI_CTX_PRX_P6 <5>
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7
<5> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <5>
DMI_CRX_PTX_P2 AY18
<5> DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI2TXP
<5> DMI_CRX_PTX_P3 AU18 DMI3TXP
AW16 FDI_INT
FDI_INT FDI_INT <5>
+1.05VS BJ24 AV12 FDI_FSYNC0
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <5> +RTCVCC
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <5>
R177 49.9_0402_1%
*
1
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
C DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <5> C
R178 750_0402_1% R179
4mil width and place BB10 FDI_LSYNC1 DSWODVREN - On Die DSW VR Enable 330K_0402_5%
FDI_LSYNC1 FDI_LSYNC1 <5>
within 500mil of the PCH H：Enable
L：Disable
2
SUSACK# is only used on platform A18 DSWODVREN
DSWVRMEN
that support the Deep Sx state.
System Power Management
1
T72 SUSACK# C12 E22 PCH_DPWROK R02 @1 R181 2 0_0402_5% PCH_RSMRST#_R
SUSACK# DPWROK R183
R02 @ 330K_0402_5%
2 1 SYS_RST# K3 B9 WAKE# 1 R185 2 0_0402_5% +3VS
+3VS SYS_RESET# WAKE# PCIE_WAKE# <36,37,45> @
10K_0402_5% R184 1 2 10K_0402_5% +3V_PCH
2
R186 @ R189 8.2K_0402_5%
SYS_PWROK P12 N3 PM_CLKRUN# 1 2
SYS_PWROK CLKRUN# / GPIO32
@ R299 10K_0402_5%
AEPWROK can be connect to PCH_PWROK1 2 PCH_POK L22 G8 SUS_STAT# T74 2 1
<42> PCH_PWROK PWROK SUS_STAT# / GPIO61
PWROK if iAMT disable R190 R02 0_0402_5%
R191 1 @ 2 APWROK L10 N14

<42> PCH_APWROK APWROK SUSCLK / GPIO62 SUSCLK <42>
PCH_POK 1 2 APWROK 0_0402_5% R302
@
0_0402_5% PM_DRAM_PWRGD B13 D10
<6> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# <42>
@
+3VS 1 2 PCH_RSMRST#_R C21 H4
<42> EC_RSMRST# R02 RSMRST# SLP_S4# PM_SLP_S4# <42>
@ R193 0_0402_5%
+3V_PCH 2 R556 1 200_0402_5%
SUSWARN# K16 F4
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# <42>
2 R192 1 300_0402_5% PM_DRAM_PWRGD Can be left NC
B @ PBTN_OUT#_R SLP_A# T99 B
<42> PBTN_OUT# 1 2 E20
PWRBTN# SLP_A#
G10 when IAMT is not
R194 2 1 10K_0402_5% SUSWARN# R198 R02 0_0402_5% support on the
R195 AC_PRESENT_R AC_PRESENT_R PM_SLP_SUS# platfrom
1 2 200K_0402_5% <42,49> ACIN
D29 1 2 H20
ACPRESENT / GPIO31 SLP_SUS#
G16 T71
CH751H-40PT_SOD323-2
R197 2 1 10K_0402_5% PCH_RSMRST#_R 2 R200 1 PCH_GPIO72 E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <6>
10K_0402_5%
+3V_PCH 2 R201 1 RI# A10

RI# SLP_LAN# / GPIO29
K14 PCH_GPIO291 2 +3V_PCH Can be left NC if no use
10K_0402_5% R261 @ integrated LAN.
10K_0402_5%
A A

PCH (3/9) DMI,FDI,PM,
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
+3VS
U4D
1
D R523 R234 D
<33> PCH_ENBKL J47 L_BKLTEN SDVO_TVCLKINN AP43
2.2K_0402_5% 2.2K_0402_5% M45 AP45 +3VS
<33> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
<33> PCH_PWM P45 AM42
2
L_BKLTCTL SDVO_STALLN
SDVO_STALLP AM40
1
EDID_CLK EDID_CLK T40
+3VS <33> EDID_CLK L_DDC_CLK
EDID_DATA EDID_DATA K47 AP39 HDMI@ R202 R203HDMI@
<33> EDID_DATA L_DDC_DATA SDVO_INTN
AP40 2.2K_0402_5% 2.2K_0402_5%
2.2K_0402_5%1 R204 CTRL_CLK SDVO_INTP
2 T45 L_CTRL_CLK
2.2K_0402_5%1 R205 2 CTRL_DATA P39
2
L_CTRL_DATA
2.37K_0402_1%
2 R206 1 LVDS_IBG AF37 P38 HDMICLK_NB HDMICLK_NB <35>
LVD_IBG SDVO_CTRLCLK
AF36 LVD_VBG SDVO_CTRLDATA M39 HDMIDAT_NB HDMIDAT_NB <35>
LVD_VREF AE48 LVD_VREFH
AE47 LVD_VREFL DDPB_AUXN AT49
DDPB_AUXP AT47
DDPB_HPD AT40 TMDS_B_HPD# <35>
<33> LVDS_ACLK# AK39 LVDSA_CLK#
LVDS
<33> LVDS_ACLK AK40 LVDSA_CLK DDPB_0N AV42 TMDS_B_DATA2#_PCHHDMI@ C200 1 2 0.1U_0402_10V6K
HDMI_TX2-_CK <35>
DDPB_0P AV40 TMDS_B_DATA2_PCH HDMI@ C201 1 2 0.1U_0402_10V6K
HDMI_TX2+_CK <35> HDMI D2
<33> LVDS_A0# AN48 LVDSA_DATA#0 DDPB_1N AV45 TMDS_B_DATA1#_PCHHDMI@ C202 1 2 0.1U_0402_10V6K
HDMI_TX1-_CK <35>
<33> LVDS_A1# AM47 LVDSA_DATA#1 DDPB_1P AV46 TMDS_B_DATA1_PCH HDMI@ C203 1 2 0.1U_0402_10V6K
Digital Display Interface

C <33> LVDS_A2# AK47 LVDSA_DATA#2 DDPB_2N AU48 TMDS_B_DATA0#_PCHHDMI@ C204 1 2 0.1U_0402_10V6K
HDMI_TX0-_CK <35> HDMI C
AJ48 LVDSA_DATA#3 DDPB_2P AU47 TMDS_B_DATA0_PCH HDMI@ C205 1 2 0.1U_0402_10V6K
DDPB_3N AV47 TMDS_B_CLK#_PCH HDMI@ C206 1 2 0.1U_0402_10V6K
HDMI_CLK-_CK <35>
<33> LVDS_A0 AN47 LVDSA_DATA0 DDPB_3P AV49 TMDS_B_CLK_PCH HDMI@ C207 1 2 0.1U_0402_10V6K
HDMI_CLK+_CK <35> HDMI CLK
<33> LVDS_A1 AM49 LVDSA_DATA1
<33> LVDS_A2 AK49 LVDSA_DATA2
AJ47 P46 CAP move on Conn, side
LVDSA_DATA3 DDPC_CTRLCLK
DDPC_CTRLDATA P42
AF40 LVDSB_CLK#
AF39 LVDSB_CLK DDPC_AUXN AP47
DDPC_AUXP AP49
AH45 LVDSB_DATA#0 DDPC_HPD AT38
AH47 LVDSB_DATA#1
AF49 LVDSB_DATA#2 DDPC_0N AY47
AF45 LVDSB_DATA#3 DDPC_0P AY49
DDPC_1N AY43
AH43 LVDSB_DATA0 DDPC_1P AY45
AH49 LVDSB_DATA1 DDPC_2N BA47
+3VS AF47 BA48
LVDSB_DATA2 DDPC_2P
AF43 LVDSB_DATA3 DDPC_3N BB47
DAC_BLU BB49
<34> DAC_BLU DDPC_3P
R208 2 1 150_0402_1%
1
DAC_GRN
<34> DAC_GRN
B R559 R524 R209 2 1 150_0402_1% N48 M43 B
2.2K_0402_5% 2.2K_0402_5% DAC_RED CRT_BLUE DDPD_CTRLCLK
<34> DAC_RED P49 CRT_GREEN DDPD_CTRLDATA M36
R210 2 1 150_0402_1% T49 CRT_RED
2
DDPD_AUXN AT45
CRT
CRT_DDC_CLK CRT_DDC_CLK T39 AT43
<34> CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP
CRT_DDC_DATA CRT_DDC_DATA M40 BH41
<34> CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD
DDPD_0N BB43
<34> CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
<34> CRT_VSYNC M49 CRT_VSYNC DDPD_1N BF44
DDPD_1P BE44
DDPD_2N BF42
CRT_IREF T43 BE42
DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
1
DDPD_3P BG42
R211
1K_0402_1% PANTHER-POINT_FCBGA989
2
A A

PCH (4/9) LVDS,CRT,DP,HDMI
B 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
+3VS
U4E
RP2 AY7
PCI_PIRQA# RSVD1
8 1 RSVD2 AV7
7 2 PCI_PIRQD# BG26 AU3
PCI_PIRQC# TP1 RSVD3
6 3 BJ26 TP2 RSVD4 BG4
5 4 PCI_PIRQB# BH25 TP3
BJ16 TP4 RSVD5 AT10
8.2K_0804_8P4R_5% BG16 BC8
RP1 TP5 RSVD6
D AH38 TP6 D
8 1 PCH_GPIO2 AH37 AU2
DGPU_PWR_EN_R TP7 RSVD7
7 2 AK43 TP8 RSVD8 AT4
6 3 PCH_GPIO4 AK45 AT3
ODD_DA#_R TP9 RSVD9
5 4 C18 TP10 RSVD10 AT1
N30 TP11 RSVD11 AY3
8.2K_0804_8P4R_5% H3 AT5
TP12 RSVD12
AH12 TP13 RSVD13 AV3
AM4 TP14 RSVD14 AV1
AM5 TP15 RSVD15 BB1
R213 1 2 8.2K_0402_5% PCH_GPIO5 Y13 BA3
TP16 RSVD16
K24 TP17 RSVD17 BB5
R225 1 2 8.2K_0402_5% PCH_WL_OFF# L24 BB3
TP18 RSVD18
AB46 TP19 RSVD19 BB7
R292 1 @ 2 8.2K_0402_5% PCH_GPIO51 AB45 BE8
TP20 RSVD20
RSVD
R557 1 @ 2 8.2K_0402_5% PCH_GPIO53
PPT EDS DOC#474146 RSVD21 BD4
BF6
RSVD22
R259 1 2 8.2K_0402_5% DGPU_PWR_EN1 B21 AV5
TP21 RSVD23
M20 TP22 RSVD24 AV10
R212 1 2 8.2K_0402_5% DGPU_HOLD_RST#_R AY16 TP23
BG46 TP24 RSVD25 AT8
R214 1 @ 2 8.2K_0402_5% DGPU_HOLD_RST#_R
RSVD26 AY5
RSVD27 BA2
T1829 USB3_RX1_N BE28
T1825 USB3Rn1
BC30 USB3Rn2 RSVD28 AT12
C Boot BIOS Strap bit1 BBS1 <45> USB3_RX3_N USB3_RX3_N BE32 BF3 C
USB3_RX4_N USB3Rn3 RSVD29
<45> USB3_RX4_N BJ32 USB3Rn4
Boot BIOS T1832 USB3_RX1_P BC28
T1826 USB3Rp1
BE30 USB DEBUG=PORT1 AND PORT9
Bit11 Bit10 Destination <45> USB3_RX3_P USB3_RX3_P BF32
USB3Rp2
USB3Rp3
<45> USB3_RX4_P USB3_RX4_P BG32 C24
T1831 USB3_TX1_N USB3Rp4 USBP0N
0 1 Reserved AV26 USB3Tn1 USBP0P A24
GNT1#/ T1827 BB26 C25 USB20_N1
USB3Tn2 USBP1N USB20_N1 <43>
1 0 Reserved USB3_TX3_N AU28 B25 USB20_P1 (CR-B/D USB)
GPIO51 <45> USB3_TX3_N
USB3_TX4_N AY30
USB3Tn3 USBP1P
C26 USB20_N2
USB20_P1 <43>
<45> USB3_TX4_N USB3Tn4 USBP2N USB20_N2 <45>
1 1 SPI (Default) T1830 USB3_TX1_P AU26 A26 USB20_P2 LEFT USB
* T1828 AY26
USB3Tp1
USB3Tp2
USBP2P
USBP3N K28 USB20_N3
USB20_P2
USB20_N3
<45>
<45> (USB 3.0)
0 0 LPC USB3_TX3_P AV28 H28 USB20_P3 LEFT USB
<45> USB3_TX3_P USB3Tp3 USBP3P USB20_P3 <45>
USB3_TX4_P AW30 E28
<45> USB3_TX4_P USB3Tp4 USBP4N
USBP4P D28
C28 USB20_N5
USBP5N USB20_N5 <33>
A28 USB20_P5 USB Camera
USBP5P USB20_P5 <33>
USBP6N C29
DGPU_PWR_EN_R 1 2 NVDD_PWR_EN B29
R319 0_0402_5% PCI_PIRQA# USBP6P
K40 PIRQA# USBP7N N28
@ PCI_PIRQB# K38 M28
PIRQB# USBP7P
PCI
PCI_PIRQC# H38 L30
PCI_PIRQD# PIRQC# USBP8N
G38 PIRQD# USBP8P K30
G30 USB20_N9
R553 1 @ 2 0_0402_5% DGPU_HOLD_RST#_RC46 E30 USB20_P9 RIGHT USB
<23> DGPU_HOLD_RST# REQ1# / GPIO50 USBP9P USB20_P9 <44>
USB
GPIO55 R692 1 @ 2 0_0402_5% DGPU_PWR_EN1 C44 C30 USB20_N10
<54> NVDD_PWR_EN REQ2# / GPIO52 USBP10N USB20_N10 <36>
R691 1 @ 2 0_0402_5% DGPU_PWR_EN_R E40 A30 USB20_P10 WLAN
<23,25> DGPU_PWR_EN REQ3# / GPIO54 USBP10P USB20_P10 <36>
B PCH_WL_OFF# R215 1 @ 2 1K_0402_5% L32 USB20_N11 B
PCH_GPIO51 D47 K32 USB20_P11 CARD READER
GNT1# / GPIO51 USBP11P USB20_P11 <43>
PCH_GPIO53 E42 G32
PCH_WL_OFF# GNT2# / GPIO53 USBP12N
<36> PCH_WL_OFF# F46 GNT3# / GPIO55 USBP12P E32
A16 swap overide Strap/Top-Block C32 USB20_N13
Swap Override jumper A32 USB20_P13 Bluetooth
USBP13P USB20_P13 <40>
PCH_GPIO2 G42
R715 1 @ PIRQE# / GPIO2
Low=A16 swap <40,42> ODD_DA# 2 0_0402_5% ODD_DA#_R G40 PIRQF# / GPIO3
override/Top-Block PCH_GPIO4 C42 C33 USBRBIAS 1 R218 2
PCH_GPIO5 PIRQG# / GPIO4 USBRBIAS# 22.6_0402_1%
PCI_GNT3# Swap Override enabled D44 PIRQH# / GPIO5 USB_OC0# Share with USB_OC4#
High=Default Within 500 mils
* USBRBIAS B33
due to same power switch +3V_PCH
<42> PCI_PME# K10 PME# R02 10K_1206_8P4R_5% RP3
PCH_PLTRST# C6 A14 USB_OC5# 4 5
<6> PCH_PLTRST# PLTRST# OC0# / GPIO59 USB_OC4# <44>
K20 USB_OC1# USB_OC2# 3 6
OC1# / GPIO40 USB_OC1# <45>
B17 USB_OC2# USB_OC7# 2 7
22_0402_5% 1 OC2# / GPIO41
<15> CLK_PCI_LPBACK 2 R219 CLK_PCI_LPBACK_R H49
CLKOUT_PCI0 OC3# / GPIO42 C16 USB_OC3# 1 8
22_0402_5% 1 2 R220 CLK_PCI_EC_R H43 L16 USB_OC4#
<42> CLK_PCI_EC CLKOUT_PCI1 OC4# / GPIO43 USB_OC4# <44>
22_0402_5% 2 @ 1 R173 CLK_PCI_DB_R J48 A16 USB_OC5# 4 5
<36> CLK_PCI_DB CLKOUT_PCI2 OC5# / GPIO9
K42 D14 SMIB SMIB <45> USB_OC1# 3 6
CLKOUT_PCI3 OC6# / GPIO10 USB_OC7# USB_OC4#
H40 CLKOUT_PCI4 OC7# / GPIO14 C14 2 7
1 R222 2 USB_OC3# 1 8
0_0402_5%
PANTHER-POINT_FCBGA989 10K_1206_8P4R_5% RP4
R03
A SMIB 1 R262 2 A
3
1 PCH_PLTRST# 10K_0402_5%
G
A
<23,36,37,42,45> PLT_RST# 4 Y
B 2
P

1
1 U7@
5
MC74VHC1G08DFT2G SC70 5P 2011/06/15 2012/07/11 Title

C208 @
Issued Date Deciphered Date
1U_0402_6.3V4Z
2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/9) PCI, USB
+3VS Size Document Number Rev
2
R223 Custom 0.2

100K_0402_5%
LA-7981P
5 4 3 2 1
5 4 3 2 1
+3VS +3VS +3VS
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
PCH_GPIO69 Function PCH_GPIO70 Function
@ R702
0 HM76 by PCH @ R703 0 14/15" @ R704
1 HM70 by PCH 1 17"
1
PCH_GPIO69 PCH_GPIO70 PCH_GPIO71
PCH_GPIO71
2
10K_0402_5%
R707
R705 R706
@ 200K_0402_5%
0 USB3.0 by PCH 200K_0402_5%
D +3V_PCH 1 USB3.0 by NEC D
1
Weak internal pull-high
1 R235 2 10K_0402_5% EC_SMI#
U4F +3VS
+3VS 1 R233 2 10K_0402_5% T7 C40 PCH_GPIO68 10K_0402_5%1 R224 2

BMBUSY# / GPIO0 TACH4 / GPIO68
1 R227 2 10K_0402_5% PCH_GPIO1 A42 B41 PCH_GPIO69
GPIO28 TACH1 / GPIO1 TACH5 / GPIO69
On-Die PLL Voltage Regulator 1 R228 2 10K_0402_5% PCH_GPIO6 H36 C41 PCH_GPIO70 +3VS
+3VS TACH2 / GPIO6 TACH6 / GPIO70
This signal has a weak internal pull up
EC_SCI# E38 A40 PCH_GPIO71
<42> EC_SCI# TACH3 / GPIO7 TACH7 / GPIO71
2
H：On-Die voltage regulator enable
* L：On-Die PLL Voltage Regulator disable <42> EC_SMI# EC_SMI# C10 GPIO8
R236
10K_0402_5%
R240 1 @ 2 1K_0402_5% PCH_GPIO28 +3V_PCH 1 R229@ 2 10K_0402_5% PCH_GPIO12 C4 LAN_PHY_PW R_CTRL / GPIO12
1
R02 1 R230 2 1K_0402_5% EC_LID_OUT# G2 P4 +3VS
GPIO15 A20GATE GATEA20 <42>
<42> EC_LID_OUT#
AU16 PCH_PECI_R 1 @ 2
PECI H_PECI <6,42>
+3VS 1 R231 2 10K_0402_5% PCH_GPIO16 U2 0_0402_5% R237
SATA4GP / GPIO16 KBRST# KBRST# R226
P5 1 2 10K_0402_5%
* PCH_GPIO27 (Have internal Pull-High) <46,54> DGPU_PWROK
R297 1 2 0_0402_5%
RCIN# KBRST# <42>
GPIO
+3VS 1 R232@ 2 10K_0402_1% DGPU_PWROK_R D40 AY11
High: VCCVRM VR Enable TACH0 / GPIO17 PROCPW RGD H_CPUPWRGD <6>
CPU/MISC
PU on power side
Low: VCCVRM VR Disable +3VS 1 R238 2 10K_0402_5% BT_DISABLE T5 AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP# H_THRMTRIP# <6>
C
SCLOCK / GPIO22 THRMTRIP# R239 390_0402_5% C
PCH_GPIO27 <36> BT_DISABLE ODD_EN
R245 1 @ 2 10K_0402_5% E8 T14
R02 +3V_PCH <40> ODD_EN GPIO24 INIT3_3V#
PCH_GPIO27 PCH_THRMTRIP#_R <23>
E16 GPIO27 DF_TVS AY1
R241 INIT3_3V
1 2 10K_0402_5% PCH_GPIO28 P8 This signal has weak internal PU,can't pull low
GPIO28
<36,40> PCH_BT_ON# TS_VSS1 AH8
1 R242 2 10K_0402_5% PCH_BT_ON# K1
+3VS STP_PCI# / GPIO34 +1.8VS
TS_VSS2 AK11
+3VS 1 R243 2 10K_0402_5% PCH_GPIO35 K4
+3VS GPIO35
TS_VSS3 AH10 DMI Termination Voltage
PCH_GPIO36 V8 SATA2GP / GPIO36
1
1
TS_VSS4 AK10 Set to Vcc when HIGH
R244 @ R250 @ PCH_GPIO37 M5 NV_CLE
SATA3GP / GPIO37
10K_0402_5% 10K_0402_5% Set to Vss when LOW R216
PCH_GPIO38 N2 P37 2.2K_0402_5%
SLOAD / GPIO38 NC_1
2
2
PCH_GPIO37 PCH_GPIO36 R247 1 2 10K_0402_5% PCH_GPIO39 M3 NV_CLE 2 1
+3VS SDATAOUT0 / GPIO39 H_SNB_IVB# <6>
R217 1K_0402_5%
1
R248 1 2 10K_0402_5% PCH_GPIO48 V13 BG2 Weak internal CLOSE TO THE BRANCHING POINT
SDATAOUT1 / GPIO48 VSS_NCTF_15
1
PU,Do not pull low

R881 +3VS R249 1 2 10K_0402_5% PCH_GPIO49 V3 BG48
10K_0402_5% R547 SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
10K_0402_5% R251 1 2 10K_0402_5% PCH_GPIO57 D6 BH3
+3V_PCH
2
GPIO57 VSS_NCTF_17
2
VSS_NCTF_18 BH47
A4 VSS_NCTF_1 VSS_NCTF_19 BJ4
B
A44 VSS_NCTF_2 VSS_NCTF_20 BJ44 B
NCTF
BIOS Request SKU ID
+3VS A6 BJ6
VSS_NCTF_6 VSS_NCTF_24
B3 VSS_NCTF_7 VSS_NCTF_25 C2
B47 VSS_NCTF_8 VSS_NCTF_26 C48

2
1
10K_0402_5%
10K_0402_5%
BD1 VSS_NCTF_9 VSS_NCTF_27 D1
BD49 VSS_NCTF_10 VSS_NCTF_28 D49

R711 R246
@ @ BE1 E1
1
PCH_GPIO38 BE49 E49
PCH_GPIO67 BF1 F1
PCH_GPIO67 <15> VSS_NCTF_13 VSS_NCTF_31
BF49 VSS_NCTF_14 VSS_NCTF_32 F49
2
1
10K_0402_5%
10K_0402_5%
R708 R298 PANTHER-POINT_FCBGA989
PCH_GPIO38 PCH_GPIO67 Function

1
A A
0 0 Optimus
0 1 Reserved Security Classification Compal Secret Data
1 0 DIS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO, CPU, MISC
Custom 0.2
1 1 UMA DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-7981P
5 4 3 2 1
Compal Electronics, Inc.

5 4 3 2 1
L1 Change to 1 ohm P/N

S RES 1/10W 1 +-1% 0603
+1.05VS U4G POWER 10U
+3VS PCH Power Rail Table
@ J2 1300mA L1 1_0603_1% Refer to CPU EDS R1.5
2 1 +1.05VS_VCCCORE AA23 U48 +VCCADAC 2 1
VCCCORE[1] 1mA VCCADAC
AC23 VCCCORE[2] 1 1 1 1 S0 Iccmax
1U_0402_6.3V6K
C210
1U_0402_6.3V6K
C211
1U_0402_6.3V6K
C212
1 1 1 1 AD21 C395@ Voltage Rail Voltage Current (A)
CRT
VCCCORE[3]
10U_0603_6.3V6M
C209
PAD-OPEN 4x4m AD23 U47 C213 C214 C215 10U_0603_6.3V6M
VCCCORE[4] VSSADAC 0.01U_0402_25V7K 0.1U_0402_10V7K 10U_0603_6.3V6M
AF21
VCC CORE
VCCCORE[5] 2 2 2 2
AF23
VCCCORE[6]
V_PROC_IO 1.05 0.001
D 2 2 2 2 AG21 +3VS D
VCCCORE[7]
AG23
VCCCORE[8] +VCCA_LVDS R295 2
AG24
VCCCORE[9] 1mA VCCALVDS AK36 1 V5REF 5 0.001
AG26
VCCCORE[10] 0_0603_5%
AG27 AK37
VCCCORE[11] VSSALVDS
AG29
VCCCORE[12]
V5REF_Sus 5 0.001
AJ23 +1.8VS
VCCCORE[13]
LVDS
AJ26 AM37 L2
VCCCORE[14] VCCTX_LVDS[1] 0.1UH_MLF1608DR10KT_10%_1608
AJ27
VCCCORE[15]
Vcc3_3 3.3 0.228
AJ29 AM38 +VCCTX_LVDS 2 1
VCCCORE[16] VCCTX_LVDS[2] 0.1uH inductor, 200mA
AJ31 1 1 1
+1.05VS VCCCORE[17]
60mA VCCTX_LVDS[3] AP36 VccADAC 3.3 0.001
C216 C217 C218
AP37 0.01U_0402_25V7K 0.01U_0402_25V7K 22U_0805_6.3V6M
R254 2 +1.05VS_VCCDPLLEXPAN19 VCCTX_LVDS[4] 2 2 2
1 0_0603_5% VCCIO[28]
VccADPLLA 1.05 0.075
T47 +VCCAPLLEXP BJ22 +3VS VccADPLLB 1.05 0.075

VCCAPLLEXP R256
This pin can be left as no connect in V33 +3VS_VCC3_3_6 2 1
VCC3_3[6]
HVCMOS
AN16 VCCIO[15]
VccCore 1.05 1.3
On-Die VR enabled mode (default). 1 0_0603_5%
AN17 VCCIO[16]
V34 C219 VccDMI 1.05 0.042
VCC3_3[7]
0.1U_0402_10V7K
2
AN21 VCCIO[17]
VccIO 1.05 3.709
AN26 VCCIO[18]
AN27 3711mA AT16 +VCCAFDI_VRM VccASW 1.05 0.903
VCCIO[19] VCCVRM[3]
+1.05VS 10U AP21 +VCCP_VCCDMI +V1.05S_VCCP
C VCCIO[20] R258 C
VccSPI 3.3 0.01
+1.05VS_VCC_EXP AP23 AT20 +VCCP_VCCDMI 2 1
VCCIO[21] VCCDMI[1]
1
+1.05VS
1U_0402_6.3V6K
C222
1U_0402_6.3V6K
C223
1U_0402_6.3V6K
C224
1U_0402_6.3V6K
C225
DMI
1 1 1 1 1 AP24 0_0603_5% VccDSW 3.3 0.001
VCCIO[22]
10U_0603_6.3V6M
C221
VCCIO
R294 C220
AP26 VCCIO[23] 20mA VCCCLKDMI AB36 +1.05VS_VCC_DMI_CCI 2 1 1U_0402_6.3V6K
2 VccDFTERM 1.8 0.002
2 2 2 2 2 1
AT24 0_0603_5%
VCCIO[24] C226
1U_0402_6.3V6K VccRTC 3.3 6 uA
AN33 2
VCCIO[25]
AN34
VCCIO[26] VCCDFTERM[1]
AG16 VccSus3_3 3.3 0.065
+3VS
R260 2 1 +3VS_VCCA3GBG BH29 AG17 +VCCPNAND +1.8VS VccSusHDA 3.3 / 1.5 0.01
VCC3_3[3] 190mAVCCDFTERM[2]
DFT / SPI
1
0_0603_5% C227 R293
0.1U_0402_10V7K AJ16 2 1 VccVRM 1.8 / 1.5 0.167
VCCDFTERM[3]
2 +VCCAFDI_VRM AP16 0_0603_5%
VCCVRM[2] 1
AJ17 C228 VccCLKDMI 1.05 0.075
VCCDFTERM[4] 0.1U_0402_10V7K
This pin can be left as no connect in
T50 +1.05VS_VCCAPLL_FDI BG6
On-Die VR enabled mode (default). VccAFDIPLL 2 +3VS VccSSC 1.05 0.095
R263
2 1 +1.05VS_VCCDPLL_FDI AP17 R399
+1.05VS VCCIO[27]
V1 +3V_VCCPSPI 1 2 VccDIFFCLKN 1.05 0.055
FDI
0_0603_5% 20mA VCCSPI

+VCCP_VCCDMI AU20 1 0_0402_5%
VCCDMI[2]
VccALVDS 3.3 0.001
C230
B PANTHER-POINT_FCBGA989 1U_0402_6.3V6K B
2 VccTX_LVDS 1.8 0.04
+VCCAFDI_VRM
+1.5VS
2 1 +VCCAFDI_VRM
R265 0_0603_5%
Intel recommand VCCVRM==>1.5V FOR MOBILE

stuff R265 and unstuff R266 VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec
A A

PCH (7/9) PWR
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
Have internal VRM

+3VS +1.05VS R268 @
0_0603_5%
2 1 +VCCACLK
10U
R303
2 1+3VS_VCC_CLKF33 +3V_PCH
1 1 R269 U4J POWER +1.05VS +5VALW +5VALW_PCH
10U_0603_6.3V6M
C231
1U_0402_6.3V6K
C232
0_0603_5% 2 1 +VCCPDSW R270
1 AD49 N26 +1.05VS_VCCUSBCORE 2 1
0_0603_5% VCCACLK VCCIO[29] R289
2 2 1
C234 P26 0_0603_5% 2 1
0.1U_0402_10V7K VCCIO[30] C233
T16 3mA
D 2 VCCDSW3_3 1U_0402_6.3V6K 0_0603_5% D
P28
VCCIO[31] 2
2 1 +PCH_VCCDSW V12 T27
DCPSUSBYP VCCIO[32]
C235 @ T29
+3VS_VCC_CLKF33 VCCIO[33] +3V_PCH
On-Die PLL Voltage Regulator 0.1U_0402_10V7K T38
VCC3_3[5]
H：On-Die PLL voltage regulator enable T101
R272
T23 +3V_VCCPUSB 2 1
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 +VCCAPLL_CPY_PCH BH23
119mA VCCSUS3_3[7]
VCCAPLLDMI2 +3V_PCH +5VALW_PCH
0.1U_0402_10V7K
C236
R271 T24 1 0_0603_5%
,VCCAPLLSATA 2 1 +VCCDPLL_CPY AL29
VCCSUS3_3[8] R273 +3V_PCH
+1.05VS VCCIO[14]
V23 +3V_VCCAUBG2 1
VCCSUS3_3[9]
USB
0_0603_5% 1
2
+VCCSUS1 2 0_0603_5%
AL24 DCPSUS[3] VCCSUS3_3[10] V24
1 C238 R275 D1
P24 0.1U_0402_10V7K 10_0402_5% CH751H-40PT_SOD323-2
@ C239 VCCSUS3_3[6] 2 +1.05VS
1U_0402_6.3V6K AA19 R276
1
2 VCCASW[1] +1.05VS_VCCAUPLL +PCH_V5REF_SUS
VCCIO[34] T26 2 1
+1.05VS AA21 1010mA
R277 VCCASW[2] 1
0_0603_5%
1 2 +1.05VM_VCCASW AA24 M26 +PCH_V5REF_SUS C240
VCCASW[3] 1mA V5REF_SUS 0.1U_0603_25V7K
1 1 2
22U_0805_6.3V6M
C241
22U_0805_6.3V6M
C242
AA26
Clock and Miscellaneous

0_0805_5% VCCASW[4] +VCCA_USBSUS C243 @1
AN23 2 1U_0402_6.3V6K
DCPSUS[4]
AA27 VCCASW[5]
2 2 AN24 +3V_VCCPSUS C316 @1
@ 2 0.1U_0402_10V7K
VCCSUS3_3[1]
AA29 VCCASW[6]
AA31 +5VS +3VS
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN +3V_PCH
VCCASW[8] 1mA V5REF
2
C R278 C
1 1 1
1U_0402_6.3V6K
C244
1U_0402_6.3V6K
C245
1U_0402_6.3V6K
C246
AC27 2 1 R279 D2
VCCASW[9] +3V_VCCPSUS CH751H-40PT_SOD323-2
VCCSUS3_3[2] N20 1 10_0402_5%
+1.05VS 0_0603_5%
PCI/GPIO/LPC
AC29 VCCASW[10]
2 2 2 N22 C247
1
@ VCCSUS3_3[3] 1U_0402_6.3V +PCH_V5REF_RUN
AC31 VCCASW[11]
L5 2 +3VS
VCCSUS3_3[4] P20 1
1 2 +1.05VS_VCCA_A_DPL AD29 R281
VCCASW[12] C248
P22 2 1
VCCSUS3_3[5]
1
10UH_LB2012T100MR_20% AD31 1 1U_0603_10V6K

R300 VCCASW[13] C249 0_0603_5% 2
0_0603_5% W21 AA16 +3VS_VCCPCORE 0.1U_0402_10V7K
VCCASW[14] VCC3_3[1]
L6 W23 W16 2 +3VS
2
+1.05VS_VCCA_B_DPL VCCASW[15] VCC3_3[8] R282

1 2
10UH_LB2012T100MR_20% W24 T34 +3VS_VCCPPCI 2 1
VCCASW[16] VCC3_3[4]
1 1 1
220U_B2_2.5VM_R35
C250
22U_0805_6.3V6M
C186
1U_0402_6.3V6K
C251
220U_B2_2.5VM_R35
C252
22U_0805_6.3V6M
C187
1U_0402_6.3V6K
C253
1 1 1 1 W26 0_0603_5%
+ + VCCASW[17] C254
@ @ W29 +3VS 0.1U_0402_10V7K
VCCASW[18] R283 2
2 2 2 2 2 2 W31 AJ2 +VCC3_3_2 2 1
VCCASW[19] VCC3_3[2] +1.05VS_SATA3 +1.05VS
1
W33 0_0603_5% R285
VCCASW[20]
AF13 2 1
VCCIO[5] C255
2 0.1U_0402_10V7K 1
+VCCRTCEXT N16 0_0603_5%
DCPRTC C257
1 AH13
C258 VCCIO[12] 1U_0402_6.3V6K
0.1U_0402_10V7K +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3 2
VCCVRM[4] VCCIO[13]
2
B R274 B
AF14
+1.05VS_VCCA_A_DPL VCCIO[6]
+1.05VS 2 1 BD47
VCCADPLLA 80mA
SATA
AK1 +VCCSATAPLL T100
+1.05VS_VCCA_B_DPL VCCAPLLSATA
0_0603_5% 1 BF47
VCCADPLLB 80mA
+VCCAFDI_VRM On-Die PLL Voltage Regulator
C256 H：On-Die PLL voltage regulator enable
1U_0402_6.3V6K AF11 +VCCAFDI_VRM
+1.05VS_VCCDIFFCLKN +VCCDIFFCLK VCCVRM[1] +1.05VS_VCC_SATA +1.05VS
2
AF17
VCCIO[7] VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
AF33 R288
R280 AF34
VCCDIFFCLKN[1]
55mA AC16 +1.05VS_VCC_SATA 2 1 ,VCCAPLLSATA
+1.05VS_VCCDIFFCLKN VCCDIFFCLKN[2] VCCIO[2]
+1.05VS 2 1 AG34
VCCDIFFCLKN[3]
1 VCCIO[3]
AC17 1 0_0603_5%
0_0603_5% C261
C259 +1.05VS_SSCVCC AG33 AD17 1U_0402_6.3V6K
1U_0402_6.3V6K VCCSSC 95mA VCCIO[4]
2 2
+VCCSST V16 +1.05VS
R284 DCPSST
1
+1.05VS 2 1 C263
1 0.1U_0402_10V7K +1.05VM_VCCSUS T17 T21
0_0603_5% DCPSUS[1] VCCASW[22]
V19
C262 2 DCPSUS[2]
MISC
1U_0402_6.3V6K +V1.05S_VCCP V21

2 R286 VCCASW[23]
CPU
@ R290 2 1 +V_CPU_IO BJ8

0_0603_5% V_PROC_IO 1mA
T19
+1.05VM_VCCSUS 0_0603_5% VCCASW[21]
+1.05VS 2 1 1 1 1
+RTCVCC +3V_PCH
4.7U_0603_6.3V6K
C265
0.1U_0402_10V7K
C266
0.1U_0402_10V7K
C267
1 R287
A22 P32 +VCCSUSHDA 2 1
RTC
2 2 2 VCCRTC 10mA VCCSUSHDA

HDA
C264 @ @
1U_0402_6.3V6K
C268
0.1U_0402_10V7K
C269
0.1U_0402_10V7K
C270
1U_0402_6.3V6K 1 1 1 1 0_0603_5%
2 PANTHER-POINT_FCBGA989 C271
A 0.1U_0402_16V4Z A
@
2 2 2 2

2011/06/15 2012/07/11 Title
Issued Date Deciphered Date PCH (8/9) PWR
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
U4I
AY4 VSS[159] VSS[259] H46

AY42 VSS[160] VSS[260] K18
AY46 K26
VSS[161] VSS[261]
AY8 K39
VSS[162] VSS[262]
B11 K46
D U4H VSS[163] VSS[263] D
B15 K7
VSS[164] VSS[264]
H5 B19 L18
VSS[0] VSS[165] VSS[265]
B23 L2
VSS[166] VSS[266]
AA17 AK38 B27 L20
VSS[1] VSS[80] VSS[167] VSS[267]
AA2 AK4 B31 L26
VSS[2] VSS[81] VSS[168] VSS[268]
AA3 AK42 B35 L28
VSS[3] VSS[82] VSS[169] VSS[269]
AA33 AK46 B39 L36
VSS[4] VSS[83] VSS[170] VSS[270]
AA34 AK8 B7 L48
VSS[5] VSS[84] VSS[171] VSS[271]
AB11 AL16 F45 M12
VSS[6] VSS[85] VSS[172] VSS[272]
AB14 AL17 BB12 P16
VSS[7] VSS[86] VSS[173] VSS[273]
AB39 AL19 BB16 M18
VSS[8] VSS[87] VSS[174] VSS[274]
AB4 VSS[9] VSS[88] AL2 BB20 VSS[175] VSS[275] M22
AC19 VSS[13] VSS[92] AL27 BB30 VSS[179] VSS[279] M34
AC33 VSS[17] VSS[96] AL48 BC14 VSS[183] VSS[283] M46
AC34 VSS[18] VSS[97] AM11 BC18 VSS[184] VSS[284] M8
AC48 VSS[19] VSS[98] AM14 BC2 VSS[185] VSS[285] N18
AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
AD19 VSS[24] VSS[103] AM46 BC36 VSS[190] VSS[290] T33
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 VSS[27] VSS[106] AN29 BC48 VSS[193] VSS[293] P47
AD33 VSS[28] VSS[107] AN3 BD46 VSS[194] VSS[294] P7
AD34 VSS[29] VSS[108] AN31 BD5 VSS[195] VSS[295] R2
C C
AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
AD37 VSS[31] VSS[110] AP19 BE26 VSS[197] VSS[297] T12
AD38 VSS[32] VSS[111] AP28 BE40 VSS[198] VSS[298] T31
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD40 VSS[35] VSS[114] AP38 BF16 VSS[201] VSS[301] W34
AD43 AP42 BF22 T47
VSS[37] VSS[116] VSS[203] VSS[303]
AD45 AP46 BF24 T8
VSS[38] VSS[117] VSS[204] VSS[304]
AD46 AP8 BF26 V11
VSS[39] VSS[118] VSS[205] VSS[305]
AD8 AR2 BF28 V17
VSS[40] VSS[119] VSS[206] VSS[306]
AE2 AR48 BD3 V26
VSS[41] VSS[120] VSS[207] VSS[307]
AE3 AT11 BF30 V27
VSS[42] VSS[121] VSS[208] VSS[308]
AF10 AT13 BF38 V29
VSS[43] VSS[122] VSS[209] VSS[309]
AF12 AT18 BF40 V31
VSS[44] VSS[123] VSS[210] VSS[310]
AD14 AT22 BF8 V36
VSS[45] VSS[124] VSS[211] VSS[311]
AD16 AT26 BG17 V39
VSS[46] VSS[125] VSS[212] VSS[312]
AF16 AT28 BG21 V43
VSS[47] VSS[126] VSS[213] VSS[313]
AF19 AT30 BG33 V7
VSS[48] VSS[127] VSS[214] VSS[314]
AF24 AT32 BG44 W17
VSS[49] VSS[128] VSS[215] VSS[315]
AF26 AT34 BG8 W19
VSS[50] VSS[129] VSS[216] VSS[316]
AF27 AT39 BH11 W2
VSS[51] VSS[130] VSS[217] VSS[317]
AF29 AT42 BH15 W27
VSS[52] VSS[131] VSS[218] VSS[318]
AF31 AT46 BH17 W48
VSS[53] VSS[132] VSS[219] VSS[319]
AF38 AT7 BH19 Y12
VSS[54] VSS[133] VSS[220] VSS[320]
AF4 AU24 H10 Y38
VSS[55] VSS[134] VSS[221] VSS[321]
AF42 AU30 BH27 Y4
VSS[56] VSS[135] VSS[222] VSS[322]
AF46 AV16 BH31 Y42
VSS[57] VSS[136] VSS[223] VSS[323]
AF5 AV20 BH33 Y46
VSS[58] VSS[137] VSS[224] VSS[324]
AF7 AV24 BH35 Y8
VSS[59] VSS[138] VSS[225] VSS[325]
AF8 AV30 BH39 BG29
VSS[60] VSS[139] VSS[226] VSS[328]
AG19 AV38 BH43 N24
B VSS[61] VSS[140] VSS[227] VSS[329] B
AG2 AV4 BH7 AJ3
VSS[62] VSS[141] VSS[228] VSS[330]
AG31 AV43 D3 AD47
VSS[63] VSS[142] VSS[229] VSS[331]
AG48 AV8 D12 B43
VSS[64] VSS[143] VSS[230] VSS[333]
AH11 AW14 D16 BE10
VSS[65] VSS[144] VSS[231] VSS[334]
AH3 AW18 D18 BG41
VSS[66] VSS[145] VSS[232] VSS[335]
AH36 AW2 D22 G14
VSS[67] VSS[146] VSS[233] VSS[337]
AH39 AW22 D24 H16
VSS[68] VSS[147] VSS[234] VSS[338]
AH40 AW26 D26 T36
VSS[69] VSS[148] VSS[235] VSS[340]
AH42 AW28 D30 BG22
VSS[70] VSS[149] VSS[236] VSS[342]
AH46 AW32 D32 BG24
VSS[71] VSS[150] VSS[237] VSS[343]
AH7 AW34 D34 C22
VSS[72] VSS[151] VSS[238] VSS[344]
AJ19 AW36 D38 AP13
VSS[73] VSS[152] VSS[239] VSS[345]
AJ21 AW40 D42 M14
VSS[74] VSS[153] VSS[240] VSS[346]
AJ24 AW48 D8 AP3
VSS[75] VSS[154] VSS[241] VSS[347]
AJ33 AV11 E18 AP1
VSS[76] VSS[155] VSS[242] VSS[348]
AJ34 AY12 E26 BE16
VSS[77] VSS[156] VSS[243] VSS[349]
AK12 AY22 G18 BC16
VSS[78] VSS[157] VSS[244] VSS[350]
AK3 AY28 G20 BG28
VSS[79] VSS[158] VSS[245] VSS[351]
G26 BJ28
PANTHER-POINT_FCBGA989 VSS[246] VSS[352]
G28
VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]
A A

PCH (9/9) VSS
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
+3VS_VGA
U65A N13P@
PCH_THRMTRIP#_R <19>
1
PCIE_CTX_GRX_N[0..15]
<5> PCIE_CTX_GRX_N[0..15]
PCIE_CTX_GRX_P0 AN12 Part 1 of 7
3
PCIE_CTX_GRX_P[0..15] PCIE_CTX_GRX_N0 PEX_RX0 GPU_VID4 RV208
<5> PCIE_CTX_GRX_P[0..15] AM12 P6 GPU_VID4 <54>
PCIE_CTX_GRX_P1 PEX_RX0_N GPIO0 GPU_VID3 R03 10K_0402_5% QV7B
AN14 M3 GPU_VID3 <54>
PCIE_CRX_GTX_N[0..15] PCIE_CTX_GRX_N1 PEX_RX1 GPIO1
<5> PCIE_CRX_GTX_N[0..15] AM14 L6 DMN66D0LDW-7 2N_SOT363-6
2
PCIE_CTX_GRX_P2 PEX_RX1_N GPIO2 VGA_GPIO3 0_0402_5% 1 @ DPRSLPVR_VGA
AP14 P5 2 5
PCIE_CRX_GTX_P[0..15] PCIE_CTX_GRX_N2 PEX_RX2 GPIO3 RV113
<5> PCIE_CRX_GTX_P[0..15] AP15 P7
6
PCIE_CTX_GRX_P3 PEX_RX2_N GPIO4 GPU_VID1 QV7A
AN15 L7 GPU_VID1 <54>
4
D PCIE_CTX_GRX_N3 PEX_RX3 GPIO5 GPU_VID2 DMN66D0LDW-7 2N_SOT363-6 D
AM15 M7 GPU_VID2 <54>
PCIE_CTX_GRX_P4 PEX_RX3_N GPIO6
AN17 N8
PCIE_CTX_GRX_N4 PEX_RX4 GPIO7 OVERT#
AM17 M1 2
PCIE_CTX_GRX_P5 PEX_RX4_N GPIO8 GC6_EVENT#_R
AP17 M2
PCIE_CTX_GRX_N5 PEX_RX5 GPIO9
AP18 L1
1
PCIE_CTX_GRX_P6 PEX_RX5_N GPIO10 GPU_VID0
AN18 M5
GPIO
PEX_RX6 GPIO11 GPU_VID0 <54>
PCIE_CTX_GRX_N6 AM18 N3 VGA_GPIO12 2 1
PEX_RX6_N GPIO12 VGA_AC_DET <42,54>
PCIE_CTX_GRX_P7 AN20 M4 GPU_VID5 DV3
PEX_RX7 GPIO13 GPU_VID5 <54>
PCIE_CTX_GRX_N7 AM20 N4 CH751H-40PT_SOD323-2
PEX_RX7_N GPIO14 VGA_GPIO15 100K_0402_5% 1 @
PCIE_CTX_GRX_P8 AP20 P2 2 RV17
PCIE_CTX_GRX_N8 PEX_RX8 GPIO15 VGA_GPIO16 0_0402_5% 1 @
AP21 R8 2 RV114 DPRSLPVR_VGA
DPRSLPVR_VGA <54>
AN21 M6
PCIE_CTX_GRX_N9 PEX_RX9 GPIO17 R03
AM21 R1
AN23 P3
PCIE_CTX_GRX_N10 PEX_RX10 GPIO19
AM23 P4
AP23 P1
PCIE_CTX_GRX_N11 PEX_RX11 GPIO21 if GC6 is supported, stuff the BOM option to
AP24
PCIE_CTX_GRX_P12 PEX_RX11_N pull high to 3.3vs system power, if not, stuff
AN24
PCIE_CTX_GRX_N12 PEX_RX12 the BOM option to pull high to NV3V3;
AM24
+3VS_VGA PCIE_CTX_GRX_P13 PEX_RX12_N
AN26
PCIE_CTX_GRX_N13 PEX_RX13
AM26
+3VS_VGA PCIE_CTX_GRX_P14 PEX_RX13_N +3VS_VGA
AP26
PCIE_CTX_GRX_N14 PEX_RX14
AP27
2
PCIE_CTX_GRX_P15 PEX_RX14_N
AN27 AK9
RV24 RV25 PCIE_CTX_GRX_N15 PEX_RX15 DACA_RED GC6_EVENT#_R
AM27 AL10 1 2
2.2K_0402_5% 2.2K_0402_5% PEX_RX15_N DACA_GREEN RV49 10K_0402_5%
AL9
DACA_BLUE VGA_EDID_CLK 1 2
DACs
5
PCIE_CRX_GTX_P0 CV6 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P0 AK14 RV3 2.2K_0402_5%

1
QV1B CV7 PEX_TX0

PCIE_CRX_GTX_N0 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N0 AJ14 AM9 VGA_EDID_DATA 1 2
CV8 PEX_TX0_N DACA_HSYNC
VGA_SMB_CK2 4 3 EC_SMB_CK2 <15,39,42>
PCIE_CRX_GTX_P1 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P1 AH14 AN9 RV4 2.2K_0402_5%
PCIE_CRX_GTX_N1 CV9 PEX_TX1 DACA_VSYNC
1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N1 AG14 VGA_CRT_DATA 1 2
2N7002DW-T/R7_SOT363-6 CV10 PEX_TX1_N
PCIE_CRX_GTX_P2 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P2 AK15 10K_0402_5% RV10 2.2K_0402_5%
C PCIE_CRX_GTX_N2 CV11 PEX_TX2 C
1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N2 AJ15 AG10 +DACA_VDD 2 RV107 1 VGA_CRT_CLK 1 2
PEX_TX2_N DACA_VDD
PCI EXPRESS
PCIE_CRX_GTX_P3 CV12 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P3 AL16 AP9 RV11 2.2K_0402_5%
CV13 PEX_TX3 DACA_VREF
PCIE_CRX_GTX_N3 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N3 AK16 AP8 I2CB_SCL 1 2
PCIE_CRX_GTX_P4 CV15 PEX_TX3_N DACA_RSET
1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P4 AK17 RV12 2.2K_0402_5%
2
CV17 PEX_TX4
PCIE_CRX_GTX_N4 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N4 AJ17 I2CB_SDA 1 2
QV1A PCIE_CRX_GTX_P5 CV19 PEX_TX4_N
1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P5 AH17 RV13 2.2K_0402_5%
CV14 PEX_TX5
VGA_SMB_DA2 1 6 EC_SMB_DA2 <15,39,42>
PCIE_CRX_GTX_N5 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N5 AG17 OVERT# 1 2
CV16 PEX_TX5_N
PCIE_CRX_GTX_P6 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P6 AK18 RV1 10K_0402_5%
2N7002DW-T/R7_SOT363-6 PCIE_CRX_GTX_N6 CV18 PEX_TX6
1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N6 AJ18 VGA_GPIO12 1 2
CV20 PEX_TX6_N
PCIE_CRX_GTX_P7 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P7 AL19 RV2 10K_0402_5%
PCIE_CRX_GTX_N7 CV22 PEX_TX7
1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N7 AK19 R4 VGA_CRT_CLK
CV24 PEX_TX7_N I2CA_SCL
PCIE_CRX_GTX_P8 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P8 AK20 R5 VGA_CRT_DATA
CV26 N13P@ PEX_TX8 I2CA_SDA
PCIE_CRX_GTX_N8 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N8 AJ20
PCIE_CRX_GTX_P9 CV21 N13P@ PEX_TX8_N
1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P9 AH20 R7 I2CB_SCL
CV23 N13P@ PEX_TX9 I2CB_SCL
PCIE_CRX_GTX_N9 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N9 AG20 R6 I2CB_SDA
PCIE_CRX_GTX_P10 CV25 N13P@ PEX_TX9_N I2CB_SDA
1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P10 AK21
I2C
CV27 N13P@ PEX_TX10
PCIE_CRX_GTX_N10 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N10 AJ21 R2 VGA_EDID_CLK
CV29 N13P@ PEX_TX10_N I2CC_SCL
PCIE_CRX_GTX_P11 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P11 AL22 R3 VGA_EDID_DATA
PCIE_CRX_GTX_N11 CV31 N13P@ PEX_TX11 I2CC_SDA
1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N11 AK22
CV33 N13P@ PEX_TX11_N
PCIE_CRX_GTX_P12 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P12 AK23 T4 VGA_SMB_CK2
PCIE_CRX_GTX_N12 CV28 N13P@ PEX_TX12 I2CS_SCL
1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N12 AJ23 T3 VGA_SMB_DA2
CV30 N13P@ PEX_TX12_N I2CS_SDA +1.05VS_VGA
PCIE_CRX_GTX_P13 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P13 AH23
CV32 N13P@ PEX_TX13
PCIE_CRX_GTX_N13 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N13 AG23
1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P14 AK24 30 ohms @100MHz (ESR=0.05)
CV41 N13P@ PEX_TX14
PCIE_CRX_GTX_N14 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N14 AJ24
1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P15 AL25 60mA LV7
CV35 N13P@ PEX_TX15
PCIE_CRX_GTX_N15 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N15 AK25 +PLLVDD 1 2
+3VS_VGA +3VS_VGA N13P@ PEX_TX15_N FBMA-10-100505-300T 0402
22U_0805_6.3V6M
0.1U_0402_10V7K
CV131
AD8 RV112 1 @ 2 1 1
PLLVDD
CV40
AJ11 45mA 0_0402_5%
PEX_WAKE_N
AE8
CLK_PCIE_VGA SP_PLLVDD
<15> CLK_PCIE_VGA AL13 45mA Near GPU
2
B @ CLK_PCIE_VGA# PEX_REFCLK +SP_PLLVDD 2 2 B

<15> CLK_PCIE_VGA# AK13 AD7
RV105 CLK_REQ_GPU# PEX_REFCLK_N VID_PLLVDD
CLK
AK12
10K_0402_5% PEX_CLKREQ_N
Differential signal 1 @ 2 PEX_TSTCLK_OUT AJ26 H3 XTALIN
5
RV20 200_0402_1% PEX_TSTCLK_OUT# PEX_TSTCLK_OUT XTAL_IN XTAL_OUT

AK26 H2
1
PEX_TSTCLK_OUT_N XTAL_OUT
2 Under GPU
P
<18,36,37,42,45> PLT_RST# B
4 PLT_RST_VGA# AJ12 J4 XTALOUT
Y PEX_TERMP PEX_RST_N XTAL_OUTBUFF XTALSSIN
<18> DGPU_HOLD_RST# 1 AP29 H1
G
A PEX_TERMP XTAL_SSIN
1
1
3
UV2 RV18 RV26 RV27

2
MC74VHC1G08DFT2G SC70 5P 100K_0402_5% 10K_0402_5% 10K_0402_5%

RV22
2.49K_0402_1% N13P-GL-A1 MP
2
2
1
N13M@ Under GPU(below 150mils)

U65 1 2 150mA
RV29 10K_0402_5% RV23 10M_0402_5%
2 1 +1.05VS_VGA 1 2 +SP_PLLVDD
<18,25> DGPU_PWR_EN
LV1
22U_0805_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0402_6.3V6M
+3VS_VGA
CV112
CV113
CV4
CV5
YV1 BLM18PG330SN1D_0603 1 1 1 1
1 4 3 XTAL_OUT 180ohms (ESR=0.2) Bead
NC OSC
N13M-GE-B-A1
R02 CV42 SA00004V050 XTALIN 1 2
2
0.1U_0402_10V7K OSC NC 2 2 2 2
2 RV30 27MHZ 16PF +-30PPM X3G027000FG1H-HX
1 1
10K_0402_5%
2
CV37 R02 CV38

G
15P_0402_50V8J 15P_0402_50V8J
1
A
1 3 CLK_REQ_GPU# 2 2 A
<15> CLK_REQ_VGA#
D
QV2
2N7002H 1N_SOT23-3 @ RV32
10K_0402_5%
1 2 Security Classification Compal Secret Data Compal Electronics, Inc.

1
RV110 @ 0_0402_5%
N13X-PCIE/DAC/GPIO
0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
U65D
Part 4 of 7
AM6 IFPA_TXC
AN6 IFPA_TXC_N NC P8
AP3 IFPA_TXD0 NC AC6
AN3 IFPA_TXD0_N NC AJ28
AN5 IFPA_TXD1 NC AJ4
AM5 IFPA_TXD1_N NC AJ5
AL6 IFPA_TXD2 NC AL11
AK6 IFPA_TXD2_N NC C15
NC
AJ6 IFPA_TXD3 NC D19
D
AH6 IFPA_TXD3_N NC D20 D
NC D23
NC D26
AJ9 IFPB_TXC NC H31
AH9 IFPB_TXC_N NC T8
AP6 IFPB_TXD4 NC V32
AP5 IFPB_TXD4_N
AM7 IFPB_TXD5
AL7 IFPB_TXD5_N
AN8 IFPB_TXD6
AM8 IFPB_TXD6_N
AK8 IFPB_TXD7
AL8 IFPB_TXD7_N
L4 VCCSENSE_VGA VCCSENSE_VGA <54>
VDD_SENSE
AK1 IFPC_L0
AJ1 IFPC_L0_N
AJ3 L5 VSSSENSE_VGA VSSSENSE_VGA <54>
IFPC_L1 GND_SENSE
AJ2 IFPC_L1_N
AH3 IFPC_L2 trace width: 16mils
AH4
AG5
IFPC_L2_N differential voltage sensing.
IFPC_L3
AG4 IFPC_L3_N differential signal routing.
TEST
AM1 AK11 TESTMODE
IFPD_L0 TESTMODE
AM2 IFPD_L0_N
AM3 IFPD_L1 JTAG_TCK AM10 TV2
1
AM4 IFPD_L1_N JTAG_TDI AM11 TV3
AL3 IFPD_L2 JTAG_TDO AP12 TV4
C AL4 AP11 10K_0402_5% C
IFPD_L2_N JTAG_TMS TV5
AK4 AN11 1 2 RV33
IFPD_L3 JTAG_TRST_N RV34 10K_0402_5%
AK5
2
IFPD_L3_N
LVDS/TMDS
AD2 IFPE_L0
AD3 IFPE_L0_N
AD1
AC1
IFPE_L1 SERIAL
IFPE_L1_N ROM_CS
AC2 IFPE_L2 ROM_CS_N H6
AC3 H4 ROM_SCLK ROM_SCLK <32>
IFPE_L2_N ROM_SCLK ROM_SI
AC4 IFPE_L3 ROM_SI H5 ROM_SI <32>
AC5 H7 ROM_SO ROM_SO <32>
IFPE_L3_N ROM_SO
AE3 IFPF_L0
AE4 IFPF_L0_N
AF4 IFPF_L1
AF5 IFPF_L1_N GENERAL
AD4 RV35 10K_0402_5%
IFPF_L2
AD5 IFPF_L2_N BUFRST_N L2 2 1
AG1 IFPF_L3
AF1 IFPF_L3_N CEC L3 1 2 +3VS_VGA
RV230 N13P@ 10K_0402_5% R02 3V3 on N13P-GL/ for CEC signal
MULTI_STRAP_REF0_GND J1 1 2
RV38 N13P@40.2K_0402_1%
AG3 IFPC_AUX_I2CW _SCL
AG2 IFPC_AUX_I2CW _SDA_N
J2 STRAP0 STRAP0 <32>
STRAP0 STRAP1
B STRAP1 J7 STRAP1 <32> B
AK3 J6 STRAP2 STRAP2 <32>
IFPD_AUX_I2CX_SCL STRAP2 STRAP3
AK2 IFPD_AUX_I2CX_SDA_N STRAP3 J5 STRAP3 <32>
J3 STRAP4 STRAP4 <32>
STRAP4
AB3 IFPE_AUX_I2CY_SCL
AB4 IFPE_AUX_I2CY_SDA_N
THERMDP K3
THERMDN K4
AF3 IFPF_AUX_I2CZ_SCL
AF2 IFPF_AUX_I2CZ_SDA_N
Reserve 1MB SPI ROM FOR VBIOS ROM
+3VS_VGA
CV295
N13P-GL-A1 MP
2 1
20mils
N13P@
1
0.1U_0402_16V4Z
@ RV229 @ @ RV225
10K_0402_5% 10K_0402_5%
2
@ RV224
@RV224 0_0402_5% UV15 @
ROM_CS 1 2 ROM_CS_R 1 8
ROM_SO ROM_SO_R CS# VCC ROM_HOLD#
1 2 2 DO HOLD# 7
@RV226
@ RV226 0_0402_5% 3 6
W P# CLK @ RV228 0_0402_5%
4 GND DIO 5
ROM_SCLK_R 1 2 ROM_SCLK
A MX25L1005AMC-12G SOP ROM_SI_R 1 2 ROM_SI A
@ RV227 0_0402_5%

N13X-LVDS/HDMI/DP/THM
0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
+1.5VS_VGA U65E
Near GPU
Near GPU Part 5 of 7 2000mA +1.05VS_VGA
3.5A
D AA27 AG19 D
FBVDDQ_0 PEX_IOVDD_0
22U_0805_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CV273
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
AA30 AG21
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CV269
CV270
CV271
CV272
CV43
CV44
CV45
CV46
CV47
CV48
CV49
CV50
CV51
CV52
1 2 2 2 2 AB27 AG22 1 1 1 1 1 1 2 2 2 2
AB33 AG24
AC27 AH21
@ FBVDDQ_4 PEX_IOVDD_4
AD27 AH25
2 1 1 1 1 FBVDDQ_5 PEX_IOVDD_5 2 2 2 2 2 2 1 1 1 1
AE27
FBVDDQ_6
AF27
+1.5VS_VGA FBVDDQ_7
AG27 AG13
FBVDDQ_8 PEX_IOVDDQ_0
4.7uF X7R 0402 * 2 B13
AG15 Under GPU(below 150mils) +1.05VS_VGA
B16 AG16
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
Under GPU(below 150mils) B19
AG18
CV54
CV53
CV56
CV55
1uF X7R 0402 * 2 0.1uF X7R 0402 * 8 E13 FBVDDQ_12 PEX_IOVDDQ_4 AG25 1 1 1 1
E16 FBVDDQ_13 PEX_IOVDDQ_5 AH15
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
E19 FBVDDQ_14 PEX_IOVDDQ_6 AH18
1U_0603_6.3V6M
1U_0603_6.3V6M
CV267
CV268
CV277
CV278
CV279
CV280
CV292
CV287
CV294
CV284
CV285
CV286
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 H10 FBVDDQ_15 PEX_IOVDDQ_7 AH26

2 2 2 2
H11 FBVDDQ_16 PEX_IOVDDQ_8 AH27
H12 FBVDDQ_17 PEX_IOVDDQ_9 AJ27
H13 FBVDDQ_18 PEX_IOVDDQ_10 AK27
2 2 2 2 2 2 2 2 2 2 2 2 H14 AL27
POWER
H15 FBVDDQ_20 PEX_IOVDDQ_12 AM28
H16 AN28 Under GPU(below 150mils) LV2 N13M@
H18 FBVDDQ_22
H19 +3VS_VGA
FBVDDQ_23
H20 FBVDDQ_24
0.1U_0402_10V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
H21 AH12 +PEX_PLLHVDD RV138 1 N13M@ 2 0_0402_5%
FBVDDQ_25 PEX_PLL_HVDD
CV70
CV74
CV73
H22 FBVDDQ_26 1 1 1
H23 FBVDDQ_27 0_0603_5%
H24 FBVDDQ_28
H8 AG12 +PEX_SVDD3V3
FBVDDQ_29 PEX_SVDD_3V3 2 2 2
H9
rise 1.5v system source voltage to 1.55-1.57V L27
FBVDDQ_30
FBVDDQ_31
+1.05VS_VGA
M27 LV2 N13P@
N27
FBVDDQ_32
AG26 +PEX_PLLVDD +PEX_PLLVDD 120mA 2 1
FBVDDQ_33 PEX_PLLVDD
1U_0603_10V6K
0.1U_0402_10V7K
4.7U_0805_25V6-K
C
P27 FBVDDQ_34 C
CV65
CV66
CV3
R27 1 1 1 BLM18PG121SN1D_0603
FBVDDQ_35
T27 FBVDDQ_36 +3VS_VGA
120ohms @100MHz (ESR=0.18)
T30 FBVDDQ_37 VDD33_0 J8
T33 FBVDDQ_38 VDD33_1 K8 Place near balls Place near GPU 2 2 2
V27 L8 RV5
FBVDDQ_39 VDD33_2 +VDD33
W27 FBVDDQ_40 VDD33_3 M8 2 1
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0603_6.3V6K
W30 FBVDDQ_41
+1.5VS_VGA
1U_0402_6.3V6K
CV109
CV111
CV293
CV75
W33 1 1 1 1 0_0603_5%
FBVDDQ_42
Y27
FBVDDQ_43 RV40 2 10K_0402_5%
AH8 +IFPAB_PLLVDD1 Place near balls
IFPAB_PLLVDD RV48 1 @
AJ8 2 1K_0402_1%
IFPAB_RSET 2 2 2 2
2 RV141 @1 FB_VDDQ_SENSE
10_0402_5% AG8 +IFPAB_IOVDD 1 RV65 2 10K_0402_5%
@ IFPA_IOVDD
AG9
IFPB_IOVDD
2 RV142 1 FB_VSS_SENSE F1
10_0402_5% FB_VDDQ_SENSE
AF7 +IFPC_PLLVDD 1 RV42 2 10K_0402_5%
+1.5VS_VGA IFPC_PLLVDD RV43 2 @ Reserve for NV DG
F2 AF8 1 1K_0402_1%
FB_GND_SENSE IFPC_RSET
AF6 +IFPC_IOVDD 1 RV44 2 10K_0402_5% +VDD33
IFPC_IOVDD
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2 J27
FB_CAL_PD_VDDQ
CV303
CV304
RV6 40.2_0402_1%
CALIBRATION PIN DDR3 AG7 +IFPD_PLLVDD 1 RV45 2 10K_0402_5%
1 1
IFPD_PLLVDD RV46 1 @
1 2 H27 AN2 2 1K_0402_1%
RV8 42.2_0402_1% FB_CAL_PU_GND IFPD_RSET @
FB_CAL_x_PD_VDDQ 40.2Ohm AG6 +IFPD_IOVDD 1 RV47 2 10K_0402_5% @ 2 2
IFPD_IOVDD
1 2 H25
RV9 51.1_0402_1% FB_CAL_TERM_GND
FB_CAL_x_PU_GND 42.2Ohm AB8 +IFPEF_PLLVDD1 RV72 2 10K_0402_5%
IFPEF_PLVDD RV50 2 1K_0402_1% R02
AD6 1
IFPEF_RSET
FB_CAL_xTERM_GND 51.1Ohm Place near balls AC7
IFPE_IOVDD +IFPE_IOVDD1 RV73 2 10K_0402_5%
AC8
IFPF_IOVDD
B B
+3VS to +3VS_VGA
N13P-GL-A1 MP
N13P@ +3VS +3VS_VGA

J10
@
1 2
1 2
JUMP_43X79
+5VALW
QV5 CV57
LP2301ALT1G_SOT23 10U_0603_6.3V6M
D
R1109 @ 3 1 2 1
0_0402_5% R1103
1
2 1 100K_0402_5%
<10,42,46,51,52,53,54> SUSP#
G
2
2
RV205 RV206
DGPU_PWR_EN# 1 2 470_0603_5%
10K_0402_5% @
1 2
1
D
CV241
R1104 1 D
0.1U_0402_10V7K
2 @ 1 2 Q128 RV207 @
<18,23> DGPU_PWR_EN
G 2N7002_SOT23 2 2 1DGPU_PWR_EN#
0_0402_5% S QV6 @ G
3
2 S 10K_0402_5%
3
1
2N7002_SOT23
R1105
0.1U_0402_10V7K
@ CV242
100K_0402_5% 1
2
A A
2
Security Classification
2011/06/15
Compal Secret Data
2012/07/11 Title
Compal Electronics, Inc.
N13X-POWER
0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
U65F
Part 6 of 7
A2 GND_0 GND_100 D2
AA17 GND_1 GND_101 D31
AA18 GND_2 GND_102 D33
AA20 E10 U65G +VGA_CORE
GND_3 GND_103 +VGA_CORE
AA22 GND_4 GND_104 E22
AB12 GND_5 GND_105 E25
AB14 E5 Part 7 of 7 V17
GND_6 GND_106 VDD_56
AB16 GND_7 GND_107 E7 AA12 VDD_0 VDD_57 V18
AB19 GND_8 GND_108 F28 AA14 VDD_1 VDD_58 V20
AB2 GND_9 GND_109 F7 AA16 VDD_2 VDD_59 V22
D
AB21 GND_10 GND_110 G10 AA19 VDD_3 VDD_60 W 12 D
A33 GND_11 GND_111 G13 AA21 VDD_4 VDD_61 W 14
AB23 GND_12 GND_112 G16 AA23 VDD_5 VDD_62 W 16
AB28 GND_13 GND_113 G19 AB13 VDD_6 VDD_63 W 19
AB5 GND_16 GND_116 G25 AB18 VDD_9 VDD_66 Y13
AB7 GND_17 GND_117 G28 AB20 VDD_10 VDD_67 Y15
AC13 GND_18 GND_118 G3 AB22 VDD_11 VDD_68 Y17
AC15 GND_19 GND_119 G30 AC12 VDD_12 VDD_69 Y18
AA13 GND_22 GND_122 G5 AC19 VDD_15
AC20 GND_23 GND_123 G7 AC21 VDD_16
AC22 GND_24 GND_124 K2 AC23 VDD_17 XVDD_1 U1
AE2 GND_25 GND_125 K28 M12 VDD_18 XVDD_2 U2
POWER
AE7 GND_31 GND_131 M13 N13 VDD_24 XVDD_8 U8
AH10 GND_32 GND_132 M15 N15 VDD_25
AA15 GND_33 GND_133 M17 N17 VDD_26
AH13 GND_34 GND_134 M18 N18 VDD_27 XVDD_9 V1
AH2 GND_37 GND_137 N12 P12 VDD_30 XVDD_12 V4
C AH28 GND_40 GND_140 N19 P19 VDD_33 XVDD_15 V7 C
AH30 GND_42 GND_142 N21 P23 VDD_35
GND
AH32 GND_43 GND_143 N23 R13 VDD_36
AH33 GND_44 GND_144 N28 R15 VDD_37 XVDD_17 W2
AJ7 GND_47 GND_147 N33 R20 VDD_40 XVDD_20 W5
AK10 GND_48 GND_148 N5 R22 VDD_41 XVDD_21 W7
AK7 GND_49 GND_149 N7 T12 VDD_42 XVDD_22 W8
AL12 GND_50 GND_150 P13 T14 VDD_43
AL14 GND_51 GND_151 P15 T16 VDD_44
AL15 GND_52 GND_152 P17 T19 VDD_45 XVDD_23 Y1
AL2 GND_55 GND_155 P22 U13 VDD_48 XVDD_26 Y4
AL20 GND_56 GND_156 R12 U15 VDD_49 XVDD_27 Y5
AL26 GND_60 GND_160 R21 U22 VDD_53
AL28 GND_61 GND_161 R23 V13 VDD_54
AL30 GND_62 GND_162 T13 V15 VDD_55 XVDD_31 AA1
AL32 GND_63 GND_163 T15 XVDD_32 AA2
AM13 GND_66 GND_166 T2 XVDD_35 AA5
B
AM22 GND_69 GND_169 AG11 XVDD_38 AA8 B
AM25 GND_70 GND_170 T28
AN1 GND_71 GND_171 T32
AN16 U12 N13P-GL-A1 MP
GND_74 GND_174
AN19 GND_75 GND_175 U14
AN22 GND_76 GND_176 U16 N13P@
AN25 GND_77 GND_177 U19
AN30 GND_78 GND_178 U21
AN34 GND_79 GND_179 U23
AN4 GND_80 GND_180 V12
AN7 GND_81 GND_181 V14
AP2 GND_82 GND_182 V16
AP33 GND_83 GND_183 V19
B1 GND_84 GND_184 V21
B10 GND_85 GND_185 V23
B22 GND_86 GND_186 W 13
B25 GND_87 GND_187 W 15
B28 GND_88 GND_188 W 17
B31 GND_89 GND_189 W 18
B34 GND_90 GND_190 W 20
B4 GND_91 GND_191 W 22
B7 GND_92 GND_192 W 28
C10 GND_93 GND_193 Y12
C13 GND_94 GND_194 Y14
C19 GND_95 GND_195 Y16
C22 GND_96 GND_196 Y19
C25 GND_97 GND_197 Y21
C28 GND_98 GND_198 Y23
A C7 GND_99 GND_199 AH11 A
GND_OPT C16
GND_OPT W 32
N13P-GL-A1 MP Security Classification Compal Secret Data Compal Electronics, Inc.

N13P@
N13-VGA CORE, GND
0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
FBA_D[0..63] FBA_MA[15..0] <28,29> FBC_D[0..63] FBC_MA[15..0] <30,31>

<28,29> FBA_D[0..63] <30,31> FBC_D[0..63]
FBA_BA[2..0] <28,29> FBC_BA[2..0] <30,31>
U65C
U65B
Part 3 of 7
Part 2 of 7 FBC_D0 G9 D13 FBC_CS0#_L
FBB_D0 FBB_CMD0 FBC_CS0#_L <30>
FBA_D0 L28 U30 FBA_CS0#_L FBC_D1 E9 E14
FBA_D0 FBA_CMD0 FBA_CS0#_L <28> FBB_D1 FBB_CMD1
FBA_D1 M29 T31 FBC_D2 G8 F14 FBC_ODT_L
FBA_D1 FBA_CMD1 FBB_D2 FBB_CMD2 FBC_ODT_L <30>
FBA_D2 L29 U29 FBA_ODT_L FBC_D3 F9 A12 FBC_CKE_L
FBA_D2 FBA_CMD2 FBA_ODT_L <28> FBB_D3 FBB_CMD3 FBC_CKE_L <30>
FBA_D3 M28 R34 FBA_CKE_L FBC_D4 F11 B12 FBC_MA14
FBA_D3 FBA_CMD3 FBA_CKE_L <28> FBB_D4 FBB_CMD4
FBA_D4 N31 R33 FBA_MA14 FBC_D5 G11 C14 FBC_RST#
D FBA_D4 FBA_CMD4 FBB_D5 FBB_CMD5 FBC_RST# <30,31> D
FBA_D5 P29 U32 FBA_RST# FBC_D6 F12 B14 FBC_MA9
FBA_D5 FBA_CMD5 FBA_RST# <28,29> FBB_D6 FBB_CMD6
FBA_D6 R29 U33 FBA_MA9 FBC_D7 G12 G15 FBC_MA7
FBA_D7 FBA_D6 FBA_CMD6 FBA_MA7 FBC_D8 FBB_D7 FBB_CMD7 FBC_MA2
P28 U28 G6 F15
J28 V28 F5 E15
H29 V29 E6 D15
J29 V30 F6 A14
FBA_D11 FBA_D10 FBA_CMD10 FBA_MA1 FBC_D12 FBB_D11 FBB_CMD11 FBC_BA0
H28 U34 F4 D14
FBA_D12 FBA_D11 FBA_CMD11 FBA_BA0 FBC_D13 FBB_D12 FBB_CMD12 FBC_WE#
G29 U31 G4 A15 FBC_WE# <30,31>
FBA_D13 FBA_D12 FBA_CMD12 FBA_WE# FBC_D14 FBB_D13 FBB_CMD13 FBC_MA15
E31 V34 FBA_WE# <28,29> E2 B15
FBA_D14 FBA_D13 FBA_CMD13 FBA_MA15 FBC_D15 FBB_D14 FBB_CMD14 FBC_CAS#
E32 V33 F3 C17 FBC_CAS# <30,31>
FBA_D15 FBA_D14 FBA_CMD14 FBA_CAS# FBC_D16 FBB_D15 FBB_CMD15 FBC_CS0#_H
F30 Y32 FBA_CAS# <28,29> C2 D18 FBC_CS0#_H <31>
FBA_D16 FBA_D15 FBA_CMD15 FBA_CS0#_H FBC_D17 FBB_D16 FBB_CMD16
C34 AA31 FBA_CS0#_H <29> D4 E18
FBA_D17 FBA_D16 FBA_CMD16 FBC_D18 FBB_D17 FBB_CMD17 FBC_ODT_H
D32 AA29 D3 F18 FBC_ODT_H <31>
FBA_D18 FBA_D17 FBA_CMD17 FBA_ODT_H FBC_D19 FBB_D18 FBB_CMD18 FBC_CKE_H
B33 AA28 FBA_ODT_H <29> C1 A20 FBC_CKE_H <31>
FBA_D19 FBA_D18 FBA_CMD18 FBA_CKE_H FBC_D20 FBB_D19 FBB_CMD19 FBC_MA13
C33 AC34 FBA_CKE_H <29> B3 B20
F33 AC33 C4 C18
F32 AA32 B5 B18
H33 AA33 C5 G18
FBA_D23 H32
FBA_D22
FBA_D23
FBA_CMD22
FBA_CMD23
Y28 FBA_MA11 FBC_D24 A11
FBB_D23
FBB_D24
FBB_CMD23
FBB_CMD24
G17 FBC_MA5 Mode D - Mirror Mode Mapping
FBA_D24 P34 Y29 FBA_MA5 FBC_D25 C11 F17 FBC_MA3
MEMORY INTERFACE
FBA_D25 FBA_D24 FBA_CMD24 FBA_MA3 FBC_D26 FBB_D25 FBB_CMD25 FBC_BA2
MEMORY INTERFACE B
P32 W31 D11 D16
FBA_D26 FBA_D25 FBA_CMD25 FBA_BA2 FBC_D27 FBB_D26 FBB_CMD26 FBC_BA1
P31 Y30 B11 A18
FBA_D27 FBA_D26 FBA_CMD26 FBA_BA1 FBC_D28 FBB_D27 FBB_CMD27 FBC_MA12
P33
FBA_D27 FBA_CMD27
AA34 D8
FBB_D28 FBB_CMD28
D17 DATA Bus
FBA_D28 L31 Y31 FBA_MA12 FBC_D29 A8 A17 FBC_MA10
FBA_D29 FBA_D28 FBA_CMD28 FBA_MA10 FBC_D30 FBB_D29 FBB_CMD29 FBC_RAS# Address
L34
FBA_D29 FBA_CMD29
Y34 C8
FBB_D30 FBB_CMD30
B17 FBC_RAS# <30,31> 0..31 32..63
FBA_D30 L32 Y33 FBA_RAS# FBC_D31 B8 E17
FBA_D30 FBA_CMD30 FBA_RAS# <28,29> FBB_D31 FBB_CMD31
FBA_D31 L33 V31 FBC_D32 F24 FBx_CMD0 CS0#_L
FBA_D32 FBA_D31 FBA_CMD31 FBC_D33 FBB_D32
AG28 G23
FBA_D33 FBA_D32 FBC_D34 FBB_D33
AF29
FBA_D33
E24
FBB_D34 FBx_CMD1
FBA_D34 AG29 FBC_D35 G24 C12
FBA_D35 FBA_D34 FBC_D36 FBB_D35 FBB_CMD_RFU0
AF28
FBA_D35 FBA_CMD_RFU0
R32 D21
FBB_D36 FBB_CMD_RFU1
C20 FBx_CMD2 ODT_L
FBA_D36 AD30 AC32 FBC_D37 E21
C FBA_D37 FBA_D36 FBA_CMD_RFU1 +1.5VS_VGA FBC_D38 FBB_D37 +1.5VS_VGA C
AD29
FBA_D37
G21
FBB_D38 FBx_CMD3 CKE_L
FBA_D38 AC29 FBC_D39 F21
FBA_D38 FBB_D39 RV60 1 @
FBA_D39 AD28 FBC_D40 G27 G14 2 60.4_0402_1% FBx_CMD4 A14 A14
FBA_D39 FBB_D40 FBB_DEBUG0
A
FBA_D40 AJ29 R28 RV58 1 @ 2 60.4_0402_1% FBC_D41 D27 G20 RV61 1 @ 2 60.4_0402_1%
FBA_D40 FBA_DEBUG0 RV59 @ FBB_D41 FBB_DEBUG1
FBA_D41 AK29 AC28 1 2 60.4_0402_1% FBC_D42 G26 can be unstuff by default FBx_CMD5 RST RST
FBA_D42 FBA_D41 FBA_DEBUG1 FBC_D43 FBB_D42
AJ30
FBA_D42 can be unstuff by default E27
FBB_D43
FBA_D43 AK28 FBC_D44 E29 FBx_CMD6 A9 A9
FBA_D44 FBA_D43 FBC_D45 FBB_D44 FBC_CLK0
AM29 F29 D12 FBC_CLK0 <30>
FBA_D45 FBA_D44 FBA_CLK0 FBC_D46 FBB_D45 FBB_CLK0 FBC_CLK0#
AM31
FBA_D45 FBA_CLK0
R30 FBA_CLK0 <28> E30
FBB_D46 FBB_CLK0_N
E12 FBC_CLK0# <30> FBx_CMD7 A7 A7
FBA_D46 AN29 R31 FBA_CLK0# FBC_D47 D30 E20 FBC_CLK1
FBA_D46 FBA_CLK0_N FBA_CLK0# <28> FBB_D47 FBB_CLK1 FBC_CLK1 <31>
FBA_D47 AM30 AB31 FBA_CLK1 FBC_D48 A32 F20 FBC_CLK1# FBx_CMD8 A2 A2
FBA_D47 FBA_CLK1 FBA_CLK1 <29> FBB_D48 FBB_CLK1_N FBC_CLK1# <31>
FBA_D48 AN31 AC31 FBA_CLK1# FBC_D49 C31
FBA_D48 FBA_CLK1_N FBA_CLK1# <29> FBB_D49
FBA_D49 AN32 FBC_D50 C32 FBx_CMD9 A0 A0
AP30 B32
AP32
FBA_D51
D29
FBB_D52 FBB_WCK01
F8 FBx_CMD10 A4 A4
FBA_D52 AM33 K31 FBC_D53 A29 E8
FBA_D53 FBA_D52 FBA_WCK01 FBC_D54 FBB_D53 FBB_WCK01_N
AL31
FBA_D53 FBA_WCK01_N
L30 C29
FBB_D54 FBB_WCK23
A5 FBx_CMD11 A1 A1
FBA_D54 AK33 H34 FBC_D55 B29 A6
AK32
FBA_D55 FBA_WCK23_N
J34 B21
FBB_D56 FBB_WCK45
D24 FBx_CMD12 BA0 BA0
FBA_D56 AD34 AG30 FBC_D57 C23 D25
AD32
FBA_D57 FBA_WCK45_N
AG31 A21
FBB_D58 FBB_WCK67
B27 FBx_CMD13 WE# WE#
FBA_D58 AC30 AJ34 FBC_D59 C21 C27
AD33
FBA_D59 FBA_WCK67_N
AK34 B24
FBB_D60 FBx_CMD14 A15 A15
FBA_D60 AF31 FBC_D61 C24
FBA_D61 FBA_D60 +1.05VS_VGA +FB_PLLAVDD FBC_D62 FBB_D61
AG34
FBA_D61
B26
FBB_D62 FBx_CMD15 CAS# CAS#
FBA_D62 AG32 Place close to BGA FBC_D63 C26 D6
FBA_D63 FBA_D62 FBB_D63 FBB_WCKB01
AG33
FBA_D63 FBA_WCKB01
J30 200mA FBB_WCKB01_N
D7 FBx_CMD16 CS0#_H
J31 BLM18PG330SN1D_0603 FBC_DQM0 E11 C6
FBA_DQM0 FBA_WCKB01_N FBB_DQM0 FBB_WCKB23
P30 J32 1 2 +FB_PLLAVDD FBC_DQM1 E3 B6 FBx_CMD17
FBA_DQM1 FBA_DQM0 FBA_WCKB23 LV3 FBC_DQM2 FBB_DQM1 FBB_WCKB23_N
F31 J33 A3 F26
FBA_DQM2 FBA_DQM1 FBA_WCKB23_N FBC_DQM3 FBB_DQM2 FBB_WCKB45
F34
FBA_DQM2 FBA_WCKB45
AH31 C9
FBB_DQM3 FBB_WCKB45_N
E26 FBx_CMD18 ODT_H
FBA_DQM3 M32 AJ31 FBC_DQM4 F23 A26
B FBA_DQM4 FBA_DQM3 FBA_WCKB45_N FBC_DQM5 FBB_DQM4 FBB_WCKB67 B
AD31
FBA_DQM4 FBA_WCKB67
AJ32 F27
FBB_DQM5 FBB_WCKB67_N
A27 FBx_CMD19 CKE_H
FBA_DQM5 AL29 AJ33 FBC_DQM6 C30
FBA_DQM6 FBA_DQM5 FBA_WCKB67_N FBC_DQM7 FBB_DQM6
AM32
FBA_DQM6
A24
FBB_DQM7 FBx_CMD20 A13 A13
FBA_DQM7 AF34 R02
FBA_DQM7 RV66 N13M@ 10K_0402_5% FBC_DQS0 D10
FBB_DQS_WP0 FBx_CMD21 A8 A8
FBA_DQS0 M31 E1 FB_CLAMP 2 1 FBC_DQS1 D5
FBA_DQS1 FBA_DQS_WP0 FB_CLAMP FBC_DQS2 FBB_DQS_WP1
G31
FBA_DQS_WP1 +FB_PLLAVDD C3
FBB_DQS_WP2 FBx_CMD22 A6 A6
FBA_DQS2 E33 FBC_DQS3 B9
FBA_DQS3 FBA_DQS_WP2 CV106 0.1U_0402_10V7K FBC_DQS4 FBB_DQS_WP3
M33
FBA_DQS_WP3
E23
FBB_DQS_WP4 FBB_PLL_AVDD
H17 +FB_PLLAVDD FBx_CMD23 A11 A11
FBA_DQS4 FBC_DQS5
0.1U_0402_10V7K
AE31 K27 1 2 E28
FBA_DQS_WP4 FB_DLL_AVDD FBB_DQS_WP5
CV108
FBA_DQS5 AK30 FBC_DQS6 B30 1 FBx_CMD24 A5 A5
FBA_DQS6 FBA_DQS_WP5 FBC_DQS7 FBB_DQS_WP6
AN33
FBA_DQS_WP6
Place close to ball A23
FBB_DQS_WP7
FBA_DQS7 AF33 FBx_CMD25 A3 A3
FBA_DQS_WP7 FBC_DQS#0
U27 +FB_PLLAVDD D9
FBA_DQS#0 FBA_PLL_AVDD FBC_DQS#1 FBB_DQS_RN0 2 FBx_CMD26 BA2 BA2
22U_0805_6.3V6M
0.1U_0402_10V7K
M30 E4
FBA_DQS_RN0 FBB_DQS_RN1
CV107
CV110
FBA_DQS#1 FBC_DQS#2
1U_0402_6.3V6K
H30 1 1 1 B2
FBA_DQS_RN1 FBB_DQS_RN2
CV39
FBA_DQS#2 E34 FBC_DQS#3 A9 FBx_CMD27 BA1 BA1

FBA_DQS#3 FBA_DQS_RN2 FBC_DQS#4 FBB_DQS_RN3
M34 H26 D22
FBA_DQS#4 AF30 FBA_DQS_RN3 FB_VREF FBC_DQS#5 FBB_DQS_RN4
FBA_DQS_RN4 2 2 2
D28
FBB_DQS_RN5
Place close to ball FBx_CMD28 A12 A12
FBA_DQS#5 AK31 FBC_DQS#6 A30
FBA_DQS#6 AM34 FBA_DQS_RN5 FBC_DQS#7 FBB_DQS_RN6
FBA_DQS_RN6
B23
FBB_DQS_RN7 FBx_CMD29 A10 A10
FBA_DQS#7 AF32
FBA_DQS_RN7
FBx_CMD30 RAS# RAS#
Place close to ball Place close to BGA
N13P-GL-A1 MP N13P@
N13P-GL-A1 MP N13P@
<30,31> FBC_DQM[7..0]
<28,29> FBA_DQM[7..0] <30,31> FBC_DQS[7..0]
A <28,29> FBA_DQS[7..0] <30,31> FBC_DQS#[7..0] A
<28,29> FBA_DQS#[7..0] 30ohms (ESR=0.01) Bead
P/N;SM010007W00

N13X-MEM Interface
0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
FBA_D[0..63] <27,29>
Memory Partition A - Lower 32 bits FBA_MA[15..0] <27,29>
FBA_BA[2..0] <27,29>
UV3 UV4
FBA_DQM[7..0] <27,29>
+1.5VS_VGA +FBA_VREF0 M8 E3 FBA_D4 +FBA_VREF0 M8 E3 FBA_D19
VREFCA DQL0 VREFCA DQL0 FBA_DQS[7..0] <27,29>
D H1 F7 FBA_D1 H1 F7 FBA_D20 D
VREFDQ DQL1 FBA_D7 VREFDQ DQL1 FBA_D17
DQL2 F2 DQL2 F2 FBA_DQS#[7..0] <27,29>
1
FBA_MA0 N3 F8 FBA_D0 FBA_MA0 N3 F8 FBA_D21 Group2 (IN1)

RV79 FBA_MA1 A0 DQL3 FBA_D6 FBA_MA1 A0 DQL3 FBA_D16
P7 A1 DQL4 H3 Group0 (IN3) P7 A1 DQL4 H3
FBA_MA2 P3 H8 FBA_D3 FBA_MA2 P3 H8 FBA_D23
1.1K_0402_1% FBA_MA3 N2
A2
A3
DQL5
DQL6 G2 FBA_D5 FBA_MA3 N2
A2
A3
DQL5
DQL6 G2 FBA_D18 CMD mapping mod Mode D
FBA_MA4 P8 H7 FBA_D2 FBA_MA4 P8 H7 FBA_D22
2
+FBA_VREF0 FBA_MA5 A4 DQL7 FBA_MA5 A4 DQL7

P2 A5 P2 A5
FBA_MA6 R8 FBA_MA6 R8 DATA Bus
1
A6 A6
CV118
FBA_MA7 R2 D7 FBA_D29 FBA_MA7 R2 D7 FBA_D10

0.01U_0402_25V7K
1 A7 DQU0 A7 DQU0
RV68 FBA_MA8 T8 C3 FBA_D25 FBA_MA8 T8 C3 FBA_D15 Address 0..31 32..63
FBA_MA9 A8 DQU1 FBA_D28 FBA_MA9 A8 DQU1 FBA_D8
R3 A9 DQU2 C8 R3 A9 DQU2 C8
1.1K_0402_1% FBA_MA10 L7 C2 FBA_D26 FBA_MA10 L7 C2 FBA_D13 Group1 (TOP) FBx_CMD0 CS0#_L
2 FBA_MA11 A10/AP DQU3 FBA_D31 FBA_MA11 A10/AP DQU3 FBA_D9
R7 A7 Group3 (BOT) R7 A7
2

N7 A12 DQU5 A2 N7 A12 DQU5 A2 FBx_CMD1
FBA_MA13 T3 B8 FBA_D30 FBA_MA13 T3 B8 FBA_D11
T7 A14 DQU7 A3 T7 A14 DQU7 A3 FBx_CMD2 ODT_L
FBA_MA15 M7 FBA_MA15 M7
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA FBx_CMD3 CKE_L
FBA_BA0 M2 B2 FBA_BA0 M2 B2 FBx_CMD4 A14 A14
FBA_BA1 BA0 VDD FBA_BA1 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
FBA_CLK0 FBA_BA2 M3 G7 FBA_BA2 M3 G7 FBx_CMD5 RST RST
BA2 VDD BA2 VDD
VDD K2 VDD K2
VDD K8 VDD K8 FBx_CMD6 A9 A9
2
VDD N1 VDD N1
RV80 FBA_CLK0 J7 N9 FBA_CLK0 J7 N9 FBx_CMD7 A7 A7
<27> FBA_CLK0 CK VDD CK VDD
C 160_0402_1% FBA_CLK0# K7 R1 FBA_CLK0# K7 R1 C
<27> FBA_CLK0# CK VDD CK VDD
FBA_CKE_L K9 R9 FBA_CKE_L K9 R9 FBx_CMD8 A2 A2
<27> FBA_CKE_L CKE/CKE0 VDD CKE/CKE0 VDD
1
FBx_CMD9 A0 A0
FBA_CLK0# FBA_ODT_L K1 A1 FBA_ODT_L K1 A1
<27> FBA_ODT_L ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBA_CS0#_L L2 A8 FBA_CS0#_L L2 A8 FBx_CMD10 A4 A4
<27> FBA_CS0#_L CS/CS0 VDDQ CS/CS0 VDDQ
FBA_RAS# J3 C1 FBA_RAS# J3 C1
<27,29> FBA_RAS# RAS VDDQ RAS VDDQ
FBA_CAS# K3 C9 FBA_CAS# K3 C9 FBA_ODT_L FBx_CMD11 A1 A1
<27,29> FBA_CAS# CAS VDDQ CAS VDDQ
FBA_WE# L3 D2 FBA_WE# L3 D2
<27,29> FBA_WE# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 FBx_CMD12 BA0 BA0
F1 F1 FBA_CKE_L
FBA_DQS0 VDDQ FBA_DQS2 VDDQ
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2 FBx_CMD13 WE# WE#
FBA_DQS3 C7 H9 FBA_DQS1 C7 H9
DQSU VDDQ DQSU VDDQ
2
FBx_CMD14 A15 A15
RV67 RV76
FBA_DQM0 E7 A9 FBA_DQM2 E7 A9 10K_0402_5% 10K_0402_5% FBx_CMD15 CAS# CAS#
FBA_DQM3 DML VSS FBA_DQM1 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3
E1 E1 FBx_CMD16 CS0#_H
1
VSS VSS
VSS G8 VSS G8
FBA_DQS#0 G3 J2 FBA_DQS#2 G3 J2 FBx_CMD17
FBA_DQS#3 B7 DQSL VSS FBA_DQS#1 B7 DQSL VSS
DQSU VSS J8 DQSU VSS J8
VSS M1 VSS M1 FBx_CMD18 ODT_H
VSS M9 VSS M9
VSS P1 VSS P1 FBx_CMD19 CKE_H
FBA_RST# T2 P9 FBA_RST# T2 P9
<27,29> FBA_RST# RESET VSS RESET VSS
VSS T1 VSS T1 FBx_CMD20 A13 A13
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
B FBx_CMD21 A8 A8 B
1
1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 FBx_CMD22 A6 A6
1
RV78 RV77 L1 B9 RV69 L1 B9

10K_0402_5% NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 FBx_CMD23 A11 A11
L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8
E2 E2 FBx_CMD24 A5 A5
2
VSSQ 2 VSSQ
E8 E8
2
VSSQ VSSQ
VSSQ F9 VSSQ F9 FBx_CMD25 A3 A3
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 FBx_CMD26 BA2 BA2
96-BALL 96-BALL FBx_CMD27 BA1 BA1
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 FBx_CMD28 A12 A12
X76@ X76@
FBx_CMD29 A10 A10
+1.5VS_VGA UV3 SIDE +1.5VS_VGA UV4 SIDE FBx_CMD30 RAS# RAS#
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CV119
CV120
CV121
CV123
CV162
@ CV161
CV159
CV134
CV129
CV160
CV133
CV132
CV164
@ CV136
CV163
CV137
CV135
@ CV157
@ CV155
@ CV138
CV142
@ CV143
@ CV144
CV158
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A

N13X-VRAM A Lower
0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
Memory Partition A - Upper 32 FBA_D[0..63] <27,28>
bits UV5 UV6

FBA_MA[15..0] <27,28>
+1.5VS_VGA
FBA_BA[2..0] <27,28>
+FBA_VREF1 M8 E3 FBA_D36 +FBA_VREF1 M8 E3 FBA_D63
VREFCA DQL0 FBA_D34 VREFCA DQL0 FBA_D58
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 FBA_DQM[7..0] <27,28>
1 DQL2 F2 FBA_D37
DQL2 F2 FBA_D60
RV70 FBA_MA0 N3 F8 FBA_D35 FBA_MA0 N3 F8 FBA_D59
A0 DQL3 A0 DQL3 FBA_DQS[7..0] <27,28>
D FBA_MA1 P7 H3 FBA_D39 Group4 (IN1) FBA_MA1 P7 H3 FBA_D61 Group7 (IN3) D
1.1K_0402_1% FBA_MA2 A1 DQL4 FBA_D32 FBA_MA2 A1 DQL4 FBA_D56
P3 A2 DQL5 H8 P3 A2 DQL5 H8 FBA_DQS#[7..0] <27,28>
FBA_MA3 N2 G2 FBA_D38 FBA_MA3 N2 G2 FBA_D62
2
+FBA_VREF1 FBA_MA4 A3 DQL6 FBA_D33 FBA_MA4 A3 DQL6 FBA_D57

P8 A4 DQL7 H7 P8 A4 DQL7 H7
FBA_MA5 P2 FBA_MA5 P2
A5 A5
1
CV178
FBA_MA6 R8 FBA_MA6 R8
CMD mapping mod Mode D
0.01U_0402_25V7K
1 A6 A6
RV82 FBA_MA7 R2 D7 FBA_D45 FBA_MA7 R2 D7 FBA_D55
T8 A8 DQU1 C3 T8 A8 DQU1 C3
1.1K_0402_1% FBA_MA9 R3 C8 FBA_D46 FBA_MA9 R3 C8 FBA_D54 DATA Bus
2 FBA_MA10 A9 DQU2 FBA_D41 FBA_MA10 A9 DQU2 FBA_D49
L7 C2 Group5 (TOP) L7 C2
2
FBA_MA11 A10/AP DQU3 FBA_D47 FBA_MA11 A10/AP DQU3 FBA_D52 Address

R7 A11 DQU4 A7 R7 A11 DQU4 A7 Group6 (BOT) 0..31 32..63
FBA_MA12 N7 A2 FBA_D43 FBA_MA12 N7 A2 FBA_D50
T3 A13 DQU6 B8 T3 A13 DQU6 B8 FBx_CMD0 CS0#_L
FBA_MA14 T7 A3 FBA_D40 FBA_MA14 T7 A3 FBA_D48
FBA_MA15 A14 DQU7 FBA_MA15 A14 DQU7
M7 A15/BA3 +1.5VS_VGA
M7 A15/BA3 +1.5VS_VGA
FBx_CMD1
FBx_CMD2 ODT_L
FBA_BA0 M2 B2 FBA_BA0 M2 B2
FBA_BA1 BA0 VDD FBA_BA1 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 FBx_CMD3 CKE_L
FBA_CLK1 FBA_BA2 M3 G7 FBA_BA2 M3 G7
BA2 VDD BA2 VDD
VDD K8 VDD K8
2
VDD N1 VDD N1 FBx_CMD5 RST RST

RV83 FBA_CLK1 J7 N9 FBA_CLK1 J7 N9
<27> FBA_CLK1 CK VDD CK VDD
160_0402_1% FBA_CLK1# K7 R1 FBA_CLK1# K7 R1 FBx_CMD6 A9 A9
<27> FBA_CLK1# CK VDD CK VDD
FBA_CKE_H K9 R9 FBA_CKE_H K9 R9
<27> FBA_CKE_H CKE/CKE0 VDD CKE/CKE0 VDD
FBx_CMD7 A7 A7
1
C C
FBA_CLK1# FBA_ODT_H K1 A1 FBA_ODT_H K1 A1 FBx_CMD8 A2 A2
<27> FBA_ODT_H ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBA_CS0#_H L2 A8 FBA_CS0#_H L2 A8
<27> FBA_CS0#_H CS/CS0 VDDQ CS/CS0 VDDQ
FBA_RAS# J3 C1 FBA_RAS# J3 C1 FBx_CMD9 A0 A0
<27,28> FBA_RAS# RAS VDDQ RAS VDDQ
FBA_CAS# K3 C9 FBA_CAS# K3 C9
<27,28> FBA_CAS# CAS VDDQ CAS VDDQ
FBA_WE# L3 D2 FBA_WE# L3 D2 FBx_CMD10 A4 A4
<27,28> FBA_WE# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 FBx_CMD11 A1 A1
FBA_DQS4 F3 H2 FBA_DQS7 F3 H2
FBA_DQS5 DQSL VDDQ FBA_DQS6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 FBx_CMD12 BA0 BA0
FBx_CMD13 WE# WE#
FBA_DQM4 E7 A9 FBA_DQM7 E7 A9
FBA_DQM5 DML VSS FBA_DQM6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 FBx_CMD14 A15 A15
VSS E1 VSS E1
VSS G8 VSS G8 FBx_CMD15 CAS# CAS#
FBA_DQS#4 G3 J2 FBA_DQS#7 G3 J2
FBA_DQS#5 B7 DQSL VSS FBA_DQS#6 B7 DQSL VSS
DQSU VSS J8 DQSU VSS J8 FBx_CMD16 CS0#_H
VSS M1 VSS M1
FBA_CKE_H M9 M9 FBx_CMD17
VSS VSS
VSS P1 VSS P1
FBA_RST# T2 P9 FBA_RST# T2 P9 FBx_CMD18 ODT_H
<27,28> FBA_RST# RESET VSS RESET VSS
FBA_ODT_H T1 T1
VSS VSS
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 FBx_CMD19 CKE_H
FBx_CMD20 A13 A13
1
1
RV84 RV87 J1 B1 J1 B1
10K_0402_5% 10K_0402_5% RV86 NC/ODT1 VSSQ RV85 NC/ODT1 VSSQ
B L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9 FBx_CMD21 A8 A8 B
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 FBx_CMD22 A6 A6
E2 E2
2
2
VSSQ VSSQ
VSSQ E8 VSSQ E8 FBx_CMD23 A11 A11
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 FBx_CMD24 A5 A5
VSSQ G9 VSSQ G9
FBx_CMD25 A3 A3
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD26 BA2 BA2
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@ FBx_CMD27 BA1 BA1
FBx_CMD28 A12 A12
+1.5VS_VGA UV5 SIDE +1.5VS_VGA UV6 SIDE
FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CV145
CV174
CV296
CV301
CV291
CV302
CV299
CV290
CV300
CV297
CV298
CV165
CV177
@ CV170
CV166
CV172
@ CV179
@ CV173
@ CV169
@ CV180
CV167
CV171
@ CV168
@ CV175
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A

N13X-VRAM A Upper
0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
FBC_D[0..63] <27,31>
Memory Partition C - Lower 32 bits FBC_MA[15..0] <27,31>
FBC_BA[2..0] <27,31>
FBC_DQM[7..0] <27,31>
+1.5VS_VGA UV7 UV8
FBC_DQS[7..0] <27,31>
+FBB_VREF0 M8 E3 FBC_D4 +FBB_VREF0 M8 E3 FBC_D16
1 VREFCA DQL0 VREFCA DQL0 FBC_DQS#[7..0] <27,31>
D H1 F7 FBC_D3 H1 F7 FBC_D21 D
RV111 VREFDQ DQL1 FBC_D7 VREFDQ DQL1 FBC_D18
DQL2 F2 DQL2 F2
FBC_MA0 N3 F8 FBC_D0 Group0 (IN3)FBC_MA0 N3 F8 FBC_D17
1.1K_0402_1% FBC_MA1 A0 DQL3 FBC_D5 FBC_MA1 A0 DQL3 FBC_D20
P7 A1 DQL4 H3 P7 A1 DQL4 H3 Group2 (IN1) CMD mapping mod Mode D
FBC_MA2 P3 H8 FBC_D1 FBC_MA2 P3 H8 FBC_D23
2
+FBB_VREF0 FBC_MA3 A2 DQL5 FBC_D6 FBC_MA3 A2 DQL5 FBC_D19

N2 A3 DQL6 G2 N2 A3 DQL6 G2
FBC_MA4 P8 H7 FBC_D2 FBC_MA4 P8 H7 FBC_D22
A4 DQL7 A4 DQL7
1
CV202
FBC_MA5 P2 FBC_MA5 P2 DATA Bus

0.01U_0402_25V7K
1 A5 A5
RV115 FBC_MA6 R8 FBC_MA6 R8
FBC_MA7 A6 FBC_D28 FBC_MA7 A6 FBC_D8 Address
R2 A7 DQU0 D7 R2 A7 DQU0 D7 0..31 32..63
1.1K_0402_1% FBC_MA8 T8 C3 FBC_D27 FBC_MA8 T8 C3 FBC_D15
2 FBC_MA9 A8 DQU1 FBC_D31 FBC_MA9 A8 DQU1 FBC_D11
R3 C8 R3 C8 FBx_CMD0 CS0#_L
2
FBC_MA10 A9 DQU2 FBC_D25 FBC_MA10 A9 DQU2 FBC_D12

L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
FBC_MA11 R7 A7 FBC_D29 Group3 (BOT)FBC_MA11 R7 A7 FBC_D9 Group1 (TOP) FBx_CMD1
N7 A12 DQU5 A2 N7 A12 DQU5 A2
FBC_MA13 T3 B8 FBC_D30 FBC_MA13 T3 B8 FBC_D10 FBx_CMD2 ODT_L
T7 A14 DQU7 A3 T7 A14 DQU7 A3
FBC_MA15 M7 FBC_MA15 M7 FBx_CMD3 CKE_L
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA
FBx_CMD4 A14 A14
FBC_BA0 M2 B2 FBC_BA0 M2 B2
FBC_BA1 BA0 VDD FBC_BA1 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 FBx_CMD5 RST RST
FBC_CLK0 FBC_BA2 M3 G7 FBC_BA2 M3 G7
BA2 VDD BA2 VDD
VDD K8 VDD K8
2
310mA VDD N1 VDD N1 FBx_CMD7 A7 A7

RV89 FBC_CLK0 J7 N9 FBC_CLK0 J7 N9
<27> FBC_CLK0 CK VDD CK VDD
C 160_0402_1% FBC_CLK0# K7 R1 FBC_CLK0# K7 R1 FBx_CMD8 A2 A2 C
<27> FBC_CLK0# CK VDD CK VDD
FBC_CKE_L K9 R9 FBC_CKE_L K9 R9
<27> FBC_CKE_L CKE/CKE0 VDD CKE/CKE0 VDD
FBx_CMD9 A0 A0
1
FBC_CLK0# FBC_ODT_L K1 A1 FBC_ODT_L K1 A1 FBx_CMD10 A4 A4

<27> FBC_ODT_L ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBC_CS0#_L L2 A8 FBC_CS0#_L L2 A8
<27> FBC_CS0#_L CS/CS0 VDDQ CS/CS0 VDDQ
FBC_RAS# J3 C1 FBC_RAS# J3 C1 FBx_CMD11 A1 A1
<27,31> FBC_RAS# RAS VDDQ RAS VDDQ
FBC_CAS# K3 C9 FBC_CAS# K3 C9
<27,31> FBC_CAS# CAS VDDQ CAS VDDQ
FBC_WE# L3 D2 FBC_WE# L3 D2 FBx_CMD12 BA0 BA0
<27,31> FBC_WE# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 FBx_CMD13 WE# WE#
FBC_DQS0 F3 H2 FBC_DQS2 F3 H2 FBC_ODT_L
FBC_DQS3 DQSL VDDQ FBC_DQS1 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 FBx_CMD14 A15 A15
FBC_CKE_L FBx_CMD15 CAS# CAS#
FBC_DQM0 E7 A9 FBC_DQM2 E7 A9
FBC_DQM3 DML VSS FBC_DQM1 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 FBx_CMD16 CS0#_H
VSS E1 VSS E1
1
G8 G8 RV117 RV116 FBx_CMD17
FBC_DQS#0 G3 VSS FBC_DQS#2 G3 VSS 10K_0402_5% 10K_0402_5%
DQSL VSS J2 DQSL VSS J2
FBC_DQS#3 B7 J8 FBC_DQS#1 B7 J8 FBx_CMD18 ODT_H
DQSU VSS DQSU VSS
VSS M1 VSS M1
M9 M9 FBx_CMD19 CKE_H
2
VSS VSS
VSS P1 VSS P1
FBC_RST# T2 P9 FBC_RST# T2 P9 FBx_CMD20 A13 A13
<27,31> FBC_RST# RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 FBx_CMD21 A8 A8
B B
FBx_CMD22 A6 A6
1
1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
1
RV91 RV90 L1 B9 RV88 L1 B9 FBx_CMD23 A11 A11

10K_0402_5% NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
E2 E2
2
VSSQ 2 VSSQ
E8 E8 FBx_CMD25 A3 A3
2
VSSQ VSSQ
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 FBx_CMD26 BA2 BA2
VSSQ G9 VSSQ G9
FBx_CMD27 BA1 BA1
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD28 A12 A12
X76@ X76@ FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
+1.5VS_VGA UV7 SIDE +1.5VS_VGA UV8 SIDE
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
@ CV191
@ CV183
CV199
CV189
CV205
@ CV188
@ CV190
CV206
@ CV181
CV182
@ CV185
@ CV194
CV192
CV203
CV195
CV184
CV197
CV186
CV187
CV198
CV200
CV201
CV204
CV193
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A

N13X-VRAM C Lower
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
Memory Partition C - Upper 32 bits FBC_D[0..63] <27,30>
FBC_MA[15..0] <27,30>
FBC_BA[2..0] <27,30>
UV9 UV10
+1.5VS_VGA FBC_DQM[7..0] <27,30>

+FBB_VREF1 M8 E3 FBC_D39 +FBB_VREF1 M8 E3 FBC_D60
VREFCA DQL0 FBC_D33 VREFCA DQL0 FBC_D57
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 FBC_DQS[7..0] <27,30>
D F2 FBC_D38 F2 FBC_D63 D
DQL2 DQL2
1 FBC_MA0 N3 A0 DQL3 F8 FBC_D32 FBC_MA0 N3 A0 DQL3 F8 FBC_D58
FBC_DQS#[7..0] <27,30>
RV120 FBC_MA1 P7 H3 FBC_D36 Group4 (IN1) FBC_MA1 P7 H3 FBC_D61 Group7 (IN3)
FBC_MA2 A1 DQL4 FBC_D35 FBC_MA2 A1 DQL4 FBC_D56
P3 A2 DQL5 H8 P3 A2 DQL5 H8
1.1K_0402_1% FBC_MA3 N2 G2 FBC_D37 FBC_MA3 N2 G2 FBC_D62
FBC_MA4 A3 DQL6 FBC_D34 FBC_MA4 A3 DQL6 FBC_D59
P8 H7 P8 H7
CMD mapping mod Mode D
2
+FBB_VREF1 FBC_MA5 A4 DQL7 FBC_MA5 A4 DQL7

P2 A5 P2 A5
FBC_MA6 R8 FBC_MA6 R8
A6 A6
1
CV229
FBC_MA7 R2 D7 FBC_D47 FBC_MA7 R2 D7 FBC_D54 DATA Bus
0.01U_0402_25V7K
1 A7 DQU0 A7 DQU0
RV127 FBC_MA8 T8 C3 FBC_D43 FBC_MA8 T8 C3 FBC_D51
FBC_MA9 A8 DQU1 FBC_D46 FBC_MA9 A8 DQU1 FBC_D55 Address
R3 A9 DQU2 C8 R3 A9 DQU2 C8 0..31 32..63
1.1K_0402_1% FBC_MA10 L7 C2 FBC_D42 FBC_MA10 L7 C2 FBC_D49
2 FBC_MA11 A10/AP DQU3 FBC_D40 FBC_MA11 A10/AP DQU3 FBC_D52
R7 A7 Group5 (TOP) R7 A7 Group6 (BOT) FBx_CMD0 CS0#_L
2

N7 A12 DQU5 A2 N7 A12 DQU5 A2
FBC_MA13 T3 B8 FBC_D44 FBC_MA13 T3 B8 FBC_D53 FBx_CMD1
T7 A14 DQU7 A3 T7 A14 DQU7 A3
FBC_MA15 M7 FBC_MA15 M7 FBx_CMD2 ODT_L
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA
FBx_CMD3 CKE_L
FBC_BA0 M2 B2 FBC_BA0 M2 B2
FBC_BA1 BA0 VDD FBC_BA1 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 FBx_CMD4 A14 A14
FBC_BA2 M3 G7 FBC_BA2 M3 G7
FBC_CLK1 BA2 VDD BA2 VDD
VDD K2 VDD K2 FBx_CMD5 RST RST
VDD K8 VDD K8
VDD N1 VDD N1 FBx_CMD6 A9 A9
2
FBC_CLK1 J7 N9 FBC_CLK1 J7 N9
<27> FBC_CLK1 CK VDD CK VDD
RV129 FBC_CLK1# K7 R1 FBC_CLK1# K7 R1 FBx_CMD7 A7 A7
<27> FBC_CLK1# CK VDD CK VDD
C 160_0402_1% FBC_CKE_H K9 R9 FBC_CKE_H K9 R9 C
<27> FBC_CKE_H CKE/CKE0 VDD CKE/CKE0 VDD
FBx_CMD8 A2 A2
1
FBC_ODT_H K1 A1 FBC_ODT_H K1 A1 FBx_CMD9 A0 A0

<27> FBC_ODT_H ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBC_CLK1# FBC_CS0#_H L2 A8 FBC_CS0#_H L2 A8
<27> FBC_CS0#_H CS/CS0 VDDQ CS/CS0 VDDQ
FBC_RAS# J3 C1 FBC_RAS# J3 C1 FBx_CMD10 A4 A4
<27,30> FBC_RAS# RAS VDDQ RAS VDDQ
FBC_CAS# K3 C9 FBC_CAS# K3 C9
<27,30> FBC_CAS# CAS VDDQ CAS VDDQ
FBC_WE# L3 D2 FBC_WE# L3 D2 FBx_CMD11 A1 A1
<27,30> FBC_WE# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 FBx_CMD12 BA0 BA0
FBC_DQS4 F3 H2 FBC_DQS7 F3 H2
FBC_DQS5 DQSL VDDQ FBC_DQS6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 FBx_CMD13 WE# WE#
FBx_CMD14 A15 A15
FBC_DQM4 E7 A9 FBC_DQM7 E7 A9
FBC_DQM5 DML VSS FBC_DQM6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 FBx_CMD15 CAS# CAS#
VSS E1 VSS E1
VSS G8 VSS G8 FBx_CMD16 CS0#_H
FBC_DQS#4 G3 J2 FBC_DQS#7 G3 J2
FBC_DQS#5 B7 DQSL VSS FBC_DQS#6 B7 DQSL VSS
DQSU VSS J8 DQSU VSS J8 FBx_CMD17
FBC_ODT_H M1 M1
VSS VSS
VSS M9 VSS M9 FBx_CMD18 ODT_H
VSS P1 VSS P1
FBC_CKE_H FBC_RST# T2 P9 FBC_RST# T2 P9 FBx_CMD19 CKE_H
<27,30> FBC_RST# RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 FBx_CMD20 A13 A13
1
RV118 RV119
B 10K_0402_5% 10K_0402_5% FBx_CMD21 A8 A8 B
1
1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
RV123 L1 B9 RV128 L1 B9 FBx_CMD22 A6 A6
NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 D1 243_0402_1% J9 D1
2
NC/CE1 VSSQ NC/CE1 VSSQ

E2 E2
2
2
VSSQ VSSQ
VSSQ E8 VSSQ E8 FBx_CMD24 A5 A5
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 FBx_CMD25 A3 A3
VSSQ G9 VSSQ G9
FBx_CMD26 BA2 BA2
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD27 BA1 BA1
X76@ X76@ FBx_CMD28 A12 A12
FBx_CMD29 A10 A10
+1.5VS_VGA UV9 SIDE +1.5VS_VGA UV10 SIDE FBx_CMD30 RAS# RAS#
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CV209
@ CV227
CV213
CV233
CV226
CV207
@ CV230
CV220
CV221
@ CV228
CV225
CV210
@ CV208
CV223
@ CV211
@ CV222
CV212
@ CV231
CV224
CV214
CV215
CV217
CV218
CV232
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A

N13X-VRAM C Upper
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
+3VS_VGA Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
2
R02
RV92 X76@ RV93 X76@ RV94 X76@ RV121 X76@ RV122 X76@ ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
45.3K_0402_1% 45.3K_0402_1% 10K_0402_1% 20K_0402_1% 20K_0402_1%
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
1
STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
<24> STRAP0 STRAP0
D <24> STRAP1 STRAP1 STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0] D
<24> STRAP2 STRAP2
<24> STRAP3 STRAP3 STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
<24> STRAP4 STRAP4
STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
2 CHANGE_GEN3
2
R02
RV95 X76@ RV96 X76@ RV97 X76@ RV124 X76@ RV125 X76@
45.3K_0402_1% 45.3K_0402_1% 10K_0402_1% 4.99K_0402_1% 10K_0402_1% Pull-up to
Resistor Values +3VS_VGA Pull-down to Gnd
1
1
5K 1000 0000
ZZZ ZZZ
10K 1001 0001
RV96 X76@ 15K 1010 0010
20K 1011 0011
Samsung Samsung
S2GP@ S1GM@ 25K 1100 0100
X7634138L01 X7634138L05
34.8K_0402_1% 30K 1101 0101
SD034348280 ZZZ ZZZ
+3VS_VGA
35K 1110 0110
45K 1111 0111
Hynix Hynix
C H2GP@ H1GM@ C
2
X7634138L02 X7634138L06
2
RV98
4.99K_0402_1% RV99 X76@ RV100 X76@ ZZZ ZZZ
X76@ 30K_0402_1% 4.99K_0402_1%
1
SUB_VENDOR 3GIO_PADCFG XCLK_417

1
<24> ROM_SI ROM_SI

<24> ROM_SO ROM_SO
<24> ROM_SCLK ROM_SCLK Samsung Samsung 0 No VBIOS ROM 3GIO_PADCFG[3:0] 0 277MHz (Default)
S1GP@ S512M@
X7634138L03 X7634138L07
2
1 BIOS ROM is present (Default) 0110 Notebook Default 1 Reserved

2
RV101 ZZZ ZZZ

X76 20K_0402_1% RV102 RV103 X76@ RV103 X76@
X76@ 30K_0402_1%
X76@
15K_0402_1% FB_0_BAR_SIZE SLOT_CLK_CFG
1
0 Reserved 0 GPU and MCH don't share a common reference clock

Hynix Hynix
4.99K_0402_1% H1GP@ H512M@
SD034499180 X7634138L04 X7634138L08 1 Reserved 1 GPU and MCH share a common reference clock (Default)
2 256MB (Default) SMBUS_ALT_ADDR VGA_DEVICE

For N13P-GL strap table X76
3 Reserved 0 0x9E (Default) 0 3D Device (Class Code 302h)
GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
B B
128M* 16* 8 Samsung (2Gb) R R R R R R 1 0x9C (Multi-GPU usage) 1 VGA Device (Default)
N13P-GL 900 MHz 2GB K4W2G1646C-HC11 PU 45K PD 45K PU 10K n/a n/a PD 45K PD 10K PD 15K
USER Straps
128M* 16* 8 Hynix (2Gb) R R R R R R
N13P-GL 900 MHz 2GB H5TQ1G63DFR-11C PU 45K PD 45K PU 10K n/a n/a PD 35K PD 10K PD 15K User[3:0]
64M* 16* 8 Samsung (1Gb) R R R R R R
N13P-GL 900 MHz 1GB K4W1G1646G-BC11 PU 45K PD 45K PU 10K n/a n/a PD 20K PD 10K PD 15K
64M* 16* 8 Hynix (1Gb) R R R R R R 1000-1100 Customer defined
N13P-GL 900 MHz 1GB H5TQ1G63DFR-11C PU 45K PD 45K PU 10K n/a n/a PD 15K PD 10K PD 15K
PEX_PLL_EN_TERM
0 Disable (Default)
For N13M-GE strap table 1 Enable
GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
N13M-GE 128M* 16* 4 Samsung (2Gb) R R R R R R R R PCIE_MAX_SPEED

900 MHz 1GB K4W2G1646C-HC11 PU 10K PD 10K PU 10K PD 10K PD 10K PD 10K PD 10K PD 10K
N13M-GE 128M* 16* 4 Hynix (2Gb) R R R R R R R R 0 Limit to PCIE Gen1
900 MHz 1GB H5TQ1G63DFR-11C PD 10K PU 10K PU 10K PD 10K PD 10K PD 10K PD 10K PD 10K
N13M-GE 64M* 16* 4 Samsung (1Gb) R R R R R R R R
900 MHz 512MB K4W1G1646G-BC11 PU 10K PU 10K PD 10K PD 10K PD 10K PD 10K PD 10K PD 10K 1 PCIE Gen 2/3 Capable
N13M-GE 64M* 16* 4 Hynix (1Gb) R R R R R R R R
900 MHz 512MB H5TQ1G63DFR-11C PD 10K PD 10K PU 10K PD 10K PD 10K PD 10K PD 10K PD 10K
A A

N13X_MISC
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
LCD POWER CIRCUIT CMOS Camera

+LCDVDD +5VALW +3VS
+3VS
W=60mils
(20 MIL)
1 CMOS@ +3VS_CMOS
Q83
1
R400 R401 C513
D 150_0603_1% 100K_0402_5% 4.7U_0805_10V4Z PMV65XP_SOT23-3~D D
+3VALW CMOS@ (20 MIL)
2
D
3 1 2 1 10U
R403 1 R296 1
2
1
3
D 220K_0402_5%
S
CMOS@ 0_0603_5%
G 1
Q80 C518 C519 @
G
2 1 2 2
2
Q79 G PMV65XP_SOT23-3~D C542 @ 0.1U_0402_16V4Z R02 10U_0603_6.3V6M
2N7002_SOT23 S R435CMOS@ 0.1U_0402_16V4Z 2 2
1
D
W=60mils
1
1
C515 150K_0402_5% 2
0.1U_0402_16V4Z 4.7V
OUT
<42> CMOS_ON#
2 +LCDVDD +LCDVDD_CONN
L29 1
<17> PCH_ENVDD 2 R296 for CMOS shake issue reserve
IN C520 CMOS@
1 2
GND
0.1U_0402_16V4Z
Q81 DTC124EK FBMA-L11-201209-221LMA30T_0805 2
1
DTC124EKAT146_SC59-3 1 1
3
C516 C517
@ R408
100K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2
2
VGA LCD/PANEL BD. Conn.

C C
+LEDVDD B+
1 R813 2
1 1 0_0805_5%
C539
680P_0402_50V7K C541
@ 4.7U_0805_25V6-K
+3VS 2 2
JLVDS1
1 1
2 2 G1 31
1
3 3 G2 32
1 @ 2 R717 R433 @ 4 33
4 G3
5 5 G4 34
0_0402_5% 4.7K_0402_5% 6
DISPOFF# 6
7
2
BKOFF# DISPOFF# R430 1 INVT_PWM 7

<42> BKOFF# 1 2 <17> PCH_PWM 2 0_0402_5% 8 8
9 9
D4 @ 10
<17> LVDS_ACLK 10
1
CH751H-40PT_SOD323-2 <42> EC_INVT_PWM R431 1 @ 2 0_0402_5% 11

<17> LVDS_ACLK# 11
R716 12 12
B 10K_0402_5% <17> LVDS_A2 13 13
B
<17> LVDS_A2# 14 14
<17> LVDS_A1 15
2
15
<17> LVDS_A1# 16 16
<17> LVDS_A0 17 17
<17> LVDS_A0# 18 18
<17> PCH_ENBKL 1 2 @ ENBKL <42> <17> EDID_DATA 19 19
<17> EDID_CLK 20 20
R538 0_0402_5% +3VS 21
R02 21
1 +LCDVDD_CONN 22 22
(60 MIL) 23 23
2
680P_0402_50V7K +3VS 24
R438 C540@ 24
25 25
100K_0402_1% 2
+3VS_CMOS 26 26
<18> USB20_P5 USB20_P5 27
USB20_N5 27
<18> USB20_N5 28
1
28
CMOS 29 29
30 30
ACES_88341-3001 ME@
A A

LVDS/CAMERA
Custom 0.2
LA-7981P
5 4 3 2 1
A B C D E
+5VS +5VS +5VS
3 3 3
1 BLUE 1 GREEN 1 RED
2 2 2
@ @ @
D5 D6 D7
BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3
1 1
+5VS
D10
+CRT_VCC
CRT Connector
F1
2 1 1 2 +CRT_VCC_F
1
RB491D_SC59-3
FCM1608CF-121T03 0603 1.1A_6V_SMD1812P110TF C521
1 2 RED
<17> DAC_RED
L30 W=40mils 2
0.1U_0402_16V4Z
FCM1608CF-121T03 0603
1 2 GREEN
<17> DAC_GRN
L31
FCM1608CF-121T03 0603 CONTE_80431-5K1-152
1 2 BLUE
<17> DAC_BLU
C522
C523
C524
C525
C526
C527
L32 JCRT1 ME@
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
1
1
1 1 1 1 1 1 6
PAD T66 NC11 11
R445 R443 R446 RED 1
150_0402_1% 150_0402_1% 150_0402_1% 7
2 2 2 2 2 2 CRT_DDC_DAT_CONN 12
2
2
GREEN 2
8 16
CLOSE TO CONN JVGA_HS 13
G
17
BLUE G
3
9
JVGA_VS 14
1
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
4
R437
R436
R434
R432
2 10 2
+CRT_VCC CRT_DDC_CLK_CONN 15
R448
5
1 2 1
2
1 C528
C529 1K_0402_5% 100P_0402_50V8J

2
0.1U_0402_16V4Z
2
EMI Request
5
FCM1608CF-121T03 0603
OE#
P
2 4 CRT_HSYNC_1 1 2 JVGA_HS
<17> CRT_HSYNC A Y L33
G
U23
SN74AHCT1G125DCKR_SC70-5 1
3
@
D8
C530 @
10P_0402_50V8J JVGA_VS 3 6 JVGA_HS
+CRT_VCC 2 I/O2 I/O4
R451
1 2
1 2 GND VDD 5 +5VS
C531 1K_0402_5%
0.1U_0402_16V4Z
2 CRT_DDC_CLK_CONN CRT_DDC_DAT_CONN
1 I/O1 I/O3 4
5
FCM1608CF-121T03 0603
OE#
P
CRT_VSYNC_1 JVGA_VS AZC099-04S.R7G_SOT23-6

<17> CRT_VSYNC 2 A Y 4 1 2
3 L34 3
G
U24 1
SN74AHCT1G125DCKR_SC70-5
3
@ C532
10P_0402_50V8J
2
+CRT_VCC
+3VS
1
Pull high at chipset/VGA side R456 R457

5
2.2K_0402_5% 2.2K_0402_5%
2
<17> CRT_DDC_DATA 4 3 CRT_DDC_DAT_CONN
2N7002DW -T/R7_SOT363-6
2
Q62B
<17> CRT_DDC_CLK 1 6 CRT_DDC_CLK_CONN

1 1
4
2N7002DW -T/R7_SOT363-6 @ @ 4
Q62A C533 C534
100P_0402_50V8J 68P_0402_50V8K
2 2

CRT Connector
Custom 0.2
LA-7981P
A B C D E
5 4 3 2 1
+5VS
W=40mils +5VS_HDMI
+5VS RB491D_SC59-3 F2 HDMI@
+3VS D13 HDMI@ 1.1A_6VDC_FUSE
2 1+HDMI_5V 1 2 +5VS_HDMI
2
1
2
R482 @ C543
D R485 0_0805_5% HDMI@ D
1M_0402_5% Q93 D14 @ 0.1U_0402_16V4Z 2
HDMI@ HDMI@ BAT54S-7-F_SOT23-3
1
2
G
2N7002H_SOT23-3
1
TMDS_B_HPD# 3 1
<17> TMDS_B_HPD#
2
2
HDMI@ R483 R484 HDMI@
R488 2.2K_0402_5% 2.2K_0402_5%
20K_0402_5%
1
HDMI@
JHDMI1ME@
1
HDMI_DET 19 HP_DET
+5VS_HDMI 18 +5V
17 DDC/CEC_GND
HDMIDAT_R 16
HDMICLK_R SDA
15 SCL
14 Reserved
13 CEC
<17> HDMI_CLK-_CK HDMI_CLK-_CK R465 1 @ 2 0_0402_5% HDMI_CLK-_CONN 12 20
CK- G1
<17> HDMI_CLK+_CK 11 CK_shield G2 21
C
HDMI_CLK+_CKR464 1 @ 2 0_0402_5% HDMI_CLK+_CONN 10 22 C
HDMI_TX0-_CK R467 1 @ HDMI_TX0-_CONN CK+ G3
<17> HDMI_TX0-_CK 2 0_0402_5% 9 D0- G4 23
+3VS 8
<17> HDMI_TX0+_CK D0_shield
HDMI_TX0+_CK R466 1 @ 2 0_0402_5% HDMI_TX0+_CONN 7
HDMI_TX1-_CK R469 1 @ HDMI_TX1-_CONN D0+
<17> HDMI_TX1-_CK 2 0_0402_5% 6 D1-
<17> HDMI_TX1+_CK 5 D1_shield
2
HDMI_TX1+_CK R468 1 @ 2 0_0402_5% HDMI_TX1+_CONN 4

R783 HDMI_TX2-_CK R471 1 @ HDMI_TX2-_CONN D1+
<17> HDMI_TX2-_CK 2 0_0402_5% 3 D2-
0_0402_5% <17> HDMI_TX2+_CK 2 D2_shield
@ HDMI_TX2+_CK R470 1 @ 2 0_0402_5% HDMI_TX2+_CONN 1 D2+
1
SUYIN_100042GR019M23DZL
Pull up R for PCH OR VGA SIDE
Q63A
HDMI@ L35 HDMI@
2
2N7002DW-T/R7_SOT363-6 HDMI_CLK+_CK 1 2 HDMI_CLK+_CONN

1 2 C982 1 2 0.1U_0402_16V4Z @
1 6 HDMICLK_R 680 +-5% 8P4R
<17> HDMICLK_NB
HDMI_CLK-_CK 4 3 HDMI_CLK-_CONN HDMI_CLK-_CONN 5 4
4 3
5
C983 1 2 0.1U_0402_16V4Z @ HDMI_CLK+_CONN 6 3

WCM-2012HS-900T HDMI_TX1-_CONN 7 2
B <17> HDMIDAT_NB 4 3 HDMIDAT_R HDMI_TX1+_CONN 8 1 SD309680080 B
L36 HDMI@
Q63B HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN RP5 HDMI@ S ROW RES 1/16W 680 +-5% 8P4R
HDMI@ 1 2 C984 1 2 0.1U_0402_16V4Z @
2N7002DW-T/R7_SOT363-6 680 +-5% 8P4R
HDMI_TX0-_CK 4 3 HDMI_TX0-_CONN HDMI_TX0-_CONN 5 4
4 3 C985 1 HDMI_TX0+_CONN
2 0.1U_0402_16V4Z @ 6 3
WCM-2012HS-900T HDMI_TX2-_CONN 7 2
HDMI_TX2+_CONN 8 1
HDMIDAT_R L37 HDMI@ +3VS
HDMI_TX1+_CK 1 2 HDMI_TX1+_CONN RP6 HDMI@
1 2
1
C986 1 D
2 0.1U_0402_16V4Z @
HDMICLK_R 2
HDMI_TX1-_CK 4 3 HDMI_TX1-_CONN G
4 3 C987 1 2 0.1U_0402_16V4Z @ S Q95
3
WCM-2012HS-900T HDMI@
3
2N7002H_SOT23-3
D11 @ L38 HDMI@
PJDLC05_SOT23-3 HDMI_TX2+_CK 1 2 HDMI_TX2+_CONN
1 2 C988 1 2 0.1U_0402_16V4Z @
HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN
4 3 C989 1 2 0.1U_0402_16V4Z @
WCM-2012HS-900T
A A
1
Security Classification Compal Secret Data Compal Electronics,Ltd.

HDMI CONN
B 0.2
LA-7981P
5 4 3 2 1
A B C D E
Mini-Express Card for WLAN/WiMAX(Half)
1 1
+3VS_WLAN +3VALW +1.5VS_CONN
+3VS 80mil +3VS_WLAN

J6 1 1 1 1
@
C548@ C547
Mini-Express Card(WLAN/WiMAX)
@
1 2 4.7U_0603_6.3V6K 0.1U_0402_16V4Z C544 C545 @
1 2 +1.5VS 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2
JUMP_43X79
0_0402_5% JWLN1
<16,37,45> PCIE_WAKE# PCIE_WAKE#1 @ 2 R514 1 2
R02 BT_ACTIVE 1 R497 WAKE# 3.3V
<40> BT_ACTIVE 2 @ 0_0402_5% 3 NC GND 4
1 @ 2 BT_DISABLE_R 5 6 +1.5VS_CONN
<19,40> PCH_BT_ON# NC 1.5V
R892 0_0402_5% <15> CLKREQ_WLAN# 7 8 LPC_FRAME#_R
CLKREQ# NC LPC_AD3_R
<19> BT_DISABLE 1 2 9 GND NC 10
R897 0_0402_5% 11 12 LPC_AD2_R
<15> CLK_PCIE_WLAN1# REFCLK- NC
13 14 LPC_AD1_R
<15> CLK_PCIE_WLAN1 REFCLK+ NC
15 16 LPC_AD0_R
PCI_RST#_R GND NC
17 NC GND 18
CLK_PCI_DB 19 20 @1 R498 R02
2 0_0402_5%
NC NC PCH_WL_OFF# <18>
21 GND PERST# 22 PLT_RST# <18,23,37,42,45>
2 <15> PCIE_PRX_DTX_N2 23 PERn0 +3.3Vaux 24 1 R499 2 @ 0_0402_5% +3VALW 2
25 26 @1 R500 2 0_0402_5% +3VS
<15> PCIE_PRX_DTX_P2 PERp0 GND R02
27 GND +1.5V 28
29 GND SMB_CLK 30 1 R501 2 @ 0_0402_5% SMB_CLK_S3 <12,13,15>
<15> PCIE_PTX_C_DRX_N2 31 PETn0 SMB_DATA 32 1 R502 2 @ 0_0402_5% SMB_DATA_S3 <12,13,15>
<15> PCIE_PTX_C_DRX_P2 33 PETp0 GND 34
35 GND USB_D- 36 USB20_N10 <18>
+3VS_WLAN 37 38
NC USB_D+ USB20_P10 <18>
39 NC GND 40
41 42 R503 2 @ 1 0_0402_5%
NC LED_WWAN# R504 2 @ WLAN_LED#
43 NC LED_WLAN# 44 1 0_0402_5% NC
100_0402_1% 45 46
R505 NC LED_WPAN#
47 NC +1.5V 48
<42,43> EC_TX 1 2 49 NC GND 50
<42,43> EC_RX 1 2 51 NC +3.3V 52
R506
100_0402_1% 53 54
GND GND
TAITW_PFPET0-AFGLBG1ZZ4N0
2
For EC to detect ME@
R507
debug card insert. 100K_0402_5%
3 3
Reserve for SW mini-pcie debug card.

Series resistors closed to KBC side.
LPC_FRAME#_R R508 1 @ 2 0_0402_5% LPC_FRAME#
LPC_FRAME# <14,42>
LPC_AD3_R R509 1 @ 2 0_0402_5% LPC_AD3
LPC_AD3 <14,42>
LPC_AD2_R R510 1 @ 2 0_0402_5% LPC_AD2
LPC_AD2 <14,42>
LPC_AD1_R R511 1 @ 2 0_0402_5% LPC_AD1
LPC_AD1 <14,42>
LPC_AD0_R R512 1 @ 2 0_0402_5% LPC_AD0
LPC_AD0 <14,42>
PCI_RST#_R R513 1 @ 2 0_0402_5% PLT_RST#
CLK_PCI_DB CLK_PCI_DB <18>
4 4

Mini-Card/NEW Card/SIM
0.2
LA-7981P
A B C D E
5 4 3 2 1
+3VALW +3V_LAN
Layout Notice : Place as close +LX

chip as possible. J18 Close together
@
1 2 L77 L78 SWR@
1 2 R1357 L74 SWR@
+1.1_DVDDL
1 2 +LX_R 1 2 +LX FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P
JUMP_43X79
1000P_0402_50V7K
10U_0603_6.3V6M
4.7UH_SIA4012-4R7M_20% +1.1_AVDDL_L +1.1_AVDDL +1.1_DVDDL
0.1U_0402_16V4Z
1 2 1 2
@ C935
C936
0_0402_5%
0.1U_0402_16V4Z
1U_0402_6.3V4Z
4.7U_0603_6.3V6K
D 1 1 D
C967
C980
C317
S
D
3 1 1 1 1
2 2
Note: Place Close to LAN chip
C937
R176
Q105
L39 DCR< 0.15 ohm
G
2
LAN_PWR_ON# 2 1 PMV65XP_SOT23-3~D Rate current > 1A 2 2 2
<42> LAN_PWR_ON#
2
10U
10K_0402_5% C976
0.1U_0402_16V7K
1 Place close to Pin34
Close to
Pin40
Vendor recommand reseve the

PU resistor close LAN chip
R525 1 2 4.7K_0402_5% U41 8162@ +3V_LAN

+3V_LAN
@ R1367
<18,23,36,42,45> PLT_RST#
PLT_RST# SA000050E00_S IC AR8161-AL3A-R QFN 40P E-LAN CTRL +AVDDH_AVDD3.3 1 2
SA000052J10_S IC AR8162-AL3A-R QFN 40P E-LAN CTRL 0_0402_5%
AR8162-AL3A-R
0.1U_0402_16V4Z
1U_0402_6.3V4Z
H --> Overclocking mode
C948
C949
L --> Not overclocking mode 1 1
C C
U41 GIGA@
Overclocking mode stick
Place Close to Chip 2 2
C946 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N1 29 38 ACTIVITY
<15> PCIE_PRX_DTX_N1 TX_N LED_0 ACTIVITY <38>
LAN_LINK#
C947 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P1 30
Atheros LED_1 39
23
LAN_LINK# <38>
<15> PCIE_PRX_DTX_P1 TX_P LED_2
AR8151/AR8161 2 R65 R02 1 Place close to Pin16
36 LDO@ 10K_0402_5%
<15> PCIE_PTX_C_DRX_N1 RX_N
12 MDI0-
TRXN0 MDI0- <38>
35 11 MDI0+
<15> PCIE_PTX_C_DRX_P1 RX_P TRXP0 MDI0+ <38>
15 MDI1-
TRXN1 MDI1- <38>
32 14 MDI1+
<15> CLK_PCIE_LAN# REFCLK_N TRXP1 MDI1+ <38>
33 18 MDI2-
<15> CLK_PCIE_LAN REFCLK_P TRXN2 MDI2- <38>
17 MDI2+
TRXP2 MDI2+ <38>
PLT_RST# 2 21 MDI3-
PERST# TRXN3 MDI3- <38>
@ MDI3+
R1369 1 2 0_0402_5% PCIE_WAKE#_R 3
TRXP3 20 MDI3+ <38> Place Close to PIN1
<16,36,45> PCIE_WAKE# W AKE#
<42> LAN_WAKE# R1370 1 @ 2 0_0402_5%
25 10 LAN_RBIAS 1 2 +3V_LAN
R521 1 SMCLK RBIAS
+3V_LAN 2 4.7K_0402_5% 26 SMDATA
R1371 2.37K_0402_1%
Place Close to PIN1
@ 28 1 +3V_LAN
NC VDD33
C950
C951
C952
C953
C954
1000P_0402_50V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V4Z
1U_0402_6.3V4Z
Vendor recommand reseve the 27 TESTMODE 1 1 1 1
2
PU resistor close LAN chip +LX
LX 40 +LX
LAN_XTALO 7 @ @
1
@ LAN_XTALI XTLO R1372 30K_0402_5% 2 2 2 2
8 XTLI
R520 1 2 4.7K_0402_5% 5 +1.7_VDDCT 1 2
+3V_LAN VDDCT/ISOLAN +3VS
B B
<15> CLKREQ_LAN# 4 CLKREQ#
DVDDL/PPS 24
37 +1.1_DVDDL 10U
+1.1_AVDDL DVDDL_REG/DVDDL
13 AVDDL
+1.1_AVDDL 19 +2.7_AVDDH
+1.1_AVDDL AVDDL +AVDDH_AVDD3.3
31 AVDDL AVDDH/AVDD33 16
+1.1_AVDDL_L 34 22 +2.7_AVDDH
+1.1_AVDDL AVDDL AVDDH +2.7_AVDDH
6 AVDDL_REG/AVDDL AVDDH_REG 9
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
C956
C957
C958
C959
C960
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 1 C961
C962
C963
C964
C965
41 GND 1 1 1 1 1
2 2 2 2 2 AR8161-AL3A-R_QFN40_5X5
2 2 2 2 2
Near
Near Near Near Near Pin9 Near Near
Pin13 Pin19 Pin31 Pin6 Pin22 Pin37
LAN_XTALI
Y6 LAN_XTALO
A 4 NC OSC 3 A
1 OSC NC 2
3.3V : Enable switching regulator 1 25MHZ_10PF_7V25000014 1

0V : Disable switching regulator C968 C969
15P_0402_50V8J 15P_0402_50V8J
2 2 2011/06/15 2012/07/11 Title
LAN-AR8151/8161
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
MDI3+
T2
8162@
MDI3- @
2
C970 MDI3+ 1 16 MDO3+ 1 R304 2 0_0402_5%
R02
<37> MDI3+ TD+ TX+
0.1U_0402_16V4Z MDI3- 2 15 MDO3- 1 R305 2 0_0402_5%
<37> MDI3- TD- TX-
3 14 MCT3 1 2
1 CT CT R1374 75_0603_5%
4 NC NC 13 8162@
10
5 NC NC 12
6
7
8
9
1 6 11 MCT2 8162@ 1 2
D MDI2+ CT CT MDO2+ D
7 10 1 R306 2 R1375 75_0603_5%
6
7
8
9
10
<37> MDI2+ RD+ RX+
11 C972 MDI2- 8 9 MDO2- 1 R307 2 R308 change to C 10P 50V 0603 Rev0.5
GND <37> MDI2- RD- RX-
@ 0.1U_0402_16V4Z 0_0402_5%
RCLAMP3304N.TCT_SLP2626P10-10 2
D69 @ 8162@ 0_0402_5%
5
4
3
2
1
S X'FORM_ HD-081-A LAN S CER CAP 10P 50V J NPO 0603
GIGA@ R308 C973
5
4
3
2
1
0_0603_5%
R02 2 1 1 2
MDI2- T1
10P_0603_50V
2
MDI2+ C974 MDI0+ 1 16 MDO0+
<37> MDI0+ TD+ TX+
@ 0.1U_0402_16V4Z MDI0- 2 15 MDO0-
<37> MDI0- TD- TX-
3 14 MCT0 1 R1376 2
1 CT CT 75_0603_5%
Place Close to T2 4 NC NC 13
MDI1- 5 12
NC NC MCT1
1 6 CT CT 11 1 R1377 2
MDI1+ 7 10 MDO1+ 75_0603_5%
<37> MDI1+ RD+ RX+
MDI1+ @ C975 MDI1- 8 9 MDO1-
<37> MDI1- RD- RX-
0.1U_0402_16V4Z
2
S X'FORM_ HD-081-A LAN For GDTx1
10
DL1- Mount
6
7
8
9
C DL2/DL3/DL4- NC C
6
7
8
9
10
R308- 75 ohm
11 GND R1374/R1375/R1376/R1377- 0 ohm
RCLAMP3304N.TCT_SLP2626P10-10
D68 @
5
4
3
2
1
LDO Mode: pop R1380;R596

5
4
3
2
1
SWR Mode: pop R1449;R1378 MCT3

MDI0-
JRJ1 MCT2
MDI0+ R1449 2 SWR@ 1 510_0402_5% 9 Green LED- MCT1
Place Close to T1
R1380 2 LDO@ 1 510_0402_5% 10
<37> LAN_LINK# Green LED+ MCT0
1 +3V_LAN R1378 2 SWR@ 1 0_0402_5% MDO0+ 1 PR1+
LSE-200NX3216TRLF_1206-2
LSE-200NX3216TRLF_1206-2
LSE-200NX3216TRLF_1206-2
LSE-200NX3216TRLF_1206-2
1
C978 @ MDO0- 2
470P_0402_50V7K R596 LDO@ PR1-
2
2 MDO1+
0_0402_5% 3 PR2+
DL1
DL2
DL3
DL4
MDO2+ 4
2
PR3+
B MDO2- 5 @ @ @ @ B
PR3-
1
MDO1- 6 PR2-
MDO3+ 7 14
PR4+ G2
Overclocking mode stick MDO3- 8 13
PR4- G1
ACTIVITY R1448 2 1 510_0402_5% 11
<37> ACTIVITY Yellow LED-
12 Yellow LED+
1 SANTA_130452-D ME@ Reserve for EMI go rural solution
@
C979 +3V_LAN
470P_0402_50V7K
2
A A

LAN_Transformer
B 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
SMSC thermal sensor

placed near by VRAM Close to DDR
+3VS REMOTE1+
D D
Close U27 1
1
C
1
REMOTE1+ @ C586 2 Q97
+3VS R540 100P_0402_50V8J B MMST3904-7-F_SOT323-3
1 2
10K_0402_5% E
3
C587 @ REMOTE1-
2200P_0402_50V7K U27
2
2 REMOTE1-
1 10 EC_SMB_CK2
VDD SMCLK EC_SMB_CK2 <15,23,42>
REMOTE1+ 2 9 EC_SMB_DA2
REMOTE2+ DP1 SMDATA EC_SMB_DA2 <15,23,42>
REMOTE2+
Under WWAN
2
1 REMOTE1- 3 8 1
DN1 ALERT#
1
C590 C
C588 @ 0.1U_0402_16V4Z REMOTE2+ 4 7 @ C589 2 Q98 @
2200P_0402_50V7K 1 DP2 THERM# 100P_0402_50V8J B MMST3904-7-F_SOT323-3
2 REMOTE2- REMOTE2- 5 6 2 E
3
DN2 GND REMOTE2-
EMC1403-2-AIZL-TR_MSOP10
REMOTE1,2+/-:
C Address 1001_101xb Trace width/space:10/10 mil
C
Trace length:<8"
CPU VGA_L VGA_R

H1 H2 H3
HOLEA HOLEA HOLEA H4 H5
HOLEA HOLEA FD1 FD2 FD3 FD4
1
H_3P8 H_3P8 H_3P8
H_3P3 H_3P3
A B
B FAN1 Conn M/B 橢橢橢 M/B 橢橢 B
H6 H7 H8 H9 H10 H11 H12 H13 H14 L R H17

+5VS HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA H15 H16 HOLEA
HOLEA HOLEA
R581 JFAN1
2 1 1
1
1
1
<42> EC_TACH 2
1
0_0603_5%<42> EC_FAN_PWM 2
3 3
4 4
@ H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_3P0X4P0N H_3P0X4P0N H_3P0N
2 5 G5
6 G6
C591
10U_0603_6.3V6M ACES_85205-04001 D
1 ME@
2P8 * 9 pcd E
10U
A A
Security Classification Compal Secret Data Compal Electronics,Ltd.

Fintek-Thermal IC/FAN/screw
B 0.2
LA-7981P
5 4 3 2 1
A B C D E F G H
BT MODULE CONN SATA HDD Conn.

JHDD1
1 GND
+3VALW SATA_ITX_DRX_P0 2
<14> SATA_ITX_DRX_P0 RX+
<14> SATA_ITX_DRX_N0 SATA_ITX_DRX_N0 3 RX-
4 GND
1 SATA_DTX_C_IRX_N0 C596 1 2 0.01U_0402_25V7K SATA_DTX_IRX_N0 5
C710 @ <14> SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 C597 1 TX-
<14> SATA_DTX_C_IRX_P0 2 0.01U_0402_25V7K SATA_DTX_IRX_P0 6 TX+
0.1U_0402_16V4Z 7 GND
2
1 1
R632 BT@ C709 BT@
100K_0402_5% 0.1U_0402_16V4Z
<19,36> PCH_BT_ON# 1 2 1 2 8 3.3V
+3VS 9 3.3V
+3VS_BT 10 3.3V
11 GND
+3VS R02 12
R583 GND
13 GND
0_0603_5% 30mils R550 0_0805_5% 14 5V
D
3 1 2 1 +5VS 1 2 +5V_HDD 15 5V
1 16 5V
0.1U_0402_16V4Z @ 17
Q104 C712 GND
G
18
2
PMV65XP_SOT23-3~D BT@ Reserved
19 GND
2 +5V_HDD 10U +3VS 20 23
JBT1 R02 12V GND
21 12V GND 24
1 1 22 12V
2 2 1 1 1 1 1
<18> USB20_P13 USB20_P13 3 @ SUYIN_127043FB022G278ZR
USB20_N13 3 C598 C599 C600 @ C602 C603
<18> USB20_N13 4 4
BTON_LED:NC 5 7 1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0603_6.3V6M 0.1U_0402_16V4Z
BT_ACTIVE 5 G1 2 2 2 2 2
<36> BT_ACTIVE 6 6 G2 8
ACES_87213-0600G
ME@
2
ODD Power Control 2
@ J9
1 1 2 2
+5V_ODD FOR 15"
+5VALW +5VS JUMP_43X79
SATA ODD FFC Conn.
JP2
S
3 1
1 1 1
1
Q99 @ <14> SATA_ITX_C_DRX_P2 SATA_ITX_C_DRX_P2 15@ C605 1 2 0.01U_0402_25V7K SATA_ITX_DRX_P2_15 2

R552 @ PMV65XP_SOT23-3~D C604 SATA_ITX_C_DRX_N2 15@ C606 1 2
2 0.01U_0402_25V7K SATA_ITX_DRX_N2_15
G
<14> SATA_ITX_C_DRX_N2 3
2
@ R568 10K_0402_5% 0.1U_0402_16V4Z 3

4 4
10K_0402_5% R675 @ 2 SATA_DTX_C_IRX_N2 15@ C618 1 2 0.01U_0402_25V7K SATA_DTX_IRX_N2_15 5
100K_0402_5% <14> SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 15@ C617 1 5
1 2 0.01U_0402_25V7K SATA_DTX_IRX_P2_15 6
2
<14> SATA_DTX_C_IRX_P2 ODD_DETECT# 6

1 2 1 2 7 7
C608 R710 @ 0_0402_5% +5V_ODD 8 8
1
1 10U_0603_6.3V6M 9
2 ODD_DA# 9
1 2 R554 R_ODD_DA# 10
OUT
C607 @ <18,42> ODD_DA# R02 10

0.01U_0402_25V7K 0_0402_5% 11
2 R555 2 @ GND
<19> ODD_EN 2 IN +3VS 1 12 GND
10K_0402_5%
GND
10U
Q100 @ ACES_87056-01001-001
DTC124EKAT146_SC59-3
3
ME@
3 Co-lay 3
FOR 14"
SATA ODD Conn.
JODD1 ME@
1 GND
SATA_ITX_C_DRX_P2 14@ C616 1 2 0.01U_0402_25V7K SATA_ITX_DRX_P2_14 2
SATA_ITX_C_DRX_N2 14@ C615 1 SATA_ITX_DRX_N2_14 RX+
2 0.01U_0402_25V7K 3 RX-
4 GND
SATA_DTX_C_IRX_N2 14@ C614 1 2 0.01U_0402_25V7K SATA_DTX_IRX_N2_14 5
SATA_DTX_C_IRX_P2 14@ C613 1 TX-
2 0.01U_0402_25V7K SATA_DTX_IRX_P2_14 6 TX+
7 GND
ODD_DETECT# 8
+5V_ODD DP
9 +5V
10 +5V
R_ODD_DA# 11
R02 MD
12 GND GND1 14
13 GND GND2 15
TYCO_2-1759838-8~D
4 4

HDD/ODD/BT Connector
Custom 0.2
LA-7981P
A B C D E F G H
5 4 3 2 1
CX20671
High Definition Audio Codec SoC
With Integrated Class-D Stereo
Amplifier.
An integrated 5 V to 3.3 V Low-dropout
voltage regulator (LDO).
An integrated 3.3 V to 1.8V Low-dropout
voltage regulator (LDO).
D D
+3VS
1
HDA_RST_AUDIO#
+3VS
HDA_SYNC_AUDIO
EMI R351 @
4.7K_0402_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
1 1 1 HDA_SDOUT_AUDIO
2
C579
C580
C581
+LDO_OUT_3.3V 1 R515 2 HDA_BITCLK_AUDIO HDA_RST_AUDIO#
+3VS 0_0402_5%
2 2 2
1
1U_0603_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
@
@ 1 1 1 1 AVDD_3.3 pinis output of 1 1 1 1 C641 @
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
C584
C585
C625
C592
1 1 internal LDO. NOT connect
C582
C583
C575
C576
C577
C578
100P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
to external supply. 2
2 2 2 2 2 2 2 2
@ 2 2 @ @ @ @
Layout Note:Path from +5VS to LPWR_5.0
RPWR_5.0 must be very low
resistance (<0.01 ohms)
R527 0_0402_5%
ESD Reserve
+3VS 1 2
1U_0603_10V4Z
0.1U_0402_16V4Z
+5VS
+3VALW 1R528 @ 2 0_0402_5% 1 1
C593
C623
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
+5VS
1 1 Sense resistors must be
C638
C631
10 mils connected same power
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@ 2 2
1 1 1 1 that is used for VAUX_3.3
C632
C594
C595
C628
@
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
2 2
1 1
C626
C634
@
2 2 2 2 R458 1 2 5.11K_0402_1% +3VS
C Port B C
0.1U_0402_16V4Z
2 2 SENSE_A R491 1 2 20K_0402_1% MIC_JD Port A
18
29
27
28
26
1
3
7
2
C620
U25 R494 1 2 39.2K_0402_1% PLUG_IN_R
FILT_1.8
VAUX_3.3
DVDD_3.3
FILT_1.65
AVDD_3.3
VDD_IO
AVDD_5V
AVDD_HP
Please bypass caps very close to device.
12 2
LPWR_5.0 +MICBIASB
15
HDA_RST_AUDIO# RPWR_5.0
<14> HDA_RST_AUDIO# 9 17
RESET# CLASS-D_REF R490 2K_0402_5% R700 4.7K_0402_5%
HDA_BITCLK_AUDIO 5 2 1 2 1
<14> HDA_BITCLK_AUDIO BIT_CLK
HDA_SYNC_AUDIO 8 36 SENSE_A R526 0_0402_5%
<14> HDA_SYNC_AUDIO SYNC SENSE_A
R495 1 2 33_0402_5% 6 1 2 2.2U_0603_6.3V4Z
<14> HDA_SDIN0
HDA_SDOUT_AUDIO 4
SDATA_IN R490 & R700 for App & Nokia combo ear phone un-pop
<14> HDA_SDOUT_AUDIO SDATA_OUT
35 C621 1 2 R517 100_0402_1% EXT_MIC
PORTB_R EXT_MIC <43>
34 C622 1 2
PORTB_L
PC_BEEP B_BIAS
33 +MICBIASB
2.2U_0603_6.3V4Z
External MIC
10
PC_BEEP
@
32 +MICBIASC
C_BIAS MIC_INR
31
PORTC_R MIC_INL
<43> CX_GPIO0
0_0402_5% 1 BBH@2 R519 CX_GPIO0 PORTC_L
30 Internal MIC
<42> EAPD 38
R496 2 GPIO0/EAPD#
<42> EC_MUTE# 1 0_0402_5% 37
GPIO1/SPK_MUTE# R481 39_0402_5%
23 1 2 HP_OUTR <43>
PORTA_R R493 39_0402_5%
EAPD active low PORTA_L
22 1 2 HP_OUTL <43> Headphone
0=power down ex AMP 40 Changed from 5.1ohm to 15ohm
DMIC_CLK
1=power up ex AMP 1
DMIC_1/2 NC
24 for "zi zi"noise.
25
NC
39
SPK_L2+ NC
11
SPK_L1- LEFT+
13
LEFT-
Internal SPEAKER AVEE
21
19
SPK_R2+ FLY_P
16 20 1 2
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
SPK_R1- RIGHT+ FLY_N C635 1U_0603_10V4Z
14 1 1
RIGHT-
C629
C609
Short GND and GNDA on
GND
B GND1 & GND2 on layout

2 2
Combo Jack detect (normal close) B
R516 @ CX20671-21Z_QFN40_6X6 MIC_JD

41
1 2
0_0402_5%
1
Q75 D 33K_0402_5%
LBSS138LT1G_SOT-23-3 2 R693 1 2 EXT_MIC
GND GNDA G
1
S
3
C787 +5VS PLUG_IN_R
1
1U_0402_6.3V6K
2
R724
PLUG_IN_R 10K_0402_5%
PC Beep
1
D
2
<43> PLUG_IN R723 2 Q85
R182 47K_0402_5% 20K_0402_5% G 2N7002_SOT23
EC Beep <42> BEEP# 1 2
C619 0.1U_0402_16V4Z CX_GPIO0 1 2 S
3
1 @
R492 C630
ICH Beep <14> HDA_SPKR 1 2PC_BEEP1 1 2 PC_BEEP @
C612 0.1U_0402_16V4Z 33_0402_5% 0.1U_0402_16V4Z
2
1
@
R480 Place colose to Codec chip
10K_0402_5%
2
+MICBIASC close to Codec JSPK1 ME@

SPK_R1- L41 1 FBMA-L11-160808-121LMT_0603
2 SPK_R1-_CONN 1
SPK_R2+ L42 FBMA-L11-160808-121LMT_0603 SPK_R2+_CONN 1
1 2 2
1
SPK_L1- L43 FBMA-L11-160808-121LMT_0603 SPK_L1-_CONN 2

1 2 3
R518 SPK_L2+ L46 FBMA-L11-160808-121LMT_0603 SPK_L2+_CONN 3
1 2 4
4
2.2K_0402_5%
5
wide 30MIL GND1
2
A 6 A
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
2
MIC1 GND2
1 1 1 1
C610
C627
C624
C611
C633 1 2 2.2U_0603_6.3V4Z MIC_INR ACES_88231-04001
1
2 GNDA
R02
1 1 MIC_INL
WM-64PCY_2P 2 2 2 2 @ D70 D71 @
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
45@ TVNST52302AB0 C/C SOT523 TVNST52302AB0 C/C SOT523
2 2
C636
C640

@ @ 2011/06/15 2012/07/11 Title
CX20671 Codec
Custom 0.2
LA-7981P
5 4 3 2 1
+3VLP
1
C535
+3VALW 100P_0402_50V8J
2
Vcc 3.3V +/- 5%
L44
FBM-11-160808-601-T_0603 +3VALW
1 1 1 1 1 1
+EC_VCCA R694 100K +/- 5%
0.1U_0402_16V4Z
C653
0.1U_0402_16V4Z
C654
0.1U_0402_16V4Z
C662
0.1U_0402_16V4Z
C655
1000P_0402_50V7K
C657
1000P_0402_50V7K
C658
+3VALW 1 2 +EC_VCCA
1 1 Board ID R695 VAD_BID min V AD_BID typ VAD_BID max
C659
C656 2 2 2 2 2 2
0 0 0 V 0 V 0 V MP
111
125
0.1U_0402_16V4Z 1000P_0402_50V7K U31
22
33
96
67
9
2 ECAGND 2
1 2 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V PVT
L45
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
FBM-11-160808-601-T_0603 18K +/- 5%
2 0.436 V 0.503 V 0.538 V DVT
3 33K +/- 5% 0.712 V 0.819 V 0.875 V EVT
<19> GATEA20
1 21
GATEA20/GPIO00 GPIO0F BEEP#
<19> KBRST# 2 23 BEEP# <41>
KBRST#/GPIO01 BEEP#/GPIO10 NOVO#
<14> SERIRQ 3 26 NOVO# <43>
SERIRQ GPIO12 ACOFF +3VS +3VALW
<14,36> LPC_FRAME# 4 27 ACOFF <49>
LPC_AD3 LPC_FRAME# ACOFF/GPIO13
<14,36> LPC_AD3 5
2
LPC_AD2 LPC_AD3
<14,36> LPC_AD2 7 PWM Output
1
LPC_AD1 LPC_AD2 BATT_TEMP
<14,36> LPC_AD1 8 63 BATT_TEMP <48>
LPC_AD0 LPC_AD1 BATT_TEMP/GPIO38 VGA_IMVP_IMON 2 R758
<14,36> LPC_AD0 10 LPC & MISC 64 1 0_0402_5% GPU_IMON <54>
R694
LPC_AD0 GPIO39 R588 100K_0402_1%
2 1 2 1 65 ADP_I <48,49>
@ C660 22P_0402_50V8J @ R589 10_0402_5% ADP_I/GPIO3A 10K_0402_5%
<18> CLK_PCI_EC 12 AD Input 66
1
CLK_PCI_EC GPIO3B BRDID @ BRDID
<18,23,36,37,45> PLT_RST# 13 75
2
EC_RST# PCIRST#/GPIO05 GPIO42 EC_FAN_PWM
+3VALW 1 2 37 76 IMVP_IMON <55>
2
R590 47K_0402_5% EC_SCI# EC_RST# IMON/GPIO43 R04
<19> EC_SCI# 20
BATT_LEN# EC_SCII#/GPIO0E R695
2 <48> BATT_LEN# 38
GPIO1D
68 8.2K_0402_5%
C661 DAC_BRIG/GPIO3C +5VALW
70
0.1U_0402_16V4Z EN_DFAN1/GPIO3D
DA Output 71
1
1 KSI0 IREF/GPIO3E +3VALW
55 72
KSI1 KSI0/GPIO30 CHGVADJ/GPIO3F
56
KSI1/GPIO31
KSI2 57 EC_MUTE# 1 R593 2 10K_0402_5%
KSO[0..15] KSI3 KSI2/GPIO32 R594 +5VS +3VS +5VS +3VS
58 83 EC_MUTE# <41>
<43> KSO[0..15] KSI4 KSI3/GPIO33 EC_MUTE#/GPIO4A USB_ON# USB_ON# 1
59 84 USB_ON# <44,45> 2
KSI[0..7] KSI5 KSI4/GPIO34 USB_EN#/GPIO4B INT#
60 85
<43> KSI[0..7] KSI6 KSI5/GPIO35 CAP_INT#/GPIO4C 10K_0402_5% nonBBH@
61
KSI6/GPIO36 PS2 Interface EAPD/GPIO4D
86 EAPD <41>
KSI7 62 87 TP_CLK R603 1 2 4.7K_0402_5%
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <43>
+3VALW KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <43>
R595 1 @ 2 47K_0402_5% KSO1 KSO1 40 TP_CLK R591 1 BBH@ 2 4.7K_0402_5%
KSO2 KSO1/GPIO21
41
R597 1 @ KSO2/GPIO22
2 47K_0402_5% KSO2 KSO3 42 97 CPU1.5V_S3_GATE
CPU1.5V_S3_GATE <10,46,53>
R598 1nonBBH@ 2 4.7K_0402_5%
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 TP_DATAR592 1
KSO4 43 98 VGA_AC_DET
VGA_AC_DET <23,54> 2 4.7K_0402_5%
KSO5 KSO4/GPIO24 WOL_EN/GPXIOA01 BBH@
KSO5/GPIO25 Int. K/B
44 99 ME_FLASH <14>
HDA_SDO/GPXIOA02
KSO6 45 109 NTC_V_R 2 R750 1 0_0402_5% +3VALW
KSO7 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 NTC_V <48>
+3VALW
46
KSO7/GPIO27 SPI Device Interface
+3VS KSO8 47
R600 KSO9 KSO8/GPIO28 PCH_PWR_EN PCH_PWR_EN 2 R599 @1 100K_0402_1% BATT_TEMP
48 119 PCH_PWR_EN <46,48> 1 2
EC_SMB_CK1 KSO10 KSO9/GPIO29 SPIDI/GPIO5B C663 100P_0402_50V8J
1 2 49 120
2.2K_0402_5% KSO11 KSO10/GPIO2A SPIDO/GPIO5C ACIN
50
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
126 1 2
R604 KSO12 51 128 C664 100P_0402_50V8J
R601 R602 EC_SMB_DA1 KSO13 KSO12/GPIO2C SPICS#/GPIO5A
1 2 52 1 2
2.2K_0402_5% KSO14 KSO13/GPIO2D R522 @ 4.7K_0402_5%
2.2K_0402_5% 2.2K_0402_5% 53
KSO15 KSO14/GPIO2E
54 73 ENBKL <33>
KSO16 KSO15/GPIO2F ENBKL/GPIO40 RST
81 74
EC_SMB_CK2 <43> KSO16 KSO17 KSO16/GPIO48 PECI_KB930/GPIO41
82 89 LAN_PWR_ON# <37>
EC_SMB_DA2 <43> KSO17 KSO17/GPIO49 FSTCHG/GPIO50 BATT_CHG_LED#
90 BATT_CHG_LED# <43>
BATT_CHG_LED#/GPIO52 CAPS_LED#
1 1 91 CAPS_LED# <43>
@ @ EC_SMB_CK1 CAPS_LED#/GPIO53
<48,49> EC_SMB_CK1 77
EC_SMB_CK1/GPIO44 GPIO PWR_LED#/GPIO54
92 PWR_LED# <43> +3VLP
C665 C666 EC_SMB_DA1 78 93 BATT_LOW_LED#
<48,49> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# <43>
100P_0402_50V8J 100P_0402_50V8J EC_SMB_CK2 79 SM Bus 95 SYSON
2 2 <15,23,39> EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <45,46,51>
EC_SMB_DA2 80 121 @
<15,23,39> EC_SMB_DA2 VR_ON <55>
1
EC_SMB_DA2/GPIO47 VR_ON/GPIO57 KB9012A2 work around
127 PM_SLP_S4# <16>
PM_SLP_S4#/GPIO59 R4945
47K_0402_5% <55> VR_HOT#
VR_HOT# 1 R737 2 H_PROCHOT# <6,48>
6 100 0_0402_5%
<16> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# <16>
14 101 EC_LID_OUT#
<16> PM_SLP_S5# EC_LID_OUT# <19>
1
EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 Turbo_V D
<19> EC_SMI# 15 102 Turbo_V <48>
EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 H_PROCHOT#_EC R757 @ 0_0402_5% H_PROCHOT#_EC
<33> CMOS_ON# 16 103 2 1 PROCHOT <48> 2 1
+3VS GPIO0A H_PROCHOT#_EC/GPXIOA06 MAINPWON_R R738 @ 0_0402_5% G
17 104 1 2 MAINPWON <48,50>
GPIO0B VCOUT0_PH/GPXIOA07 BKOFF# Q37 C493
18 GPO 105 BKOFF# <33> S
3
ODD_DA# GPIO0C BKOFF#/GPXIOA08 PBTN_OUT# 2N7002H_SOT23-3 47P_0402_50V8J
<18,40> ODD_DA# 19
GPIO0D GPIO PBTN_OUT#/GPXIOA09
106 PBTN_OUT# <16> 2
EC_INVT_PWM 25 107 PCH_APWROK <16>
<33> EC_INVT_PWM EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10
1 2 EC_TACH EC_TACH 28 108 SA_PGOOD <52>
<39> EC_TACH FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11
R605 10K_0402_5% EC_PME# 29
EC_TX EC_PME#/GPIO15
<36,43> EC_TX 30
EC_RX EC_TX/GPIO16 ACIN
<36,43> EC_RX 31 110 ACIN <16,49>
PCH_PWROK EC_RX/GPIO17 AC_IN/GPXIOD01 EC_ON +3VALW
<16> PCH_PWROK 32 112 EC_ON <43,50>
EC_FAN_PWM PCH_PWROK/GPIO18 EC_ON/GPXIOD02
<39> EC_FAN_PWM 34 114 ON/OFF <43>
SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 LID_SW#
36 GPI 115 LID_SW# <43>
2
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 SUSP#
2 1 NUM_LED#: NC SUSP#/GPXIOD05
116 SUSP# <10,25,46,51,52,53,54>
@ R608 117 PCH_HOT#_R R792 2 @ 1 0_0402_5%
GPXIOD06 PCH_HOT# <15>
10K_0402_5% 118 PECI_KB9012 1 2 R606
PECI_KB9012/GPXIOD07 H_PECI <6,19>
AGND/AGND
R611 EC_RTCX1 122 R669 43_0402_1% 10K_0402_5%

XCLKI/GPIO5D
GND/GND
GND/GND
GND/GND
GND/GND
2 1 SUSCLK_R 123 124 +V18R

<16> SUSCLK
1
0_0402_5% XCLKO/GPIO5E V18R
1
GND0
1
C667
1
4.7U_0805_10V4Z R609 2 @ 1
R740 C93 2 0_0402_5% LAN_WAKE# <37>
11
24
35
94
113
69
100K_0402_5% 20P_0402_50V8
2
2 R610 1
2
KB9012QF A3 LQFP 128P_14X14

ECAGND
EMC Request 0_0402_5% @
EC_RTCX1 SYSON EC_PME#
S
1 3 PCI_PME# <18>
C492
SUSCLK_R PN : SA00004OB20 S IC KB9012QF A3 LQFP 128P KB CONTROLLER Q102 @
0.1U_0402_10V6K
1 2
R120 @ 2N7002_SOT23
G
2
10M_0402_5% 1 +3VALW
@
JCAP1 ME@ 2
32.768KHZ_12.5PF_9H03200413
1
4
18P_0402_50V8J
ACES_50521-0084N-P01
Y5 1
OSC
OSC
RST 1
1 1 2
C347 @ C367 @ 2
+3VS 3
@ 18P_0402_50V8J EC_SMB_DA2 3
4
4
NC
NC
EC_SMB_CK2 5
2 2 5
6
INT# 6
7
2
7
8
+5VS 8 Security Classification Compal Secret Data Compal Electronics, Inc.
check R03 9
10
GND1
GND2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
Custom 0.2
Capsensor Board For best buy use DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-7981P
KSI[0..7]
KSI[0..7] <42>
JKB1 ME@
KSO[0..17] KSO16 C693 1 2 @ 100P_0402_50V8J KSI1 1 JKB2 ME@
KSO[0..17] <42> 1
KSI7 2 26
KSO17 C692 1 2 GND2
2 @ 100P_0402_50V8J KSI6 3 25
KSO9 3 GND1
4
KSO2 C668 1 KSO1 KSI4 4 KSI1
2 @ 100P_0402_50V8J C669 1 2 @ 100P_0402_50V8J 5 24
KSI5 5 KSI7 24
6 23
KSO15 C670 1 KSO7 KSO0 6 KSI6 23
2 @ 100P_0402_50V8J C671 1 2 @ 100P_0402_50V8J 7 22
KSI2 7 KSO9 22
8 21
KSO6 C672 1 KSI2 KSI3 8 KSI4 21
2 @ 100P_0402_50V8J C673 1 2 @ 100P_0402_50V8J 9 20
KSO5 9 KSI5 20
10 19
KSO8 C674 1 10 19
2 @ 100P_0402_50V8J KSO5 C675 1 2 @ 100P_0402_50V8J KSO1 11 KSO0 18
KSI0 11 KSI2 18
12 17
KSO13 C676 1 12 17
2 @ 100P_0402_50V8J KSI3 C677 1 2 @ 100P_0402_50V8J KSO2 13 KSI3 16
KSO4 13 KSO5 16
14 15
KSO12 C678 1 KSO14 KSO7 14 KSO1 15
2 @ 100P_0402_50V8J C679 1 2 @ 100P_0402_50V8J 15 14
KSO8 15 KSI0 14
16 13
KSO11 C680 1 KSI7 KSO6 16 KSO2 13
2 @ 100P_0402_50V8J C681 1 2 @ 100P_0402_50V8J 17 12
KSO3 17 KSO4 12
18 11
KSO10 C682 1 KSI6 KSO12 18 KSO7 11
2 @ 100P_0402_50V8J C683 1 2 @ 100P_0402_50V8J 19 10
KSO13 19 KSO8 10
20 9
KSO3 C684 1 20 9
2 @ 100P_0402_50V8J KSI5 C685 1 2 @ 100P_0402_50V8J KSO14 21 KSO6 8
KSO11 21 KSO3 8
22 7
KSO4 C686 1 22 7
2 @ 100P_0402_50V8J KSI4 C687 1 2 @ 100P_0402_50V8J KSO10 23 KSO12 6
KSO15 23 KSO13 6
24 5
KSI0 C688 1 KSO9 KSO16 24 KSO14 5
2 @ 100P_0402_50V8J C689 1 2 @ 100P_0402_50V8J <42> KSO16 25 4
KSO17 25 KSO11 4
<42> KSO17 26 3
KSO0 C690 1 KSI1 26 KSO10 3
2 @ 100P_0402_50V8J C691 1 2 @ 100P_0402_50V8J 27 2
27 KSO15 2
28 1
28 1
29 31
29 GND ACES_88514-2401
30 32
JP3 30 GND
+3VALW 1 ACES_88514-3001
1
<36,42> EC_TX 2
2
<36,42> EC_RX 3
3
4
4
ACES_85205-0400
ME@
+5VS JCR1 ME@

HP_OUTR 1
+3VLP +3VALW <41> HP_OUTR 1
HP_OUTL 2
+5VALW <41> HP_OUTL 2
2 R689@ 1 0_0402_5% CR_GND 3
+3VALW JPWRB1 EXT_MIC 3
<41> EXT_MIC 4
2
+3VLP ME@ PLUG_IN 4
2 R690 1 0_0402_5% <41> PLUG_IN 5
R642 5
+3VS 6
6
R532@ 100K_0402_5% 1 <18> USB20_N11 2 R687 1 0_0402_5% USB20_N11_C 7
2
NOVO_BTN# 1 7
SMT1-05_4P SW3 @ 100K_0402_5% 2 <18> USB20_P11 2 R683 1 0_0402_5% USB20_P11_C 8
2 8
2
1 3 ON/OFFBTN# 3 5 9
1
R701 D26 3 G1 G9@ CR_GND 9
4 6 10
100K_0402_5% R535 @ NOVO# 4 G2 +USB_VCCB 10
2 4 <42> NOVO# 2 <18> USB20_N1 2 R534 1 0_0402_5% USB20_N1_C 11
2
NOVO_BTN# 11
100K_0402_5% 1 E-T_7182K-F04N-00R <18> USB20_P1 2 R533 1 0_0402_5% USB20_P1_C 12
1
G9@ 12
3 13
6
5
R725 13
14
ON/OFF @ D24 @ 14
J11 1 2 <41> CX_GPIO0 2 R684@ 1 0_0402_5% 15
R720 0_0402_5% DAN202UT106_SC70-3 15
PJSOT24C 3P C/A SOT-23 1 +MICBIASB 2 R685@ 1 0_0402_5% 16
@ 51_ON# G9@ G9@ R688 0_0402_5% 16
1 2 1 2 1 2 1 2 1
1
0_0402_5% R722 @ C734 + C733 2 R686 1 0_0402_5% 17
SHORT PADS 0_0402_5% 220U_6.3V_M 470P_0402_50V7K GND
18
SF000002Y00 GND
2 2 ACES_51524-0160N-001
3 ON/OFF
ON/OFF <42>
ON/OFFBTN# 1
2 51_ON#
51_ON# <47>
LED1 14@
D23 @
DAN202UT106_SC70-3 <42> PWR_LED# PWR_LED# 1 2 2 R623 1 14@ +5VALW
300_0402_5%
L47 @ L57 @
19-213A-T1D-CP2Q2HY-3T_WHITE USB20_N1 1 2 USB20_N1_C USB20_N11 1 2 USB20_N11_C
1 2 1 2
LED2 14@
1
D USB20_P1 USB20_P1_C USB20_P11 USB20_P11_C

4 3 4 3
EC_ON BATT_LOW_LED# 4 3 4 3
<42,50> EC_ON 2 <42> BATT_LOW_LED# 1 2 2 R764 1 14@ +3VALW
G 470_0402_5% WCM-2012-900T_4P WCM-2012-900T_4P
Q106 @ S
3
2
2N7002_SOT23-3 HT-191UD5_AMBER
R639 @
10K_0402_5% LED5 14@
<42> BATT_CHG_LED# BATT_CHG_LED# 1 2 2 R765 1 14@ +5VALW

1
300_0402_5%
19-213A-T1D-CP2Q2HY-3T_WHITE
LED6 14@
<42> CAPS_LED# CAPS_LED# 1 2 2 R2 1 14@ +5VS

+5VS 2 R889 1 0_0402_5% 300_0402_5%
nonBBH@
19-213A-T1D-CP2Q2HY-3T_WHITE
+3VS 2 R890 1 0_0402_5%
BBH@
JTP1 ME@ @
C696 +3VALW 1 2 +VCC_LID 1 R615 2
8 100K_0402_5%
0.1U_0402_16V4Z GND R614 0_0402_5%
7
GND
6
2
TP_CLK 6
<42> TP_CLK 5
TP_DATA 5
4 1
<42> TP_DATA
TP_3 4 VDD
1 1 3
TP_2 3 14@ C702
2
@ C697 C698 @ TP_1 2 0.1U_0402_16V4Z LID_SW#
1 3 LID_SW# <42>
100P_0402_50V8J 100P_0402_50V8J 1 2 OUTPUT
2 2 ACES_88058-060N JLED1 ME@
GND
3
C490
C491
2 +5VALW 1
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1 1 +3VALW 2
15@ C703 14@ 2
+5VS 3
1
@ D15 TP_3 LID_SW# 3

2 R627 1 10P_0402_50V8J 4
PSOT24C_SOT23-3 0_0402_5% @ @ U34 14@ 1 4
5
2 2 PWR_LED# 5
6
1
6
2 R619 1 14@ TP_1 BATT_LOW_LED# 7
0_0402_5% AH1806-W-7 SC59 3P BATT_CHG_LED# 7
8
CAPS_LED# 8
9
SW_R 9
10
SW_L 10
11
11
12
12
13
GND
14
GND
R621 15_nonBBH@ R624 15_nonBBH@ ACES_88058-120N
0_0402_5% 0_0402_5%
SW4 14@ 2 1 TP_2 SW5 14@ 2 1 TP_1
SMT1-05_4P SMT1-05_4P
5
6
5
6
R622 14@ R625 14@

4 2 0_0402_5% 4 2 0_0402_5%
SW_L 2 1 TP_3 SW_R 2 1 TP_2
3 1 3 1 Security Classification Compal Secret Data Compal Electronics, Inc.
2011/06/15 2012/07/11 Title
Issued Date Deciphered Date ROM/KBD/PWR/CR/LED/TP Conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
LA-7981P
A B C D E
1 1
Right Ext.USB Conn.

2 2
JUSB3 ME@
+5VALW 8
+USB_VCCB +USB_VCCB GND
W=80mils 7 GND
RIGHT USB PORT X1
6 6
R02 +USB_VCCB 5
U36 USB20_N9 R868 2 @ USB20_N9_C 5
1 <18> USB20_N9 1 0_0402_5% 4 4
1 8 C714 1 USB20_P9 R869 2 @ 1 0_0402_5% USB20_P9_C 3
GND VOUT + <18> USB20_P9 3
C713 0.1U_0402_16V4Z 2 7 2
VIN VOUT 220U_6.3V_M C715 2
2 1 3 VIN VOUT 6 1 1
2
4 5 470P_0402_50V7K
<42,45> USB_ON# EN FLG USB_OC4# <18> 6.3Φ * 5.9 2 2 ACES_88058-060N
G547I2P81U_MSOP8 SF000001500
1 USB20_N9 4 3 USB20_N9_C
C716 4 3
@ 1000P_0402_50V7K
USB20_P9 1 2 USB20_P9_C
2 1 2 D25 @
1
L66 WCM-2012-900T_4P PJDLC05_SOT23-3
3 3
4 4

USB ext. ports
B 0.2
LA-7981P
A B C D E
5 4 3 2 1
+1.05VDD
+1.5V to +1.05V Transfer @ D27 @ D30 D22
@
D31
@
+5VALW +1.5V +5VALW +1.05V
EU3@
U52 U3RXDN1 9 10 1 1U3RXDN1 U3RXDN2 9 10 1 1U3RXDN2 U2DN1 3 6 U2DP2 3 6
I/O2 I/O4 I/O2 I/O4
1U_0603_10V6K
10U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
C799
0.1U_0402_16V7K
C802
0.1U_0402_16V7K
C805
0.1U_0402_16V7K
C798
0.01U_0402_25V7K
C797
0.01U_0402_25V7K
C800
0.01U_0402_25V7K
C803
0.01U_0402_25V7K
C806
0.01U_0402_25V7K
C808
0.01U_0402_25V7K
EU3@
+1.5V
EU3@
C863
C864
C796
C794
1 1 6 1 1 1 1 1 1 1 1 1 1 1 U3RXDP1 8 9 2 2U3RXDP1 U3RXDP2 8 9 2 2U3RXDP2
VCNTL
5 3
VIN VOUT U3TXDN1 7
9 4 7 4 4U3TXDN1 U3TXDN2 7 7 4 4U3TXDN2 2 5 +5VALW 2 5 +5VALW
+5VALW VIN VOUT GND VDD GND VDD
2 2 SYSON 8 2 2 2 2 2 2 2 2 2 2 2 U3TXDP1 6 6 5 5U3TXDP1 U3TXDP2 6 6 5 5U3TXDP2
EN
10U_0603_6.3V6M
EU3@
EU3@
EU3@
EU3@
EU3@
EU3@
EU3@
EU3@
EU3@
EU3@
EU3@
2 1 7 2 1 R1149 2
GND
POK FB
C886 EU3@
R1150 5.1K_0402_1% 10K_0402_1% 1 3 3 3 3 1 4 U2DP1 1 4 U2DN2
I/O1 I/O3 I/O1 I/O3
1
EU3@ EU3@
APL5930KAI-TRG_SO8 R1151 8 8
1
D 32.4K_0402_1% AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6 D
EU3@ 2
Vout=0.8(1+10K/32.4K)
YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9
1.042 ~ 1.0469 ~ 1.0519V For EMI request
2
+3V +3V +3AVDD Close to U32.3 Close to U32.25
Spec: 0.9975 ~ 1.05 ~ 1.1025 L60 EU3@
1 2
FBMA-L11-201209-221LMA30T_0805
C887
10U_0603_6.3V6M
C816
0.1U_0402_16V7K
C817
0.1U_0402_16V7K
C809
0.01U_0402_25V7K
C810
0.01U_0402_25V7K
C811
0.01U_0402_25V7K
C812
0.01U_0402_25V7K
C813
0.01U_0402_25V7K
C888
10U_0603_6.3V6M
C821
0.1U_0402_16V7K
C825
0.01U_0402_25V7K
C823
0.1U_0402_16V7K
C827
0.01U_0402_25V7K
1 1 1 1 1 1 1 1 1 1 1 1 1
Intel_PCH_USB2.0
+3VALW to +3V Transfer 1 R728@ 2
0_0402_5%
2 2 2 2 2 2 2 2 2 2 2 2 2
WCM-2012-900T_4P
EU3@
EU3@
EU3@
EU3@
EU3@
EU3@
EU3@
EU3@
EU3@
EU3@
EU3@
EU3@
EU3@
R730
+3VALW +3V 2 IU3@ 1 U2DN2_L 1 2 U2DN2
<18> USB20_N3 1 2
0_0402_5%
U30 EU3@ R640
0.2A 2 IU3@ 1 U2DP2_L 4 3 U2DP2
+1.05V <18> USB20_P3 4 3
3 1 0_0402_5%
VIN VOUT L55
<42,46,51> SYSON 4 5
VIN/CE VOUT
1 R721@ 2
2
2 0_0402_5%
GND R766
RT9701-PB_SOT23-5 0_0603_5%
+3V EU3@ +1.05VDD +3AVDD 1 R742@ 2
0_0402_5%
1
U32 Intel_PCH_USB3.0
EU3@ R709IU3@ WCM-2012-900T_4P +USB3_VCCA
1 U3RXDN2_L U3RXDN2
12
22
34
43
21
30
33
39
42
25
<18> USB3_RX4_N 2 1 2
1 2
3
0_0402_5% W=80mils
+3V +3V LP2
VDD33
VDD33
VDD33
VDD33
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
AVDD33
AVDD33
2 1 U3RXDP2_L 4 3 U3RXDP2 JUSB2
C <18> USB3_RX4_P 4 3 C
R714 IU3@ U3TXDP2 9
SSTX+
2
0_0402_5% L54 1
VBUS
<15> CLK_PCIE_USB30 1 1 R743@ 2 U3TXDN2 8
R1187 EU3@ PECLKP U3TXDP2_R C844 1 SSTX-
<15> CLK_PCIE_USB30# 2 37 2 EU3@ .1U_0402_16V7K U3TXDP2_L 0_0402_5% U2DP2 3
2
EU3@ PECLKN U3TXDP2 D+

G
10K_0402_5% 7
.1U_0402_16V7K2 GND
1 C834 PCIE_PRX_C_DTX_P4 4 38 U3TXDN2_R C846 1 2 EU3@ .1U_0402_16V7K U3TXDN2_L 1 R636@ 2 U2DN2 2 10
1
<15> PCIE_PRX_DTX_P4 PETXP U3TXDN2 D- GND

<16,36,37> PCIE_WAKE# 1 3 <15> PCIE_PRX_DTX_N4 2 1 C835 PCIE_PRX_C_DTX_N4 5 45 U2DN2_R R774 2 EU3@ 1 0_0402_5% U2DN2_L 0_0402_5% U3RXDP2 6 11
.1U_0402_16V7K EU3@ PETXN U2DM2 C850 IU3@ SSRX+ GND
PCIE_WAKE#_USB3 4 12
D
U2DP2_R R776 2 EU3@ 1 0_0402_5% U2DP2_L .1U_0402_16V7K WCM-2012-900T_4P U3RXDN2 GND GND
<15> PCIE_PTX_C_DRX_P4 7 44 5 13
PERXP U2DP2 U3RXDP2_R U3RXDP2_L SSRX- GND
Q125 EU3@
<15> PCIE_PTX_C_DRX_N4 8 40 R772 2 EU3@ 1 0_0402_5%
<18> USB3_TX4_N 1 2 U3TXDN2_L 1 2 U3TXDN2
SSM3K7002FU_SC70-3 PERXN U3RXDP2 1 2 TAITW_PUBAU1-09FNLSCNN4H0
R02 1 41 U3RXDN2_R R763 2 EU3@ 1 0_0402_5% U3RXDN2_L ME@
U3RXDN2 U3TXDP2_L U3TXDP2
<18> USB3_TX4_P 1 2 4 3
C837 EU3@ PLT_RST#_USB3 +3V 4 3
47
PCIE_WAKE#_USB3 48 PERSTB R1161 EU3@ C848 IU3@ L53
1000P_0402_50V7K PEWAKEB
2 CLKREQ_USB3 10 17 OCI2B 1 2 10K_0402_5% .1U_0402_16V7K
PECREQB OCI2B OCI1B 1
19 2 10K_0402_5% 1 R638 @2
OCI1B R1162 EU3@ 0_0402_5%
R770 UPD720202K8-701-BAA_QFN48_7X7 18
EU3@ @ 0_0402_5% SMIB_R PPON2
<18> SMIB 1 2 46 20
SMIB PPON1
<18,23,36,37,42> PLT_RST# 1 R747 2 PLT_RST#_USB3
430K_0402_5% Intel_PCH_USB2.0
+3V EU3@ 1 R1172 2 300K_0402_5% 11 1 R563@ 2
PONRSTB
1U_0402_6.3V6K
C832
1 28 U3TXDP1_R C843 EU3@ 1 2 .1U_0402_16V7K U3TXDP1_L 0_0402_5%

U3TXDP1
1U_0603_10V6K
EU3@ 1 2
1 2 WCM-2012-900T_4P
C894 EU3@
1 SPI_CLK_USB 15 29 U3TXDN1_R C845 EU3@ 1 2 .1U_0402_16V7K U3TXDN1_L 0_0402_5%
D67 EU3@ SPI_CS_USB# 14 SPISCK U3TXDN1 U2DN1_R R759 2 EU3@
36 1 0_0402_5% U2DN1_L
<18> USB20_N2 2 IU3@ 1 U2DN1_L 1 2 U2DN1
2 1SS355TE-17_SOD323-2 USB_SO_SPI_SI 16 SPICSB U2DM1 R755 1 2
R03 USB_SI_SPI_SO 13 SPISI U2DP1_R R754 2 EU3@
35 1 0_0402_5% U2DP1_L
SMIB_R 2 SPISO U2DP1 U3RXDP1_R U3RXDP1_L U2DP1_L U2DP1
1 R267 2 +3V 31 R760 2 EU3@ 1 0_0402_5% <18> USB20_P2 2 R741 1 4 3
U3RXDP1 IU3@ 4 3
10K_0402_5% 32 U3RXDN1_R R762 2 EU3@ 1 0_0402_5% U3RXDN1_L 0_0402_5% L51
B +3V +3V USB3_XT1 24 U3RXDN1 B
EU3@ 1 R562@ 2
USB3_XT2 23 XT1 0_0402_5%
XT2
2
R1152 EU3@ 1 R564@ 2

1
27 26 1 2 Intel_PCH_USB3.0 0_0402_5%
R745 EU3@ R1180 EU3@ IC(L) RREF
10K_0402_5% 100_0402_5% 1.6K_0402_1% R773 IU3@ WCM-2012-900T_4P +USB3_VCCA
GND
2
1 U3RXDN1_L U3RXDN1
G
2 1 2
1
<18> USB3_RX3_N 1 2
0_0402_5% W=80mils
LP1
2
1 3 CLKREQ_USB3 24MHZ_12PF_X5H024000DC1H
49
<15> CLKREQ_USB30# U3RXDP1_L U3RXDP1 JUSB1
1 2 2 1 4 3
D
<18> USB3_RX3_P 4 3
1 R739 IU3@ U3TXDP1 9
Q121 EU3@ R02 Y7 EU3@ 0_0402_5% L50 SSTX+
1
SSM3K7002FU_SC70-3 C836 EU3@ VBUS
1 1 1 R561@ 2 U3TXDN1 8
C897 EU3@ C898 EU3@ 0_0402_5% U2DP1 SSTX-
1000P_0402_50V7K 3
2 12P_0402_50V8J 15P_0402_50V8J D+
7
GND
2A/Active Low 1 R565@ 2 U2DN1 2 10
2 2 0_0402_5% U3RXDP1 D- GND
6 11
+5VALW +USB3_VCCA C849 IU3@ SSRX+ GND
4 12
.1U_0402_16V7K WCM-2012-900T_4P U3RXDN1 GND GND
5 13
C704 U35 R02 U3TXDN1_L U3TXDN1 SSRX- GND
W=80mils <18> USB3_TX3_N 1 2 1
1 2
2
.1U_0402_16V7K 1 8 TAITW_PUBAU1-09FNLSCNN4H0
GND VOUT ME@
1 2 2 7
VIN VOUT R570 U3TXDP1_L U3TXDP1
3 6 <18> USB3_TX3_P 1 2 4 3
+3V +3V +3V VIN VOUT 4 3
<42,44> USB_ON# 1 2 4 5 1 2 USB_OC1# <18>
R566 0_0402_5% EN FLG 0_0402_5% C847 IU3@ L49
G547I2P81U_MSOP8 .1U_0402_16V7K 1 R546@ 2
0_0402_5%
2
1
C895 EU3@ 1 Place TX AC coupling Cap (C843~C850). Close to connector
R1177 EU3@ .1U_0402_16V K R1175 EU3@ R1176 EU3@ 1 C735
10K_0402_5% 10K_0402_5% 47K_0402_5% +
A 2 U53 C736 470P_0402_50V7K A
1
EU3@ 220U_6.3V_M
8 1 SPI_CS_USB# SF000002Y00 2 2
VCC CS# USB_SI_SPI_SO
7 2
SPI_CLK_USB HOLD# SO
6 3
USB_SO_SPI_SI 5 SCK WP#
4
SI GND
AT25F512AN-10SU-2.7_SO8~D
USB3.0/Left USB Ports
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
5 4 3 2 1
A B C D E
+3VALW TO +3VALW(PCH AUX Power)

+5VALW TO +5VS
+3VALW TO +3VS
+5VALW +5VS +3VALW +3VS
U38 +3VALW @ +3V_PCH
PJ1
U39
DMN3030LSS-13_SOP8L-8 DMN3030LSS-13_SOP8L-8 2 1
8 1 8 1
1 7 2 1 1 10U 1 7 2 1 1 JUMP_43X118
1
6 3 6 3
C720 5 C721 C722 C723 5 C724 C725 @
1 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0603_10V4Z R644 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0603_10V4Z R645 U40 1
2 2 2 470_0603_5% 2 2 2 470_0603_5% DMN3030LSS-13_SOP8L-8
4
10U 10U @ 10U @ 8 1
1 2
1 2
1
+VSB 7 2
D D 1 1
+VSB @ 6 3 @
2 SUSP 2 SUSP C782 5 C780 R777 @
1
1
G G 10U_0603_6.3V6M 1U_0603_10V4Z 470_0603_5%
R646 S Q107 S Q108 2 2
1
1 2
150K_0402_5% 2N7002_SOT23 R647 2N7002_SOT23
@ 470K_0402_1% @ C783 D
+VSB 10U_0603_6.3V6M 2 PCH_PWR_EN#
2
2
5VS_GATE 2 R649 15VS_GATE_R 2 @ G
1
1 1 S Q118 @
3
1
1
D D R650 @ 2N7002_SOT23
Q110 82K_0402_5% C726 R03 Q111 C727 R03 R778
SUSP 2 SUSP 2 0_0402_5%
G 2N7002_SOT23 0.01U_0603_50V7K G 2N7002_SOT23 0.01U_0603_50V7K 47K_0402_5%
S 2 S @ 2
3
2
1
1
D @ R779 @ @
PCH_PWR_EN# 2 Q120 0_0402_5% C781
G 2N7002_SOT23 0.1U_0603_25V7K
S 2
1
+1.5V to +1.5VS
+1.8VS +1.5V +1.05VS +0.75VS
+1.5V Q8 +1.5VS
1
PMV65XP_SOT23-3~D +5VALW
D
2 R655 R656 R659 R658 2
3 1
1
470_0603_5% 470_0603_5% 470_0603_5% 22_0603_5% 1 1 1
1
@ @ @ 2 1 CPU1.5V_S3_GATE <10,42,53>
1 2
1 2
1 2
1 2
@ R91 0_0402_5% C717 C718 C719 R780
G
2
D D D D 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0603_10V4Z R643 100K_0402_5%
2 SUSP 2 SYSON# 2 SUSP 2 SUSP 2 2 2 470_0603_5%
2
G G G G @
2
S Q113 S Q114 S Q116 S Q115 10U PCH_PWR_EN#
3
2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23
1
@ @ @ +3VALW D
1
D
2 SUSP
G PCH_PWR_EN 2
<42,48> PCH_PWR_EN
1
S Q109 G
3
For Intel S3 Power Reduction. 2N7002_SOT23 Q124 S
3
1
100K_0402_5% @ 2N7002_SOT23
R648
R781
2
2 R651 1 1.5VS_GATE 100K_0402_5%
+RTCVCC +5VALW +5VALW Q112 1 1
2
1
D
SUSP# 2 0_0402_5% C728 C729
2
Check G 0.1U_0603_25V7K
R652 @ @ 2N7002_SOT23 S 2 2
3
220K_0402_5% R653 R654 0.1U_0603_25V7K
100K_0402_5% 100K_0402_5%
+1.5V to +1.5VS_VGA Transfer
1
SUSP SYSON#
<10,53,54> SUSP
1
Q117 +1.5V +1.5VS_VGA

1
DTC124EKAT146_SC59-3 @ Q119
OUT
DTC124EKAT146_SC59-3
OUT
3 SYSON J12 @ 3
<42,45,51> SYSON 2
IN 300mil(7.2A)
2 2 1
GND
10,25,42,51,52,53,54> SUSP# IN 2 1
1 1
GND
JUMP_43X118
C856 @ C851
3
1
10U_0603_6.3V6M AO4430: Rdson: 5.5mohm @ VGS=10V 10U_0603_6.3V6M

3
2 2
R1110 @ 10U U49 10U
100K_0402_5% AO4304L_SO8
300mil(7.2A)
8 1
2
7 2
6 3
2
5 1 1
1 C853 C854 R1101 @
C852 10U_0603_6.3V6M 0.1U_0402_16V4Z 470_0603_5%
4
10U_0603_6.3V6M
10U 2 2
1
+5VALW 10U 2
+VSB
1
R1102 10K_0402_5%
R1107 2 1
1
100K_0402_5% D @
1 @ Q127 2 2 R790 1 DGPU_PWROK#
2
2
R02 C855 2N7002_SOT23 G 0_0402_5%
DGPU_PWROK# Q126 R784 @ 0.1U_0603_25V7K S
DGPU_PWROK# <54>
3
R1106 2N7002_SOT23 0_0402_5%
1
1
0_0402_5% D D 2 2 R791 @1 SUSP
2 1 2 Q129 DGPU_PWROK# 2 R782 1 2 0_0402_5%
<19,54> DGPU_PWROK
1
G 2N7002_SOT23 0_0402_5% G
S S
3
4
3 4
1
SUSP 2 R789 @1
0_0402_5%
R1108
100K_0402_5%
@
2

DC Interface
Custom 0.2
LA-7981P
A B C D E
5 4 3 2 1
DC030006J00 VIN
PF101 PL101
7A_24VDC_429007.WRML SMB3025500YA_2P
4 APDIN 1 2 APDIN1 1 2
4
3 3
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
2
2
1
D D
1
1
2
@ 4602-Q04C-09R 4P P2.5
PC101
PC102
PC103
PC104
JDCIN1
Unpop for KB9012 VIN
2
@
PD103
LL4148_LL34-2
@ PD104 PJ101
1
LL4148_LL34-2 @ JUMP_43X39 51ON-1
C
BATT+ 2 1 1 1 2 2
C
1
PR118 PR119
PQ104 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3
PR120
2
200_0603_5%
CHGRTCP 1 2 51ON-2 3 1
VS
0.22U_0603_25V7K
@ @
1
1
PC112
@ PR123 PC113
100K_0402_1% 0.1U_0603_25V7K
1
2
PR124
2
22K_0402_1%
1 2 51ON-3 @
+3VLP <43> 51_ON#
@
@
@ @
2
PR127 RTCVREF
1
0_0402_5%
@ PU102 PR128
200_0603_5%
1
APL5156-33DI-TRL_SOT89-3
3.3V
2
3 2 CHGRTCIN
VOUT VIN
@
1
@ GND PC115
B PC114 1U_0805_25V6K B
10U_0603_6.3V6M 1
2
+CHGRTC
- JRTC2 + PR131
560_0603_5%
PR132
560_0603_5%
PD109
RB751V-40_SOD323-2
2 1 1 2 1 2 2 1 +RTCBATT
@ MAXEL_ML1220T10 1 2
RTCVREF
PD108
RB751V-40_SOD323-2
RTC Battery
A A

PWR DCIN / Vin Detector /Pre-charge
Custom 0.1
C38-G series Chief River Schematic
5 4 3 2 1
5 4 3 2 1
VMB2 VMB
PF201 PL201
JBATT1 12A_65V_451012MRL SMB3025500YA_2P
1 1 1 2 1 2 BATT+
2 2
3 EC_SMCA
3 EC_SMDA
4
4
5
5
1
D D
6
6
1
7 PC201 PC202
7
100_0402_1%
100_0402_1%
1000P_0402_50V7K 0.01U_0402_25V7K
8
ADP_I need to write Charge Options Register (0x12H)=> bit6=1
2
GND
9
GND PR201
PR202
TYCO_1775789-1
2
2
@ 0: IOUT is the 20x current amplifier output <default @ POR>
1: IOUT is the 40x current amplifier output
JBATT2 For KB930 --> Keep PU201 circuit

PH1 under CPU botten side :
1 1 (Vth = 1.25V)
2 2 EC_SMB_CK1 <42,49> CPU thermal protection at 93 +-3 degree C
3 3
4
For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206
4 Recovery at 56 +-3 degree C
5 5
6
EC_SMB_DA1 <42,49> PH201, PR205, PR211,PQ201,PR208,PR212
6
7
7
8 1 2 +3VALW
VL
GND
GND 9 PR203
6.49K_0402_1%
+3VLP
<42,49> ADP_I
21.5K_0402_1%
TYCO_1775789-1
1
4.42K_0402_1%
12.7K_0402_1%
@
PR207
1 2 A/D @
BATT_TEMP <42>
PR205
PR206
PR204
1
10K_0402_5%
PC203 +3VS
2
0.1U_0603_16V7K PU201
2
1 8 NTC_V_2
VCC TMSNS1
100K_0402_1%
C OTP_N_002 C
2 GND RHYST1 7 2 1
PR208
PR209
2
<6,42,49> H_PROCHOT# 3 OT1 TMSNS2 6
PR210
Turbo_V_2 +3VALW 10K_0402_1%
ADP_OCP_2 1 @ PR231
100K_0402_1%_NCP15WF104F03RC
4 5 2
1
OT2 RHYST2
PH201
PQ201 0_0402_5%
2
D
10K_0402_1%
G718TM1U_SOT23-8 27.4K_0402_1% PR230
1
PR211
2 ADP_OCP_1 @ PR227 2 1
OTP_N_003
G 0_0402_5%
S SSM3K7002FU_SC70-3 47K_0402_1%
2
1
PR212 2 PR232 1 @ PR233
0_0402_5% 0_0402_5% 2 1
<42> PROCHOT 1 2 2 1 MAINPWON <42,50>
47K_0402_1%
PR213 0_0402_5%
<42>
<42>
Turbo_V
NTC_V
@
90W(DIS) : PR205=4.42K
PR210=27.4K
+3VLP
65W(UMA) : PR205=402(SD034020080)
PR210=5.11K
B B
P2
PQ205
+3VLP +3VALW
0.01U_0402_25V7K
TP0610K-T1-E3_SOT23-3
1
PC204
B+ 3 1 +VSBP
2
VMB2
100K_0402_1%
0.22U_0603_25V7K
PR214 PR215
2
1
100K_0402_1% 100K_0402_1%
1
PR216
PC205
PR217 PR218 <BOM Structure>
2
768K_0402_1% 10M_0402_5% PC206

1
1 2 0.1U_0603_25V7K
2
BATT_OUT <49>
PR219
2
10K_0402_1% PR220
8
1 2 PQ202 VL 22K_0402_1%
1
D 2N7002KW_SOT323-3
3 1 2
P
+
1 2
O
2
PR221 2 G
-
G
2
221K_0402_1% PU202A S @ PR222

3
LM393DG_SO8 100K_0402_1%
4
+3VLP PR224
1
PR229
1
PQ203 @ 1K_0402_5% D PJ201

1
D 2N7002KW_SOT323-3
<50> SPOK 20_0402_5%1 1 2 2 PQ204 @ JUMP_43X39
2 1 2 G 2N7002W-T/R7_SOT323-3 1 2
2VREF_8205 +VSBP 1 2 +VSB
2
1U_0402_6.3V6K
G S
3
PR228
1
PC207
PR223 PR226 S
3
10K_0402_1% 100K_0402_1% 2 1
<50> PCH_PWR_EN
2 1
2
RTCVREF
1
A PR225 0_0402_5% A
10K_0402_1%
@
<42> BATT_LEN#

PWR-BATTERY CONN/OTP
Custom 0.1
5 4 3 2 1
5 4 3 2 1
P3
B+
P2
PQ301 PQ302
AO4407A_SO8 AO4423L_SO8
PR302
VIN 8 1 1 8
0.01_1206_1% B+
7
6
2
3
2
3
7
6
SH00000AA00
5 5 1 2 1 4 PQ303
AO4407A_SO8
PL301 2 3 1 8
4
1UH_PCMB061H-1R0MS_7A_20% 2 7
@ 10U_0805_25V6K
@ 10U_0805_25V6K
3 6
2200P_0402_50V7K
PQ304
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
D 5 D
47K_0402_5%
1 2
1
2
200K_0402_1%
0.1U_0603_25V7K
PC307
4
1
PR301
PC302
PC315
PC303
PC305
PC306
DTA144EUA_SC70-3 PC304 DISCHG_G
PC301
PR303
5600P_0402_25V7K
1
PR304
200K_0402_1%
2
2
2 1 2
2
ACN VIN
2ACOFF-1
1SS355_SOD323-2
2
1
ACP PR305
1DISCHG_G-1
47K_0402_1%
1
2
PD301
P2-1 PR306
0.1U_0603_25V7K
1
2 200K_0402_1%
PQ305 PQ306
1
+3VALW PC308 PC309 DTC115EUA_SC70-3
1
DTC115EUA_SC70-3 +3VALW
PR307 <50> ACPRN PD302
1 2 2 1
3
20K_0402_1% 1SS355_SOD323-2
100K_0402_1%
1 2 0.1U_0603_25V7K 2 1 2
6
10K_0603_1%
PQ308
1
1
D
150K_0402_1%
2N7002KW _SOT323-3 PC310 PQ309
2
PR308
PR309
PR310
PQ307A 2 BATT_OUT <48>
2 2N7002KDW -2N_SOT363-6 G 0.1U_0603_25V7K P2 2N7002W -T/R7_SOT323-3
1
D
0.1U_0603_25V7K
S
3
@ 2 1 2 PACIN
1
PR313
1
PC311
VIN @ PR312 @ @ G
1
10K_0402_5%
10K_0402_5%
2 1 1 2 S
3
2
2
390K_0603_1% 4.7M_0603_1%
2
1
P2-2
PR315
PR316
10_1206_5%
39.2K_0402_1%
5
6
7
8
C C
PR314
2N7002KDW-2N_SOT363-6
PQ310
PR319
AO4466L_SO8
3
PQ307B
<BOM Structure>
ACOK
CMPIN
CMPOUT
ACP
ACN
1
1
PR318 <42,48> ADP_I
2
47K_0402_1% PR317 21
1
PACIN TP
PACIN 1 2 5 1 2 @ @ 6 ACDET PC313 4
1
64.9K_0603_1% PC312 20 BQ24727VCC1 2

4
PC323 VCC PL302

ACON 1 2 7 IOUT
0.1U_0603_25V7K 10UH_PCMB104E-100MS_5.5A_20% PR320
2
3
2
1
1U_0603_25V6K
1
PQ311 100P_0603_50V8 19 0.01_1206_1%

PHASE
DTC115EUA_SC70-3 <42,48> EC_SMB_DA1 8 SDA
PU301 BATT+
BQ24727RGRR_VQFN20_3P5X3P5 LX_CHG 1 2 CHG
1 4
PR321 18 DH_CHG
HIDRV
5
6
7
8
2ACOFF-12 <42,48> EC_SMB_CK1
<42> ACOFF 1 9 SCL SA000051W00 2 3
1
PQ312
10K_0402_5% PR324 PC314
AO4466L_SO8
4.7_1206_5%
PR322
PR323 2.2_0603_5% 0.047U_0603_16V7M
1
BST_CHG SRP SRN
10U_0805_25V6K
10U_0805_25V6K
1 2 10 ILIM BTST 17 1 2 2 1
1
16251_SN
PR325 +3VALW 316K_0402_1%
3
PD303
PR326
LODRV
0_0402_5% 4
1
PC316
PC317
100K_0402_1% 16 2 1
GND
SRN
SRP
REGN
BM
2N7002KW_SOT323-3
2
2
PQ313 RB751V-40_SOD323-2
680P_0603_50V7K
11
1 12
13
14
15
3
2
1
1
1
D
PC319
10_0603_5%
6.8_0603_5%
2
BQ24727VDD
PR328
2 PC318
<48> BATT_OUT
PR327
G 1U_0603_25V6K
2
S
3
2
2
PC320 DL_CHG
B 0.1U_0603_25V7K B
2 1
CHGVADJ=(Vcell-4)/0.10627
1
Vcell CHGVADJ
1
PC321 @
4V 0V 0.1U_0603_25V7K PC322
2
2 0.1U_0603_25V7K
4.2V 1.882V
4.35V 3.2935V
BQ24727VDD
CC=0.25A~3A PR337
10K_0402_1%
1
IREF=1.016*Icharge 1 2 ACIN <16,42>

PR336
IREF=0.254V~3.048V PR335 10K_0402_1%
47K_0402_1%
VCHLIM need over 95mV PACIN
2
2N7002KW_SOT323-3
PQ316
1
ACPRN <50> D PR339

2
G 12K_0402_1%
2
S
3
A A
For disable pre-charge circuit.

CHARGER
0.1
5 4 3 2 1
5 4 3 2 1
Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO
2VREF_8205 PJ402
+3VALW P 2 2 1 1 +3VALW
@ JUMP_43X118
1U_0603_10V6K
D D
1
PJ403
PC401
+5VALW P 2 1 +5VALW
2
2 1
@ JUMP_43X118
PR401 PR402
13K_0402_1% 30K_0402_1%
1 2 1 2
PR403 PR404
RT8205_B+ 20K_0402_1% 19.6K_0402_1% RT8205_B+
1 2 1 2
PJ401 Typ: 175mA
B+ 2 1 +3VLP
0.1U_0603_25V7K
2 1
ENTRIP2
ENTRIP1
@ JUMP_43X118 PR405 PR406
PC405
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0603_25V7K
0.1U_0603_25V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
130K_0402_1% 66.5K_0402_1%
PC402
PC410
1 2 1 2
4.7U_0805_10V6K
1
1
PC403
PC404
PC406
PC407
PC408
PC409
2
8
7
6
5
5
6
7
8
PU401
2
2
PC411
ENTRIP2
FB2
TONSEL
FB1
ENTRIP1
REF
1
C PQ401 C
TPC8065-H_SO8
PQ402
25 P PAD
AO4466L_SO8
2
4 4
7 VO2 VO1 24
SPOK <48>
8 23 PR408 PC413
PR407 VREG3 PGOOD 2.2_0603_5% 0.1U_0603_25V7K
1
2
3
3
2
1
1 2 1 2 BST_3V 9 BOOT2 BOOT1 22 BST_5V 1 2 1 2
2.2_0603_5%
PL401 PC412 UG_3V 10
VFB=2.0V 21 UG_5V PL402
4.7UH +-20% PCMC063T-4R7MN 5.5A 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH_PCMB104E-4R7MS_5.5A_20%
1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1
8
7
6
5
1
LG_3V LG_5V
4.7_1206_5%
4.7_1206_5%
12 LGATE2 LGATE1 19
5
6
7
8
PQ403
PR409
PR410
SKIPSEL
AO4712_SO8
VREG5
PQ404
GND
VIN
NC
RT8205EGQW _W QFN24_4X4
EN
1 1
2
2
4
+ PC415 4 + PC417
13
14
15
16
17
18
1
1
150U_B2_6.3VM_R45M PR411 150U_B2_6.3VM_R45M
680P_0603_50V7K
TPC8A03-H_SO8
499K_0402_1%
680P_0603_50V7K
2 2
PC418
PC419
1 2
2
1
2
3
2
B+
3
2
1
1
100K_0402_1%
1U_0603_10V6K
VL
1
PC420
1
PR412
PC421
Typ: 175mA
4.7U_0805_10V6K
B B
2
ENTRIP1 ENTRIP2
2
2
For KB9012 RT8205_B+
<42,43> EC_ON
6
PR418
1
2.2K_0402_5% PQ405B
2 1 PQ405A 2N7002KDW -2N_SOT363-6
0.1U_0603_25V7K
2N7002KDW -2N_SOT363-6 2 5 2VREF_8205 +3.3VALWP OCP(min)=5.81A
2
PC422
+5VALWP OCP(min)=8.44A
<42,48> MAINPWON
1
PR413
0_0402_5%
2 1
PR414
100K_0402_1%
2 1
VL
1
2N7002W-T/R7_SOT323-3
PR415
1
200K_0402_1% D
49> ACPRN
PQ407
2 1 2 1 2 2 PQ406
G VS DTC115EUA_SC70-3
S PR416
40.2K_0402_1%
4.7U_0603_6.3V6M
3
A A
1
100K_0402_1%
1
1
PR417
PC423
@ @
3
2
<42,43> EC_ON
2
2
PQ408
DTC115EUA_SC70-3
@ @
For KB9012 3VALWP/5VALWP

3
Custom 0.1
@
5 4 3 2 1
A B C D
1.5V_B+ 1 2 B+
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
5
6
7
8
1
PC502
PC503
PC504
PC505
PQ501 1UH_FDSD0412-H-1R0M-P3_3.3A_20%
TPC8065-H_SO8
PL502
2
4
3
2
1
1
PR503 PC506 PL501 1
100K_0402_1% PU501 2.2_0603_5% 0.22U_0603_16V7K 1UH_PCMC063T-1R0MN_11A_20%

PR505 1 PGOOD VBST 10 BST_1.5V 1 2BST_1.5V-1 1 2 1 2 +1.5VP
PR501 2 1 2 9 DH_1.5V
0_0402_5% TRIP DRVH
LX_1.5V
4.7_1206_5%
1 2 3 EN SW 8
1
<42,45,46> SYSON 1
5
6
7
8
PR504
4 VFB V5IN 7 +5VALW
2
+
47K_0402_5%
PQ502 PC507
.1U_0402_16V7K
1
PC501 @
PR502
1 PR5062 5 6 DL_1.5V 220U_6.3V_M +1.5VP OCP(min)=15.6A

RF DRVL
1
PC508
2
470K_0402_1% 1U_0603_10V6K 2
PR507 11
2
TP PJ502
1000P_0603_50V7K
4
1
2 1 2 TPS51212DSCR_SON10_3X3 2 2 1 1
PC509
VFB=0.7V
@ JUMP_43X118
11.5K_0402_1%
1
TPC8A03-H_SO8
3
2
1
2
PJ503 +1.5V
PR508 +1.5VP 2 1
10K_0402_1% 2 1
@ JUMP_43X118
2 2
3 3
PU502 PL503
4
PJ505 1UH_PH041H-1R0MS_3.8A_20%
2 1 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
+5VALW
PG
2 1 PVIN LX +1.8VSP
@ JUMP_43X118
68P_0402_50V8J
9 PVIN LX 3
1
1
680P_0603_50V7K 4.7_1206_5%
1
1
PC510 8 PC511
SVIN
PR509
22U_0805_6.3VAM PR510
6 20K_0402_1%
2
FB 2
22U_0805_6.3VAM
22U_0805_6.3VAM
5
1 2
EN
1
NC
NC
PJ504
TP
PC513
PC514
FB=0.6Volt +1.8VSP 2 1 +1.8VS
2 1
<10,25,42,46,52,53,54> SUSP#
PC512
PR511
11
2
1 2 EN_1.8VSP @ JUMP_43X118
2
0_0402_5%
0.1U_0402_10V7K
2
PC515 @
SY8033BDBC_DFN10_3X3
1
PR512 1.8VSP max current=4A

1M_0402_5%
1.8VSP_FB
2
1
4
PR513 4
10K_0402_1%
2

PWR-+1.5VP/+1.8VSP
Custom 0.1
A B C D
5 4 3 2 1
+3VS PR601
1K_0402_5%
2 1
VID [0] VID[1] VCCSA Vout PJ602
+VCC_SAP
100K_0402_5%
0 0 0.9V H_VCCSA_VID1 <10> +VCCSAP 2
2 1
1 +VCCSA
1
TDC 4.2A
@ JUMP_43X118
PR602
0 1 0.8V Peak Current 6A
1 0 0.725V OCP current 7.2A
2 +VCCSA_PWRGD
H_VCCSA_VID0 <10>
1 1 0.675V
PR603
<42> SA_PGOOD
1K_0402_5%
output voltage adjustable network 2 1
D D
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
+VCCSA_VID0
+VCCSA_VID1
+5VALW
+VCCSA_PWRGD
VCCSA VID is 00 prior to VCCIO stability.
1U_0603_10V6K
2
PC601
PR604 PR605
10_0402_1% 0_0402_5%
1
2 1 +VCCSA_EN 1 2 +V1.05S_VCCP_PWRGOOD <53>
PC602
2.2U_0603_10V7K
1 2
18
17
16
15
14
13
PU601
PR606 PC603
VID1
VID0
PGOOD
EN
V5FILT
V5DRV
0_0603_5% 0.22U_0603_16V7K
12 +VCCSA_BT 1 2+VCCSA_BT_1 1 2
BST PL601
19
PGND 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
SW
11 +VCCSA_PHASE 1 2 +VCCSAP
20
PGND
22U_0805_6.3V6M
22U_0805_6.3V6M
0.1U_0402_10V7K
1
10
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
2200P_0402_50V7K
SW
2200P_0402_50V7K
21 PR607 @ @ @ @
0.1U_0603_25V7K
PGND
2
10U_0805_6.3V6M
10U_0805_6.3V6M
4.7_1206_5%
PC605
PC606
PC608
PC609
PC611
PC612
TPS51461RGER_QFN24_4X4
PC607
PC610
9
SW
22
PC614
1 2 2
1
2
VIN
PC613
PC615
PC616
8
SW
1
23 PC604
1
2 1 1 VIN 1000P_0603_50V7K
PJ601 7
2
+3VALW 2
2 1
1 +VCCSA_PWR_SRC +VCCSA_PWR_SRC 24
VIN
SW
C @ JUMP_43X118 25 C
COMP
MODE
TP
SLEW
VOUT
VREF
GND
1
6
@ PR608
2 1
33K_0402_5%
PC617 PR609
2 1 100_0402_5%
2 1
0.22U_0402_10V6K
0.01U_0402_25V7K
2
2 1 2 1
PR611
PC619
PC618 PR610 0_0402_5%
1
3300P_0402_50V7K 5.1K_0402_1% 2 1 +VCCSA_SENSE <10>
PJ603
+3VS +V1.05S_VCCPP_B+ 2 1
2 1 B+
@ JUMP_43X118
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
5
6
7
8
0.1U_0402_25V6
1
1
PQ601
PC621
2
TPC8037-H_SO8
PC620
PC622
PC623
PR612
2
100K_0402_5% PC624
0.22U_0603_16V7K 4
PR613
1 2 1 2
1
<53> +V1.05S_VCCP_PWRGOOD 0_0603_5%

PU602
@ 1 10 BST_+V1.05S_VCCPP @ @
3
2
1
PGOOD VBST
PR614 @ @ @ @
1 2 TRIP_+V1.05S_VCCPP 2 9 UG_+V1.05S_VCCPP PL602
TRIP DRVH @ 1UH_PCMC063T-1R0MN_11A_20%
66.5K_0402_1%
PR615 EN_+V1.05S_VCCPP 3 8 SW_+V1.05S_VCCPP 1 2
B
0_0402_5%
@
EN SW +V1.05S_VCCPP B
1 2 FB_+V1.05S_VCCPP 4 7 +V1.05S_VCCPP_5V
<10,25,42,46,51,53,54> SUSP# VFB V5IN +5VALW
RF_+V1.05S_VCCPP 5 6 LG_+V1.05S_VCCPP @
1
5
6
7
8
1
RF DRVL @
1
@ @ PC625 TP
11 PQ602
0.1U_0402_16V7K PC626 PR617
2
TPS51212DSCR_SON10_3X3 1U_0603_6.3V6M 4.7_1206_5%

2
0.1U_0402_10V7K
2
2
PR616 @ 4 +V1.05S_VCCPP PJ604 +V1.05S_VCCP
@ @
PC627
470K_0402_1% 2 1
1
PC628 2 1
2
1
@ JUMP_43X118
TPC8A03-H_SO8 1000P_0603_50V7K
3
2
1
2
@
@ 1
PC629 PR618
@ @
2 1 2 1 @ + PC631
150U_B2_6.3VM_R45M
PR619 1000P_0402_50V7K 1.2K_0402_1% 2

PR620
4.32K_0402_1% 0_0402_5% @
2 1 2 1 VCCIO_SENSE <9,53>
+3VS
@
@ VCCP_PWRCTRL = "High" , Vo = 1.05V (SNB)
2
PR621 PR622 VCCP_PWRCTRL = "Low" , Vo = 1V (IVB)

10K_0402_1% 71.5K_0402_1% PR623
100K_0402_5%
1
PR624
SSM3K7002FU_SC70-3
@ D
@ 0_0402_5%
PQ603
A 2 @ 2 1 A
VCCP_PWRCTRL <10>
G
S
.01U_0402_16V7K
3
2
1
PR625
PC630
100K_0402_5%
2
@
@
PWR +VCCSAP/1.0
@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
5 4 3 2 1
5 4 3 2 1
+1.5V
1
PJ701
1
D JUMP_43X118 D
@
22
PU701
1 VIN NC 8 +3VALW PJ702
+0.75VSP 2 2 1 1 +0.75VS
PC702 2 7
GND NC
1
4.7U_0805_6.3V6K @ JUMP_43X118
1
@ PR719 3 6 PC703
PR702 VREF VCNTL
2
0_0402_5% 1K_0402_1% 4 5 1U_0603_10V6K
VOUT NC
<10,46,54> CPU1.5V_S3_GATE 1 2
9
2
PQ701 TP PJ703
2N7002W -T/R7_SOT323-3 APL5336KAI-TRL_SOP8P8 2 1
2 1
PR703 @ JUMP_43X118
.1U_0402_16V7K
+0.75VSP
1
49.9K_0402_1% D +1.05VS_VCCPP PJ704 +1.05VS
10U_0603_6.3V6M
<10,46,54> SUSP
PC704
1K_0402_1%
1 2 2 2 2 1 1
10U_0603_6.3V6M
1
1
PC705
PC706
G
2
S PR704 @ JUMP_43X118
0.1U_0402_10V7K
2
1
PC701
2
PJ605 @ +V1.05S_VCCP
+1.05VS 2 2 1 1
C JUMP_43X118 C
PJ606 @
2 2 1 1
JUMP_43X118
PR710 Ivy Bridge CPU ES2 Using

1,52,54> SUSP# 60.4K_0402_1%
1 2
+1.05VS_VCCPP OCP(min)=20.75A
@ 10K_0402_1%
+3VS
2
.1U_0402_16V7K
1
PR709
PC707
100K_0402_1%
2
PJ705
100K_0402_1%
1
1.05VS_B+ 2 1
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2 1 B+
2
PR705
0.1U_0402_25V6
2
@ JUMP_43X118
PR706
1
PR715
PC719
PC717
5
0_0402_5% PR713 PC710
PC714
PC718
<52> +V1.05S_VCCP_PW RGOOD 1 2 2.2_0603_5% 0.1U_0603_25V7K PQ702
1
2
BST_1.05VS_VCCP
1 2 1 2
1
10.7K_0402_1%
17
16
15
14
13
PU702 4
PAD
PGOOD
EN
MODE
BST
2
PR707
1 12 LX_1.05VS_VCCP TPCA8065-H_PPAK56-8-5 PL701

0.1U_0402_25V6
3
2
1
B VREF SW 1.0UH +-20% PCMC104T-1R0MN 20A B
+1.05VS_VCCPP
1
12K_0402_1%
2 1
1
PC708
2 11 DH_1.05VS_VCCP
2
REFIN DH
2
1
PR708
1000P_0603_50V7K 4.7_1206_5%
5
VSSIO_SENSE_L PC720
<9,52> TPS51219RTER_QFN16_3X3 PQ703
PR712
PR717 0.01UF_0402_25V7K 1
1
DL_1.05VS_VCCP
330U_X_2VM_R6M
3 GSNS DL 10
1 2 +
1
PC709
TPCA8057-H_PPAK56-8-5
0_0402_5% 4
2
4 VSNS V5 9 +5VALW
COMP
1
PGND
TRIP
GND
3
2
1
PC715
<BOM Structure>
2
PC712
PR716
5
1
75K_0402_1%
PR714 1 2 1 2
1
PC713
<9,52> VCCIO_SENSE 1 2 10_0402_1% 0.01UF_0402_25V7K 1U_0603_10V6K
2
10_0402_1%
PR711
@
2
2
PC716
1000P_0402_50V7K
1
PR718
A A
1 2
10_0402_1%
2
PC721
1000P_0402_50V7K
1
PWR +1.05VS_VCCPP/+0.75VSP
Custom 0.1
5 4 3 2 1
A B C D
+3VS_VGA
10K_0402_5% +1.05VS +1.05VS_VGA PJ806
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
+1.05VS 2 1 +1.05VS_VGA
+5VALW 2 1
8 1
2
2
7 2 @ JUMP_43X118
2
6 3 @
1
PC867 5 PC868 PC869 PR838
10U_0805_10V6K 470_0603_1% +VGA_B+
2
2
TPC8A03-H_SO8 PQ807 10U_0805_10V6K 1U_0603_10V6K PJ801
PR853
PR852
PR864
PR854
PR855
PR856
PR857
PR858
PR859
PR860
PR861
PR862
1
2
PR840 PR851 2 1 B+
1
PQ808 0_0402_5% 2 1
20K_0402_1%
PR839 2N7002KW_SOT323-3
@ 1 2 @ JUMP_43X118
DGPU_PWROK# <46>
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
1
100K_0402_5% D
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
1
1 2 2 1 2 SUSP
SUSP <10,46,53>
1
PC870 G
1
@ @ @ @ @ @ PR848 PR849 @
PC801
PC803
PC804
S
3
0_0402_5% 0.1U_0603_25V7K 0_0402_5%
PC802
2
1 1
<46> DGPU_PWROK# 1 2 PQ809
2
1
D 2N7002KW_SOT323-3
5
PD808
<10,46,53> SUSP SUSP 1 2 2
G PQ801
RB751V-40_SOD323-2 1 2 PR841 @ S
N13P-GL:0.95V(VID5~0=101100)->NV by 2011.12.12
3
0_0402_5%
PR802
147K_0402_1% N13M-GE:0.875V(VID5~0=110010)->NV by 2011.11.3 4
<18> NVDD_PWR_EN 1 2VRON_VGA
PD809
1 2 PR804 PC805
RB751V-40_SOD323-2 2.2_0603_5% 0.22U_0603_10V7K TPCA8065-H_PPAK56-8-5
3
2
1
@ BOOT2_VGA 2 1 BOOT2_2_VGA 1 2
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
<23>
<23>
<23>
<23>
<23>
<23>
1 PR803 2 PL803
<10,25,42,46,51,52,53> SUSP# @0_0402_5% 2@ PR863 1 UGATE2_VGA 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
47K_0402_5%
<10,25,42,46,51,52,53> DPRSLPVR_VGA 1 2 PHASE2_VGA 1 4 +VGA_COREP
2
PR805
10K_0402_1% PC806 0.1U_0402_16V7K PR801 PQ802 PQ803 LF2_VGA 2 3
<BOM V2N_VGA
Structure>
5
1 2 DPRSLPVR_VGA 0_0402_5%
10K_0402_1%
3.65K_0805_1%
1
1
+3VS @ PR806 PR810
PR808
1 1
GPU_VID6
330U_D2_2V_Y
330U_D2_2V_Y
1
1.91K_0402_1% 1_0402_1%
PR809
CLK_ENABLE#_VGA PR807 + +
PC807
PC808
1 2
LGATE2_VGA 4 4
2
1
@4.7_1206_5%
2
PR811 2 2 @
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
SNUB2_VGA
1.91K_0402_1%
PR842
PR843
PR844
PR845
PR846
PR847
VSUM-_VGA
3
2
1
3
2
1
@
2
VSUM+_VGA ISEN2_VGA
<19,46> DGPU_PWROK
1
PR812 <BOM Structure>
100K_0402_5%
1
+3VS 1 2
PC809
@680P_0402_50V7K
2
2 PR813
147K_0402_1%
+VGA_CORE Under VGA Core 2
@ PR870
100K_0402_5%
2 1 +VGA_CORE Near VGA Core
1
+3VS 1 2 PC871
1U_0603_10V6K
40
39
38
37
36
35
34
33
32
31
1 2 PU801
<23,42> VGA_AC_DET
2
CLK_EN#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
PSI#_VGA
RBIAS_VGA
PR869 @
47U_0805_4V6
22U_0805_6.3V6M
22U_0805_6.3V6M
4.7U_0805_6.3V6K
1
1
0_0402_5%
PC811
PC812
PC813
PC814
PC815
PC816
PC817
PC818
30 1
BOOT2
1
PC819
PC820
PC821
PC822
29
UGATE2
1 28
2
@ @ PGOOD PHASE2
2 27
2
PR871 470K_0402_5%_TSM0B474J4702RE PSI# VSSP2 PR814 2
3 26
RBIAS LGATE2 VCCP_VGA
1 2 1 2 4 25 1 2 +5VS
VR_TT# VCCP 0_0402_5%
5 24
4.02K_0402_1% PH802 VW_VGA NTC PWM3
6 23
COMP_VGA VW LGATE1
7 22
FB_VGA COMP VSSP1
8 21
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
FB PHASE1
1 2ISEN3_VGA 9
ISEN3
1
1
UGATE1
PC824
PC825
PC826
PC827
PC828
PC829
PC830
PC831
PC832
PC833
PC834
PC835
10
BOOT1
ISUM+
ISEN2
ISEN1
ISUM-
VSEN
IMON
PC823 1U_0603_10V6K
8.06K_0402_1%
VDD
1000P_0402_50V7K
RTN
VIN
22P_0402_50V8J 41
@249K_0402_1%
2
2
AGND
PC836
ISL62883CHRTZ-T_TQFN40_5X5
PR816
PR817
11
12
13
14
15
16
17
18
19
20
PR818 @ PR865
2
499_0402_1% PC837 0_0402_5%

ISUM-_VGA
1 2FB1_VGA1 2 1 2
1
VDD_VGA
RTN_VGA
390P_0402_50V7K
PC838 PR820 PR819 @ 0_0402_5%
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
@0.1U_0402_10V7K
@0.1U_0402_10V7K
@0.1U_0402_10V7K
100P_0402_50V8J 1.15K_0402_1% @ PR815 IMON_VGA 1 2 +5VS @
1
0_0402_5% VSEN_VGA
PC839
PC840
PC841
PC842
PC843
PC844
PC845
PC846
1 2 1 2
1 2 PR821 0_0402_5% 1 2
11.3K_0402_1%
+5VS
0.047U_0402_16V7-K
2
VIN_VGA 1 2 PR866 GPU_IMON <42> PJ802
2
1
For 15W one phase 0_0402_5%

PC874
PR850
ISEN2_VGA +VGA_B+ 2 1
2 1
1 2FB2_VGA1 2 PR823
ISEN1_VGA 1_0402_5% @ JUMP_43X118
2
3
PC847 PR822 1 2 +VGA_B+ +VGA_COREP PJ803 +VGA_CORE 3
0.22U_0402_10V6K
0.22U_0402_10V6K
1
1
150P_0402_50V8J 33K_0402_1% +5VS 2 1

2 1
1
1
PC848
PC849
PC850
PC851
1U_0603_10V6K
0.22U_0603_25V7K
PR824 VSSSENSE_VGA <24> @ JUMP_43X118

68.1K_0402_1%
2200P_0402_50V7K
2
BOOT1_VGA
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2
5
PQ804
1
PC852
PC853
PC854
PC855
2
2
VSUM+_VGA UGATE1_VGA 4
VSUM-_VGA
1 2
@82.5_0402_5%
+VGA_COREP
PR827 PC856
1
PR825 2.2_0603_5% 0.22U_0603_10V7K TPCA8065-H_PPAK56-8-5

PR826
3
2
1
1
10_0402_5% 2 1 BOOT1_1_VGA 1 2
2.61K_0402_1%
PL804
PR828
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
<24> VCCSENSE_VGA 1 2
2
PHASE1_VGA 1 4 +VGA_COREP
2
PR829
VSUM_VGA_N001
0.22U_0603_10V7K
0.033U_0603_25V7K
1
0_0402_5% PQ806 LF1_VGA 2 3

<BOM V1N_VGA
Structure>
5
NTC_VGA
PC857 PQ805
1
1
330P_0402_50V7K
PC858
PC859
10K_0402_1%
3.65K_0805_1%
2
1
PR831
1 1
330U_D2_2V_Y
330U_D2_2V_Y
PR833
2
PR830 1_0402_1% + +
PR832
PC860
PC861
@0.01U_0402_25V7K
LGATE1_VGA 4 4
@330P_0402_50V7K
2
1
@4.7_1206_5%
PC863
PC864
11K_0402_1%
2
1
PC862 PH801 2 2
PR834
PR835 1000P_0402_50V7K 10K_0402_1%_TSM0A103F34D1RZ
SNUB1_VGA
0_0402_5%
2
3
2
1
3
2
1
<24> VSSSENSE_VGA 1 2 <BOM Structure> @ VSUM-_VGA
2
Layout Note: VSUM+_VGA

PR836 PR837 Place near Phase1 Choke ISEN1_VGA
10_0402_5% 1K_0402_1%
1
4 4
For N13M-GE(15W without turbo) 1 2 1 2 VSUM-_VGA
PC865
@:PR806,PR812,PC823,PC848,PC849,PR832, @680P_0402_50V7K
2
PC801,PC802,PQ801,PQ802,PQ803,PR804,
PC805,PC803,PR808,PR809,PR810,PC807,
PC804
1
PC866
POP:PR815,PC803 0.1U_0402_16V7K
2
PR816->120K(SD034120380)
PR820->1.69K(SD00000JB80)
PR822->22K(SD034220280)
PR837->866(SD034866080) Issued Date 2008/09/15 Deciphered Date 2012/07/11 Title
PC858->0.1uF(SE026104M80)
PC859->0.068uF(SE026683K80) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR - VGA_COREP
PR850->22.1K(SD034221280) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C38 Chief River Schematic 0.1
A B C D
5 4 3 2 1
PR915,PR946=200K(setting 113 degreeC)

PR915,PR946=8.25K(setting 93 degreeC)
PC902
1200P_0402_50V7K
1 PR901 2 FBA3 1 2 PC901 1 2
1000P_0402_50V7K
D PUT COLSE D
75K_0402_1%
10_0402_1% 680P_0402_50V7K .1U_0402_16V7K
TO GT
1
PR903 1 PR904 2
PC903
PC904
PR905
TRBSTA# 1 PR902 2 FBA1 1 2 PH901 Inductor
2P: 24K 24.9K_0402_1% PR906 PC906
1
1
1.21K_0402_1% 10.7K_0402_1% 220K_0402_5%_ERTJ0EV224J CSCOMPA 1 2 DROOPA 1 2 CSREFA
PC905 1P: 24.9K
2
PR908 PC907 PC908 2 PR907 1 NTC_PH203 1K_0402_1% 1000P_0402_50V7K
2
4700P_0402_25V7K 1 2 FBA2 1 2 1 2 165K_0402_1%
10_0402_1% 2P: 1.65K
680P_0402_50V7K PR910 10P_0402_50V8J PC909
1 PR909 2 1 2 COMPA1 1 2
1P: 1K
1K_0402_1% 6.04K_0402_1% 2200P_0402_50V7K CSREFA
PC910 TSENSEA
2
1 PR912 2 SWN1A 0.047U_0402_16V7K
2P: 21.5K 63.4K_0603_1% PR913 6.98K_0402_1%
1
CSP1A 1 2
1P: 15.8K SWN1A <56>
2
15.8K_0402_1%
PR937
CSCOMPA
1 2 PC911
<10> VCC_AXG_SENSE
2
200K_0402_1%
1PR914
0_0402_5% 1000P_0402_50V7K
1
PC912 PH904
PR915
PR954 1000P_0402_50V7K
CSREFA <56>
1
1 2 100K_0402_1%_TSM0B104F4251RZ
<10> VSS_AXG_SENSE
0_0402_5% PC914
1
CSP2A
CSP1A
1 2
TRBSTA#
DROOPA
CSSUMA
TSENSEA
COMPA
IMONA
FBA
.1U_0402_16V7K
DIFFA
ILIMA
+V1.05S_VCCP
PR918 2P: 36K

1 2
1P: 26.1K PUT COLSE
26.1K_0402_1%
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
+5VS 1 PR919 2 PU901 TO V_GT
C C
2_0603_5% HOT SPOT
VSNA
VSPA
DIFFA
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
PAD
TRBSTA#
6132_PWMA
PC915
1 2 6132_VCC
.1U_0402_16V7K
.1U_0402_16V7K
1 45 PR921 PC918
2.2U_0603_10V7K VCC PWMA BSTA1
2 44 1 2 BSTA1_11 2
VDDBP BSTA +5VS
130_0402_1%
54.9_0402_1%
PR920 3 43 2.2_0603_5% 0.22U_0603_25V7K

VRDYA HGA HG1A <56>
1
PR922 2
1 2VR_ON_CPU 4 42
<42> VR_ON EN SWA SW1A <56>
PR923
PC916 PC917 0_0402_5% VR_SVID_DAT1 5 41 PC919

SDIO LGA LG1A <56>
VR_SVID_ALRT# 6 40 BST2 1 PR924 2 BST2_1 1 2 2Phase: @
2
PR927 PR925 VR_SVID_CLK ALERT# BST2 2.2_0603_5% 0.22U_0603_25V7K

7 39 HG2 <56>
SCLK HG2 1Phase: install
1
0_0402_5% 95.3K_0402_1% 1 2 VBOOT 8 38 Option for
SW2 <56>
1
VBOOT NCP6132AMNR2G_QFN60_7X7 SW2

<9> VR_SVID_DAT 1 PR926 2VR_SVID_DAT1 1 2 10K_0402_1% ROSC_CPU 9
ROSC LG2
37 LG2 <56>
PC920 1 phase GFX PR928
CPU_B+ 1 2 VRMP 10 36 6132P_VCCP 1 PR930 2 1 2 0_0402_5%
<9> VR_SVID_ALRT# VRMP PVCC
VR_HOT# 11 35 0_0402_5% 2.2U_0603_10V7K
<9> VR_SVID_CLK VRHOT# PGND
0.01U_0402_25V7K
PR929 1K_0402_1% VGATE 12 34 LG1 <56> +5VS
2
VRDY LG1
1
13 33 CSP2A
+V1.05S_VCCP VSN SW1 SW1 <56>
PC921 14 32 PC922
+3VS VSP HG1 HG1 <56>
DIFF_CPU 15 31 BST1 1 PR931 2 BST1_1 1 2
CSCOMP
2
DIFF BST1
TRBST#
2.2_0603_5% 0.22U_0603_25V7K
DROOP
CSSUM
DRVEN
CSREF
1
COMP
TSNS
CSP3
CSP2
CSP1
PWM
IOUT
ILIM
1
PR932 @
FB
75_0402_1% PR933 +5VS
10K_0402_5%
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
3P: 73.2K
2
1 PR934 2
<42> VR_HOT#
2
COMP_CPU
2P: 41.2K
1
FB_CPU 41.2K_0402_1% Option for 3Phase: @
TRBST#
<16> VGATE
PR936 2 phase CPU PR935
DROOP
TSENSE
ILIM_CPU
1 2 VSN 3P: 22p 0_0402_5% 2Phase: install
<9> VSSSENSE 6132_PWM
1
0_0402_5%
IMON
PC923 2P: 10p
2
PR938 1000P_0402_50V7K CSP3
2
1 2 VSP PC924
<9> VCCSENSE
2
PR939 12.4K_0402_1%
0_0402_5% 1 2
.1U_0402_16V7K
IMVP_IMON
B PR941 B
PC926 CSP1 CSP2 1 6.98K_0402_1%
2 TSENSE
SWN2 <56>
3P: 330p 1 PR940 2 2 1 CSP2
1
2
1K_0402_1% CSP3
2P: 1000p
1
22P_0402_50V8J PC927 PR960 @
0.047U_0402_16V7K 6.98K_0402_1%
PR942 PC928 PR943 PC929 3P: 21K
2
1 2FB_CPU1 1 2 2 1COMP_CPU1 2 1
1
PR944 PC930 49.9_0402_1% 6.04K_0402_1% 2P: 12.4K CSREF
200K_0402_1%
1 2FB_CPU3 1 2 680P_0402_50V7K 1500P_0402_50V7K
PR946 1
2
10_0402_1% 3P: 6.04K CSP1 1 PR9452
CSREF <56> SWN1 <56>
CSCOMP
0.033U_0402_16V7K 6.98K_0402_1% PH902

2P: 4.32K
2
PR947 PR948 PC932 PC931
TRBST# 1 2 FB_CPU2 1 2 1000P_0402_50V7K 3P: 1500p0.047U_0402_16V7K PR961 @ 100K_0402_1%_TSM0B104F4251RZ
1
0.033U_0402_16V7K
6.98K_0402_1%
1
2P: 1200p
1
8.06K_0402_1% 806_0402_1% 3P: 2200p

PC933
2P: 3300p
1
CSSUM CSREF
2
3P: 348 3P: 3.65K PC934

1 2
2P: 1.21K 2P: 9.53K 1000P_0402_50V7K 1 PR949 2 SWN1
24.9K_0402_1%
130K_0603_1% PUT COLSE

2
.1U_0402_16V7K
TO VCORE
PC935
3P: 23.7K 1 2 PC936 1 PR951 2 SWN2

PR950
680P_0402_50V7K 130K_0603_1% HOT SPOT

1
2P: 24.9K
1 PR952 2NTC_PH201 1 PR953 2
1
75K_0402_1%
PR955 PC937 165K_0402_1%
CSCOMP 1 2 DROOP 1 2 CSREF PH903
PUT COLSE
1K_0402_1% 1000P_0402_50V7K 2 1
3P: 806 TO VCORE
Phase 1 220K_0402_5%_ERTJ0EV224J
2P: 1K
A Inductor A
<42> IMVP_IMON

PWR-CPU_CORE
Custom C38-G series Chief River Schematic 0.1
5 4 3 2 1
5 4 3 2 1
CPU_B+ CPU_B+
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
B+
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_25V7K
2200P_0402_25V7K
5
5
PL901
HCB4532KF-800T90_1812 PQ902
1
PQ901
PC938
PC939
PC940
PC941
PC942
PC943
PC944
PC946
1 2 CPU_B+
1
2
<55> HG1 4 <55> HG2 4
+
+VCC_CORE PC947 +VCC_CORE
220U_25V_M
PL902 2
TPCA8065-H_PPAK56-8-5 TPCA8065-H_PPAK56-8-5
3
2
1
3
2
1
D D
0.36UH_VMPI1004AR-R36M-Z03_30A_20% PL903
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
<55> SW1 1 4 <55> SW2 1 4
<BOM Structure>
1
2 3 2 3
5
PR956 PQ904 PR957
PQ903 4.7_1206_5% 4.7_1206_5%
2
PR958
4 V1N_CPU2 1 4 V2N_CPU 2 PR959 1 CSREF
<55> LG1 CSREF <55> <55> LG2
1SNUB_CPU1
SNUB_CPU2
10_0402_1%
10_0402_1%
SWN1 <55> SWN2 <55>
3
2
1
3
2
1
PC948
1
680P_0603_50V7K PC949
2
680P_0603_50V7K
2
C C
QC 45W CPU DC 35W CPU

VID1=0.9V VID1=1.05V
IccMax=94A IccMax=53A
Icc_Dyn=66A Icc_Dyn=43A
Icc_TDC=52A Icc_TDC=36A
R_LL=1.9m ohm R_LL=1.9m ohm
OCP~110A OCP~65A
CPU_B+
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_25V7K
B B
1
1
PC957
PC958
PC959
PC960
2
2
5
PQ907
<55> HG1A 4
PL905
+VCC_GFXCORE_AXG
3
2
1
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
<55> SW1A 1 4
<BOM Structure>
1
2 3
5
PQ909 PR967
V1N_GFX
4.7_1206_5%
2
55> LG1A 4
SNUB_GFX1
TPCA8057-H_PPAK56-8-5 2 PR971 1
CSREFA <55>
3
2
1
<BOM Structure>
10_0402_1%
1
PC968
680P_0603_50V7K SWN1A <55>
2
A A
QC 45W GT2 DC 35W GT2

VID1=1.23V VID1=1.23V
IccMax=46A IccMax=33A
Icc_Dyn=37A Icc_Dyn=20.2A Security Classification Compal Secret Data Compal Electronics, Inc.
Icc_TDC=38A Icc_TDC=21.5A Issued Date 2009/12/01 Deciphered Date 2012/07/11 Title
R_LL=3.9m ohm R_LL=3.9m ohm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE
OCP~55A OCP~40A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C38-G series Chief River Schematic
5 4 3 2 1
5 4 3 2 1
+VCC_CORE Below is 458544_CRV_PDDG_0.5 Table 5-8.

+VCC_CORE +VCC_GFXCORE_AXG
1 1 1 1 1
5 x 22 µF (0805)
PC1
PC2 PC3 PC4 PC5
Socket Bottom 5 x (0805) no-stuff
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM +VCC_GFXCORE_AXG sites
D
7 x 22 µF (0805) D
@ @
Socket Top 2 x (0805) no-stuff
sites
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 @ 1 1 1
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
@
PC6 PC7 PC8 PC9 PC10 PC11
10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM
2 2 2 2 2 2 2 2 2 2 2 2 2 2
+V1.05S_VCCP
+VCC_CORE +V1.05S_VCCP
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 @ @ @ @
PC25
PC26
PC27
PC28
PC29
PC30
PC31
PC32
PC33
PC34
PC35
PC20 PC21 PC22 PC23 PC24
2 2 2 2 2 2 2 2 2 2 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1 1 @ 1 1 1 1 1 1
2 2 2 2 2
PC36
PC37
PC38
PC39
PC40
PC41
PC42
PC43
2 2 2 2 2 2 2 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1
1 1 1 1 1 @ @ @
PC49
PC50
PC51
PC52
PC53
PC54
PC55
PC56
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2 2 2 2 2 2
2 2 2 2 2
1 1 1 1
330U_D2_2VM_R6M
330U_D2_2VM_R9M
330U_D2_2VM_R6M
330U_D2_2VM_R9M
@ @
PC57
PC58
PC59
PC60
+ + + +
C C
2 3 2 3 2 3 2 3
1 1 1
330U_D2_2VM_R9M
330U_D2_2VM_R9M
330U_D2_2VM_R9M
1 1 1 1 1 @ @
PC66
PC67
PC68
@ + + +
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2 3 2 3 2 3
1 1 1 1
@ @ <BOM Structure> <BOM Structure>
PC69 PC70 PC71 PC72
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2
+VCC_CORE
1 1 1 1
+ PC73 + PC74 + PC75@ + PC76@
330U_D2_2VM_R9M 330U_D2_2VM_R9M 330U_D2_2VM_R6M 330U_D2_2VM_R6M

B 2 3 2 3 2 3 2 3 B
1 1
+ PC77 + PC78
330U_D2_2VM_R6M 330U_D2_2VM_R9M
2 3 2 3
A A

PWR - PROCESSOR DECOUPLING
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C38-G series Chief River Schematic 0.1
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase
add PR865 for ISL62883 one phase solution and 2011.08.29 DVT
1 unpop for two phase solution. P54 add PR865
D D
unpop PR315,PR316 for SMBus SPEC. unpop PR315,PR316 2011.08.29 DVT
2 P49
3 delet PSI#_VGA for NV chip. P54 2011.10.14 DVT2
change NTC_V pull high voltage from +3VLP to +3VALW P48

4
C C
9
10
11
12
13
14
B B
15
16
17
A A

PIR (PWR)
Custom 0.1
5 4 3 2 1
5 4 3 2 1
COMPAL CONFIDENTIAL
MODEL NAME: Power Sequence Block Diagram
PCB NAME: LA-7981P
D REVISION: D
DATE: 2011/07/13 10
PCH_PWROK
AC A1
MODE VIN +3V_PCH
V V
A2 A3 B5 +5V_PCH
VV
A5 3
V
PU301 PU401
V
B+
+3VALW B7 3 3
BATT BATT V 10
+5VALW
MODE
B1
B2
B+ B4 V PCH_PWROK
V SYS_PWROK 15 14 VGATE
V
EC 4
PQ2 11
PCH_RSMRST#_R PM_DRAM_PWRGD
V
V V PCH
B3 A5 B7 5 12
PBTN_OUT# H_CPUPWRGD
CPU
V V
13 SVID
V
C C
51ON# EC_ON
PM_SLP_S3#
PM_SLP_S4# PLT_RST# 16
PM_SLP_S5#
A4 B6 PM_SLP_SUS# 6
DGPU_PWROK
V
V
ON/OFF
SYSON 7 SYSON#
V
+1.5V
PU501
DGPU_PWR_EN
SUSP#,SUSP 8
(DIS)
V
PU601 U38
8b
B +VCC_SA +5VS B
(DIS)
V
V
PU702 U39
8a
+V1.05S +3VS DGPU
V
V
V
PU602 Q8
+V1.05S_VCCP +1.5VS
PU701
V
SA_PGOOD 8a +0.75VS
13 SVID
VR_ON 9 PU901
V
+VCC_CORE
A A
14 VGATE

Power sequence
Custom 0.2
LA-7981P
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 2 for HW PIR
1 GPU 13M GPU Device loss (Pcie lan x8 issue) 8 Add R43 DVT
D D
2 HDD no function 40 Add R550 DVT
3 10/100 lan no function & change to overclocking mode 37 ADD R1372 ; DEL R31 DVT
4 For DGPU_PWROK leakage issue.(Let timing +5VS > +3VS) 46 Change C726 from 0.1uF to 0.01uF DVT
Change R56 from 15K to 4.7K
5 For S3 can't wake up 10 change R885 from 0 ohm to 15K DVT
6 Can unstuff RV66 for N13P-GL & as NV DG 27 RV66 change to N13M@ DVT
7 GPU N13P-GL QS sample change strap 32 RV94 change from 45.3K to 10K DVT
8 PCH 25Mhz for vender crystal test report change CL to 12pF 15 C196;C197 DVT
C C
9 GPU 27Mhz for vender crystal test report change CL to 15pF 23 CV37;CV38 DVT
10 EC_LID_OUT# internal PD 20K, follow ORB change R230 from 10k to 1K 19 R230 DVT
11 For GPIO70;GPIO71 voltage level issue ( internal Pull High 20k ) 19 R705;R706 Change from 10K to 200K DVT
12 for DVT board ID Change R695 from 33k to 18k 42 R695 DVT
13 LAN Surge test fail change P/N from SP050006E00 to SP050006W00 27 T1;T2 DVT
14 Del ODD Power Control function component 40 R568;Q100;R675;C607;Q99 DVT
15 AO4430L(SB000007O10)EOL Change to AO4304 (SB00000RV00) 46 U49 DVT
16 Del (PCH AUX Power) Reserve component no use 46 C780;C781;C782;C783;R778;Q120;U40 DVT

B B
17 PCH(U4) P/N Change from SA00004NQ30 to SA00004NQ80 14 U4 DVT
18 NV-GPU (U65)P/N change N13M from SA00004V000 to SA00004V010

N13P Keep SA000051A00 23 U65 DVT
19 EXT USB 3.0 IC PCIE_WAKE# ; CLKREQ_USB30# leakage on S4 45 Swap Q125;Q121 pin1 & pin3 DVT
20 No function 45 DEL R769 DVT
21 add LAN LDO mode function 37;38 ADD R65;R596;R1449;R1380 DVT
22 USB_OC0# Share with USB_OC4# due to same power switch 18 short USB_OC0#;USB_OC4# ; del R267 DVT
23 Add Capsensor B/D Conn. For best buy use 42 ADD JCAP1 Conn.
DVT
A A

HW-PIR1
Custom 0.1
LA-7981P
5 4 3 2 1
5 4 3 2 1
24 L1 change to 1 ohm R 20 L1 change to R footprint DVT

D D
25 Reserve 0 ohm for CMOS Camera shake 33 add R296 0 ohm DVT
26 Reserve 0 ohm for U49 MOS VGS 20V will burn out issue 46 add R784 0 ohm DVT
27 For HDD +5VS Power plant del C601; DVT

change C598 pin1 power name for good power plant 40 change from +5VS to +5V_HDD ;DEL C601
DVT
28 For Audio jack support APPLE and NOKIA function Reserve 43 add R684;R685;R688;R686 0ohm R
DVT
10,20 C124;C125;C126;C127;C130;C221;C215;C395; DVT

For standard part cost down change 10uF 0805 type to 0603 type 21,33 C231;C519;C937;C953;C954;C591;C608;C602;
29
37,39 C720;C721;C723;C724;C782;C783;C717;C718;
40,46 C856;C852;C851;C853 DVT
C C
30 change Crystal foot print follow standard parts from 5032 to 3225 package 15;23; DVT
37 Y2;Y6;YV1
7;8; DVT
10;15 R40;R60;R77;R144;R190;R193;R198;R181;R185;
31 change 0ohm to short-pad (R0402_0ohm) R265;R538;R498;R500;R583;R614
16;20; DVT
33;36;
40;43
DVT
32 Reserve BT_DISABLE (GPI022) for combo card(BT+WLAN) 19 ADD R892;R897 DVT
33 U35;U36 Change footprint without thermal PAD type 44;45 U35;U36 DVT
34 PU 10K with 3V3 on N13P-GL/ for CEC signal 24 RV230 DVT
35 VGA_GPIO3;VGA_GPIO16 change connect DPRSLPVR_VGA to PSI#_VGA 23;54 RV113;RV114 DVT

B B
36 Fix VGA power on CLKREQ has drop (QV2 gate add 0.1uF) CV42 DVT
23
37 LED5 和LED2 Location sawp ; Location name D9 change to LED6

43 LED2;LED5;LED6 DVT
38 For Lan surge fail add 0 ohm on MDO2-;MDO2+;MDO3-;MDO3+ 38 R304;R305;R306;R307 DVT
39 Change UV2 PN from SA007080B90 to SA00000OH00 23 UV2 09/28 DVT
40 Change 2M BIOS ROM from SA00003FO00 to SA00003FO10 14 U6 09/29 DVT
41 45
Correct PCIE_PRX_DTX_P4/N4 of U32 (SWAP) U32 10/03 DVT
42 Reserve +5VS to JCR1, add R689 ,R690 43 R689 (@),R690

10/03 DVT
A A
43 10/04
Update Power sheet of 1003 version 47~58

HW-PIR2
Custom 0.1
LA-7981P
5 4 3 2 1
5 4 3 2 1

5,6,7,
44 CPU Symbol Update Location : Jcpu1 PVT
D
8,9,10,11 D
45 Change 10P 50V Cap from 1206 to 0603 38 Location : C973 PVT
46 S3 Reduction 53 Reserve PR719 for 0.75V PVT
47 LAN CO-lay x1 GDT & 75ohm

38 Location : R308,R304,R305,R306,R307,DL1,DL2,DL3,DL4 PVT
48 R750 for Power request 42 Location :R750 PVT
49 JUSB3 From 4PIN TO 6 PIN FOR VOLTAGE DROP 44 Location : JUSB3

PVT
C C
50 Add C535 100pF on +3VLP for ESD request - Pony 42 Location : C535 PVT
51 FOR TP POWER SOLUTION 42 Location : R598.R603 PVT2
52 FOR POWER REQUEST 42 Location : R738 PVT2
Location : C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,
C11,C12,C13,C14,C15,C16,C17,C18,C19,C20,
5 C21,C22,C23,C24,C25,C26,C27,C28,C29,C30,
C31,C32,
52 Change C from 0.22Uf to 0.11uF CV6,CV7,CV8,CV9,CV10,CV11,CV12,CV13,CV15, SVT
23 CV17,CV19,CV14,CV16,CV18,CV20,CV22,CV24,
CV26,CV21,CV23,CV25,CV27,CV29,CV31,CV33,
CV28,CV30,CV32,CV36,CV41,CV34,CV35,
B B
A A

HW-PIR2
Custom 0.1
LA-7981P
5 4 3 2 1
www.s-manuals.com

Lenovo G580 Compal La-7981p r1.0 Schematics

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Lenovo G580 Compal La-7981p r1.0 Schematics

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A B C D E

QIWG5/QIWG6 DIS M/B Schematics Document

Security Classification Compal Secret Data Compal Electronics, Inc.

Compal confidential ZZZ ZZZ1 ZZZ2 ZZZ3 ZZZ4 QIWG5

Security Classification Compal Secret Data Compal Electronics, Inc.

Board ID PCB Revision Full ON HIGH HIGH HIGH HIGH ON ON ON ON

+5VALW +1.5V +VCC_CORE

For QIWG5 (14") 14@

SMBUS Control Table

Hot plug detect for IFP link C

GPIO3 OUT H Panel Power Enable

GPIO11 OUT - GPU VID0 Device ID

GPIO13 OUT - GPU VID5 N13M-GE

GPIO15 IN Hot plug detect for IFP link C

1. all power rail ramp up time should be larger than 40us

Security Classification Compal Secret Data Compal Electronics, Inc.

PEG_ICOMPI and RCOMPO signals should be

PCI EXPRESS* - GRAPHICS

<16> FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_C_N5 C11 1 2 0.1U_0402_10V7K PCIE_CTX_GRX_N5

PEG_TX#[14] PCIE_CTX_GRX_C_N0 C16 PCIE_CTX_GRX_N0

PEG_TX[6] PCIE_CTX_GRX_C_P8 C24 N13P@

Security Classification Compal Secret Data

T48 H_CATERR# AL33 CATERR#

<19> H_THRMTRIP# AN32 THERMTRIP# DDR3 Compensation Signals

JTAG & BPM

R29 AL35 XDP_DBRESET# R28 2 1 1K_0402_5% +3VS

2 BPM#[1] XDP_BPM#2 T91

1 Buffered reset to CPU

<16> SYS_PWROK 1 R880@ 2

Security Classification Compal Secret Data Compal Electronics, Inc.

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY A

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

<6> H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 DDR3_DRAMRST# <12,13>

CFG Straps for Processor

Interl request AH26 short GND

1: Normal Operation; Lane # definition matches

Display Port Presence Strap

R82 1 @ VSS_AXG_VAL_SENSE VAXG_VAL_SENSE RSVD39

F23 1K_0402_1% 1K_0402_1%

1: (Default) PEG Train immediately following xxRESETB

Security Classification Compal Secret Data Compal Electronics, Inc.

JCPU1F POWER +V1.05S_VCCP

PEG AND DDR

VCC62 VIDALERT# VR_SVID_ALRT# <55>

VSS_SENCE 100ohm +-1% pull-down to GND near processor

TYCO_2013620-2_IVY BRIDGE Security Classification Compal Secret Data

DDR3 -1.5V RAILS

H23 +VCCSA_SENSE <52> +3VS

VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 <52>

@ 1 1 1 1 1 A2 C24 R75 R76 @

A IVY Bridge drives VCCIO_SEL low A

Security Classification Compal Secret Data

AT35 VSS1 VSS81 AJ22

Security Classification Compal Secret Data Compal Electronics, Inc.

+VREF_DQ_DIMMA +1.5V +1.5V

DDR_A_D3 DQ2 DQ6 DDR_A_D7

A 201 202 SMB_CLK_S3 A

1 1 203 VTT1 VTT2 204 +0.75VS

205 206 0.65A@0.75V

Security Classification Compal Secret Data Compal Electronics, Inc.

DDR_B_D8 VSS7 VSS8 DDR_B_D12

<7> DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB

R97 10K_0402_5% 203 204 +0.75VS