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2017 IEEE 7th International Advance Computing Conference

Low Power and High Speed Optimized 4-bit


Array Multiplier using MOD-GDI Technique
Pinninti Kishore P. V. Sridevi K. Babulu
Dept. of ECE Dept. of ECE Dept. of ECE
VNRVJIET Andhra University College of Engg. University College of Engg.
Hyderabad, India Visakhapatnam, India JNUK, Kakinada, India
kishore_p@vnrvjiet.in pvs6_5@yahoo.co.in kapbbl@gmail.com

Abstract— Multipliers are the most commonly used elements in to achieve portable digital applications with low cost. This
today's digital devices. In order to achieve high data throughput paper proposes a technique known as MOD-GDI technique
in digital signal processing systems, hardware multiplication is the
which is used to reduce the transistor count, propagation
important factor. Depending on the applications which are
delay and total power dissipation in compared with the
emerging with the electronics devices, various types of multipliers
are emerged. Among all the multipliers, the basic multiplier is existing techniques like CMOS and GDI techniques.
Array Multiplier. This paper aims at design of an optimized, low Initially fundamental blocks like two input AND gate, Half
power and high speed 4- bit array multiplier by proposing Adder and Full Adders are designed and then by using these
Modified Gate Diffusion Input (MOD-GDI) technique. With this blocks design of 4 bit aarray multiplier is carried out.
technique the total propagation delay, power dissipation, and no.
of transistors required to design are much more decreased than This paper initially describes the operation of MOD-GDI
compared to the Gate Diffusion Input (GDI) and CMOS
and their basic functions in section II. Then the design of
techniques. Simulations are carried out on mentor graphics tools
with 90nm Process technology.
fundamental logic blocks like 2 input AND, 2 input XOR, 2
input OR gates and half adder which are used in multiplier
Keywords—GDI; Mod-GDI; Low power; Array Multiplier;
design are discussed in section III along with an optimized
full adder design. In section IV the design of proposed 4 bit
I. INTRODUCTION Array Multiplier using the AND gates, Half adders and Full
With an enormous increase in the development of adders is discussed. Finally in section V, simulation results
portable devices and digital applications, the demand for and results comparison with existing techniques is described
compact implementation of the devices, speed and low followed by conclusion in section VI.
power dissipation are being increased by numerous research
II. BASIC MOD-GDI FUNCTIONS
efforts[1][2]. In various processors, Multiplier Circuits are
The MOD-GDI technique is adopted from the basic GDI
mostly used in computational architectures like ALU’s,
technique [4].This technique is a new technique which used
Image processing, DSP processors etc. The important
to design the low power digital circuits. The MOD-GDI
factors like area, total power dissipation and propagation
technique is mainly used to reduce the total power
delay are the leading factors to analyze the performance of
dissipation, propagation delay and also the transistor count.
these processors. So the designers concentrate on to meet up
All these parameters are also achieved using GDI technique
these constraints as stated before. There are many designs of
but due to some limitations of GDI technique like additional
Multipliers which are proposed. Of them the basic
circuitry in order to give the inputs to the GDI circuits and
Multiplier is the Array Multiplier. This multiplier is
difficulty in fabrication process.
designed based on the basic Mathematical multiplication
method. In order to achieve the low power parameters,
many different techniques were proposed. Some of them
were Pseudo NMOS [3],C2MOS, Dynamic CMOS, Domino
logic , Pass transistor, transmission gates CMOS logic etc.
Though these techniques have been proposed in order the
reduce the total power dissipation but at the same time it
was observed that propagation delay, total area were
increased drastically. Therefore these techniques have failed Fig.1.Basic structure of Mod-GDI

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DOI 10.1109/IACC.2017.98
Fig. 1. shows the basic structure of MOD-GDI cell TABLE III. TRANSISTOR COUNT OF DIFFERENT PRIMITIVE GATES
which is similar to the basic GDI cell, both the designs
Primitive Transistor Count
consists of three input terminals namely G, P and N. In Gates CMOS GDI MGDI
GDI[5] both the substrates of the PMOS and NMOS are
INVERTER 2 2 2
connected to the source where as in the MOD-GDI the
AND 6 2 2
substrate of PMOS is connected to VDD and substrate of OR 6 2 2
the NMOS is connected to the GND. Most of the complex NAND 4 4 4
circuits can be replaced with less transistor count, keeping NOR 4 4 4
the functionality and the output swing constant. Let us see XOR 12 6 4
XNOR 14 6 6
the input configuration for different primitive logic
functions which can be obtained using the MOD-GDI
technique in the Table I. TABLE IV. PROPAGATION DELAY OF DIFFERENT PRIMITIVE GATES
Primitive Propagation delay
The input configuration for the inverter is same for the Gates
CMOS GDI MGDI
CMOS and GDI techniques, so there will be no difference in In ns In ns In ns

the power dissipation. Other remaining function INVERTER 20.7 20.8 24.25
configurations vary when compared with other technique AND 30.5 42.7 19.95
designs. The input configuration for the EX-NOR and EX- OR 29.69 48.7 18.08
OR gates are the basic configuration. The proposed EX-OR NAND 20.57 76.13 20.49

and EX-NOR [6][7] gates can be discussed in next section. NOR 40.97 19.0 19.0
XOR 102.5 78.3 29.15
In Table II, the comparison of the total power dissipation
XNOR 20.4 28.1 14.9
reading with respective to all other techniques is shown.
From the table it is described that inverter has same total III. PRELIMINARIES
power dissipation in all the three cases because the basic A. AND gate, EX-OR gate and EX-NOR gate using the
structure is same for inverter. Table III and Table IV depicts
MOD-GDI technique
the no. of transistors and total propagation delay of various
logic gates. Table I. Input configurations for different logic Fig. 2 , Fig. 3 and Fig. 4 shows the efficient designs of
functions two input AND gate and EX-OR gates respectively using
the MOD-GDI technique. When compared to the CMOS
N NS P PS G D Function
designs of the AND gate and EX-OR gates the area and also
the speed of the gates is optimised. In addition to that the
0 0 1 1 A Al INVETER
power dissipation is also consumed as seen in the Table II.
B 0 0 1 A AB AND
A 0 B 1 A A+B OR
A1 0 A 1 B A1 B+AB1 EX-OR
A 0 A1 1 B AB+A1 B1 EX-NOR
1
0 0 B B A AB FUNCTION
C 0 B 1 A A1B+AC MUX

TABLE II. COMPARISON OF TOTAL POWER DISSIPATION WITH RESPECTIVE


TO ALL OTHER TECHNIQUES

Primitive Total power dissipation


Gates CMOS GDI MOD-GDI
INVERTER 8.2774 pw 8.2774 pw 8.2774 pw
AND 39.6428 ȝw 40.3738 nw 6.5160 pw
OR 44.0824 ȝw 40.3738 nw 6.5160 pw
NAND 0.1641 ȝw 48.5046 pw 14.7934 pw
NOR 1.9706 ȝw 48.5046 pw 14.7934 pw Fig. 2. Two input AND gate using Mod-GDI
XOR 85.1884 ȝw 96.6106 nw 13.0320 pw
XNOR 85.7694 ȝw 49.9776 nw 21.3099 pw

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Fig. 5. 1 –Bit Half adder using AND and EX-OR gates.

Fig. 3. Two input EX-OR gate using Mod-GDI The 1-bit Full adder is also designed using the MOD-GDI
technique. The Logic equations for the 1- bit Full adder are
shown in Eq. (3) and Eq. (4).

SUM = A ْ B ْ Cin (3)

CARRY = A (A ٖ B ) + Cin (A ْ B )

= A (A ْ B )l + Cin (A ْ B ) (4)

The SUM for the proposed 1 –bit full adder can be


implemented by cascading the two EX-OR gates and the
CARRY can be implemented by the Eq. (4) as it in the form
of S1A+ SB which is the logic function for the 2 X 1
MUX. As the 2 X 1 MUX shown in the Fig. 6. can be
implemented using MOD-GDI with minimal transistor
count of 2 transistors , the Proposed full adder circuit gets
optimised . The proposed full adder is as shown in the Fig.
Fig. 4. Mod-GDI based two input EX-NOR gate 7.

B. Logic Equations for Half adder and Proposed Full adder


The Eq. (1) and Eq. (2) are the Boolean equations for
implementing 1- bit the half adder.

SUM =A ْB (1)

CARRY = AB (2)

The sum is obtained by giving the two inputs A and B to


the EX –OR gate and the carry is obtained using the AND
gate. The design of the Half adder is shown in the Fig. 5.
Fig. 6. Mod-GDI based 2 x 1 MUX

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Fig. 7. Mod-GDI based 1- Bit Full adder

IV. PROPOSED ARRAY MULTIPLIER


The most of digital multiplier follows the most basic level
of multiplication which is done by the series of bit shifts and
bit additions. Both the multiplier and the multiplicand are
given to the multiplier and are combined to get the final
result. There are many number of multiplier
implementations some are power consuming and are
maintained with high seed and accuracy. Among them the
most basic Multiplier is the Array multiplier. In this section
the 4-bit Array Multiplier is discussed.

A. Array Multiplier
The basic characteristic about the array multiplier
architecture is its regular structure which is shown in the
Fig. 8. The advantages of the Array multiplier is it is easy to
layout the architecture as the 1- bit adders are associated in
an array. In an N X N Array multiplier the AND gates
compute the partial products aibi terms simultaneously.
Those terms are summed by n half adders and n(n-2) full
adders [8][9]. So the major components of the Array
multiplier are AND gates, half adders and Full adders. The
schematic design of the array multipliers using the MOD –
GDI technique is shown in the Fig. 9 where the X and Y Fig. 9. Schematic of proposed 4 x 4 –bit Array multiplier
input have replaced by A and B.

V. RESULTS AND ANALYSIS


The simulation analysis of the 4 x 4 –bit Array multiplier
is done using th Mentor Graphics Pyxis schematic tools.
The inputs given to the Array multiplier is given as shown
in the Fig. 10. To test the functionality of the 4 x 4 –bit
Array multiplier ,the inputs given to it is as follows :
X[3:0]= 1010 and y[3:0]=1010 . The outputs after the
computation is completed are obtained at p[7:0]. The
expected outputs for the given inputs as stated above is
p[7:0]=01100100.

The waveforms obtained after the simulation process is


done is shown in the Fig. 11 . According to the waveforms
Fig. 8. Block diagram of 4 x 4 –bit Array multiplier the output obtained is p[7:0]=01100100 which is exactly the

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expected output ,so the functionality of the 4 x 4 –bit Array and less area without losing the functionality of an ideal
multiplier is achieved. The comparison of the total power array multiplier. From the Table V, it is understood that
dissipation and the transistor count of the 4 x 4 –bit Array MOD- GDI array multiplier dissipates the very less power.
multiplier using the CMOS and the Mod-GDI Technique Also circuit complexity is reduced in terms of number of
results are given in the Table V. transistors required and has low propagation delay. It is also
found that the work in [9], with also proposed the multiplier
by using MOD-GDI technique. But, the proposed multiplier
in this paper gave better results than [9].This is because of
novel in the design of full adder. Further this work can be
extended to design of ALUs and processors that are used in
signal processing applications.

REFERENCES
[1] N. Weste and K. Eshraghian, “Principles of CMOS digital design‫”ۅ‬,
Pearson Education, Addison-Wesley, 2002.
[2] W. Al-Assadi, A. P. Jayasumana, and Y. K. Malaiya, “Pass-
transistor logic design”, Int. J. Electron., vol. 70,.pp. 739–749,
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[3] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen , “Low-power
CMOS digital design”, IEEE J. Solid-.State Circuits, vol. 27, pp.
473–484, 1992.
[4] A. Morgenshtein, A. Fish, I.A. Wagner, 2002, "Gate- Diffusion
Input (GDI) – A Power Efficient Method for Digital Combinational
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Novel Low Power and Area Efficient Carry-Lookahead Adder using
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[8] Pinninti Kishore, P.V.Sridevi, K.Babulu,"Low Power and Optimized
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Fig. 11. Output waveforms of 4 x 4 –bit Array multiplier for the given Engineering science and Computing,pp 1568-1571, 2015.
Example

TABLE V. COMPARATIVE ANALYSIS OF 4 X 4 –BIT ARRAY MULTIPLIER


Type of Parameter CMOS GDI MOD-GDI
Adder
Total power
4.23 mw 3.56mW 492.39pw
dissipation
Array Propagation
270ps 98.98ns 214ps
multiplier Delay
Transistor
392 144 144
Count

VI. CONCLUSION
The MOD-GDI technique was proposed and verified with
CMOS and GDI techniques and is shown that this technique
is better than the other techniques. Though the GDI and the
MOD-GDI were similar, to overcome the limitations of GDI
the MOD-GDI was proposed. The proposed half adder and
full adder were used in the 4 x 4 array multiplier in order to
achieve less power consumption, reduced propagation delay

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