EEE360/371/461 Report 1

THE UNIVERSITY OF SHEFFIELD

Department of Electronic and Electrical Engineering
3rd Year Individual Project
Project Initialisation Document
Student Name Ahmad Firdaus Bin Rosli
Project Title Phase Locked Loop in Grid Connected Converters
Supervisor Professor Jiabin Wang Second Marker

Description and aims of Project:

Description
Due to the increasing development of renewable energy sources, use of grid connection network are
getting more attention each year as it is often used to boost the application of local power generation
system such as photovoltaic cells in solar panels, tidal wave energy generator, and wind turbine
generator that cannot supply constant power due to changing of weather conditions [1]. Not to
mention all these energy sources come in different phase and magnitude. Phase Locked Loop (PLL)
contributes a large part in connected grid power system because of its functionality in synchronizing
the phase from the reference signal to match the grid’s phase [2] for normal operation and control
of the converters’ execution.
Project aim
This project aims to incorporate phase locked loop system in connected grid converter. Connected
grid converted ranges from renewable energy sources like wind energy, hydroelectric energy and
solar energy from photovoltaic cells. MATLAB will be used to simulate the effectiveness of chosen
phase locked loop when connected to grid with converter.

Page 1 of 8
EEE360/371/461 Report 1
Literature review:

To begin with there are various types of PLL that existed throughout the years but all of those are
based on the basic phase-locked loops shown in Figure 1

Figure 1- Operational Concept

The basic block diagram is to illustrate the operating concept of PLL. PLL consist of phase detector
(PD), a loop filter (LF) and voltage controlled oscillator. The input can be any signal from the source.
The phase detector then compare the phase of input signal and phase of voltage controlled oscillator.
The comparison will produce a phase difference that will be passed to loop filter to extract DC
component from the phase error. The DC component will be amplified to be passed to VCO to
generate the frequency of output signal [3]. The phase will be integrated to become a phase of output
signal. This cycle of phase comparison will continue until phase difference of input and output signals
become zero. When this happens, both of input and output signal have the same phase hence are
locked.

u ũ
ũ
v

Figure 2- Simple PLL

As shown in Figure 2, phase detector unit is a multiplier whereas loop filter is a low pass filter and
VCO contains proportional integral controller, an integrator and sinusoidal function. Assuming input
signal 𝑢 = 𝑈𝑚 𝑐𝑜𝑠𝜃𝑔 with phase 𝜃𝑔 = 𝜔𝑔 𝑡 + ∅𝑔 and for the output signal 𝑦 = 𝑠𝑖𝑛𝜃 with phase 𝜃 =
𝜔𝑡 + ∅ , the output of phase detector unit is

ũ = 𝑢𝑦 = 𝑈𝑚 𝑠𝑖𝑛𝜃𝑐𝑜𝑠𝜃𝑔
𝑈𝑚 𝑈𝑚
= sin(𝜃 − 𝜃𝑔 ) + sin(𝜃 + 𝜃𝑔 )
2 2

Page 2 of 8
EEE360/371/461 Report 1
Based on the equation above, it is apparent that the first term that has phase difference is a low
frequency term whereas the other term is a high frequency which will be filtered out by the low pass
filter located in loop filter. Hence the output d of LF would be
𝑈𝑚
𝑑= sin(𝜔 − 𝜔𝑔 ) 𝑡 + (∅ − ∅𝑔 )
2
That will be put into a PI controller to produce estimated frequency 𝜔 = 𝜃̇ until 𝑑 = 0. In steady
state, d will be driven to zero and ∅ = ∅𝑔 , 𝜔 = 𝜔𝑔

The importance of having PLL in a grid connected converter is it acts as a synchronizer [4] which allow
the source signal and the signal of the grid on the same phase. It is crucial to have the reference signal
and internal oscillating signal (from VCO) on a same phase because it will ensure a high quality power
from the source to be channelled to the grid. Furthermore, when both of the signals are in the same
phase, it is easier to control the active and reactive power based on demands [5].

Although PLL plays an important part in connecting power converters to the grid network, the classic
PLL has its drawback as it is susceptible to disturbance such as harmonics and frequent unbalanced
phase voltages [6]. Harmonics is a distortion of a sinusoidal waveform by waveform from different
frequencies that is inherent in power supply switching circuits such as rectifiers, power transistors
and solid state switches. Harmonics also can be classified different levels such as 1 st Harmonics, 2nd
Harmonics and the list goes on. To determine what level it is we need to look at the fundamental
frequency. This varies according to different countries, fundamental frequency (f) of United Kingdom
for example is set at 50Hz. How 2nd harmonic frequency came about is by multiplying 2 with
fundamental frequency, 50Hz which gives 100Hz. This means 3rd harmonic frequency is 150Hz and so
on. Figure 3 illustrates how harmonic frequency effects output waveform.

Page 3 of 8
EEE360/371/461 Report 1

Figure 3 - How Harmonics Effect Output Waveform

Realising this situation, people have come up with many genius innovations on PLL to be suited in 3
phase systems such as Synchronous Reference Frame (SRF) PLL with lead compensation aims to
remove or reducing the harmonic content.

Figure 4 - Synchronous Reference Frame PLL with Lead Compensation

Page 4 of 8
EEE360/371/461 Report 1
Clarke and Park is transformation is largely used in most phase locked loop hence it is useful to
understand how it is done mathematically. To explain Clarke and Park transformation, we need to
assume a three phase voltage vector as 𝑈𝑥𝑦𝑧 = [𝑢𝑥 𝑢𝑦 𝑢𝑧 ]𝑇 that can be transformed into a
vector [𝑈𝑑 𝑈𝑞 ]𝑇 in synchronously rotating reference frame by using the Clarke transformation [3],

1 1
𝑣𝛼 2 1 − −
2 2
𝑢𝛼𝛽 = [𝑣 ] = = 𝑢𝑥𝑦𝑧 = 𝑇𝛼𝛽 × 𝑢𝑥𝑦𝑧 (1)
𝛽 3 √3 √3
[0 − 2 2 ]

And followed by Park transformation

𝑈𝑑 𝑐𝑜𝑠𝜃 −𝑠𝑖𝑛𝜃
[𝑈 ] = [ ] 𝑣 = 𝑇𝑑𝑞 𝑢𝛼𝛽 (1.1)
𝑞 𝑠𝑖𝑛𝜃 𝑐𝑜𝑠𝜃 𝛼𝛽
For a voltage vector
𝐸𝑐𝑜𝑠(𝜃𝑔 )
𝑢𝑥 2𝜋
[𝑢𝑦 ] = 𝐸𝑐𝑜𝑠(𝜃𝑔 − 3 )
𝑢𝑧 2𝜋
[ 𝐸𝑐𝑜𝑠(𝜃𝑔 + )
3 ]

There is
𝑈𝑑 𝐸𝑐𝑜𝑠(𝜃 − 𝜃𝑔 )
[𝑈 ] = [ ]
𝑞 𝐸𝑠𝑖𝑛(𝜃 − 𝜃𝑔 )
Therefore, [𝑈𝑑 𝑉𝑞 ]𝑇 is two DC component vector 𝑈𝑑 and 𝑈𝑞 in SRF. 𝑈𝑞 component is to be fed into
proportional integral (PI) controller to obtain 𝑈𝑞 = 0 to lock into a phase of input signal in steady
state. Output of PI controller will be the predicted frequency which will be integrate to acquire
estimation of phase angle 𝜃 as shown in Figure 1.1. Estimation of amplitude E of voltage vector can
be obtained from equation

𝐸 = √(𝑈𝑑 2 + 𝑈𝑞 2
𝐸 = 𝑉𝑑 when the phase is locked. As shown in the above equations, we can say that the amplitude,
frequency and phase are all available from Synchronous Reference Frame Phase Locked Loop.

Page 5 of 8
EEE360/371/461 Report 1
Project Specification:

The specifications are acquired based on the voltage disturbance standard EN 50160 [7]

Table 1

Table 2 – Values of individual harmonic voltage up to 25th orders (IEEE standards)

Page 6 of 8
EEE360/371/461 Report 1
Project Schedule:

Page 7 of 8
EEE360/371/461 Report 1
REFERENCES
[1] S. Chung, “Phase-locked loop for grid-connected three-phase power conversion system,” IEE
Proceedings - Electric Power Application, vol. 147, no. 3, pp. 213-219, 2000.
[2] S. Gao, “Phase-locked loops for grid-tied inverters : comparison and testing,” in IET, Glasgow,
UK, 2016.
[3] T. H. Qing-Chang Zhong, Control of Power Inverters in Renewable Energy and Smart Grid
Integration, Wiley-IEEE Press, 2013.
[4] R. R. K. N. D. B. G. Ramya, “Analysis of synchronization algorithm for grid connected
photovoltaic modular multilevel converter using positive sequence detector and phase locked
loop,” in Trends in Industrial Measurement and Automation (TIMA), 2017, Chennai, India, India,
2017.
[5] X. W. D. P. D. Y. W. L. C. B. Xinbo Ruan, Control Techniques for LCL-Type Grid-Connected
Inverters, Springer, 2017.
[6] D. Siemaszko, “Grid Synchronization of Power Converters to Weak Unbalanced Networks with
Disturbances,” in Electrical Systems for Aircraft, Railway and Ship Propulsion (ESARS), Bologna,
Italy, 16-18 Oct. 2012.
[7] H. M. &. A. Klajn, Voltage Disturbances Standard EN 50160, Wroclaw University of Technology:
Copper Development Association, July 2004.

Risk Register:

Risk Description of Risk Mitigation of Risk Risk Chance

Number evaluation of risk
(L/M/H) occurring
(L/M/H)
1 Loss of data (USB key) Multiple back-ups in M L
multiple locations
2 MATLAB crash Make sure to save regularly M M
3 Lack of Project Diversify the search on L L
Resource different source of
reference
4 Calculation Error Refer to supervisor for any L L
uncertainties

Page 8 of 8