PERFORMANCE COMPARISION OF NEURO CONTROLLED

SEVEN LEVEL SHUNT ACTIVE POWER FILTER FOR

CARRIER BASED PWM TECHNIQUES
*
G. Jayakrishna1,
Professor, Department of EEE, Narayana Engineering College, Nellore.
AndhraPradesh,India-524101
g.jayakrishna25@gmail.com.
ABSTRACT
This paper presents the performance comparison of carrier based pulse width modulation
techniques applied to Asymmetric Cascaded Seven-Level Inverter (ACSLI) based Shunt Active
Power Filter (SAPF) to suppress the harmonic distortion in supply current due to non-linear
loads and to improve the power factor. The ACSLI uses two H-Bridge cells and the control
strategy includes p-q theory for reference compensation current estimation and Neuro controller
(NC) for maintaining DC bus voltage constant. For generating switching signals for ACSLI,
Carrier based pulse width modulation techniques with constant switching frequency and
variable switching frequency are used. The performance of SAPF for different carrier based
modulation techniques is simulated using MATLAB/SIMULINK and the results are presented.
I. INTRODUCTION
Medium voltage drives have found extensive application in various industries and several
industries have increased their power-level needs, urged mostly by economy of scale, causing
the development of new power semiconductors, converter topologies, and control methods.
Currently, medium voltage drives cover a power range of 0.2 MW to 40 MW at voltage level of
2.3 kV to 13.8 kV. These nonlinear loads will introduce harmonics in to the system causing
higher losses, electromagnetic interference, measurement errors, misoperation of some power
system components[1]-[2]. The development of high voltage based multilevel inverter has
attracted the attention of power electronics community for reactive power compensation and
power quality improvement [3]-[4]. Different multilevel inverter topologies are Diode clamped,
Flying capacitor and Cascade H-bridge inverter are discussed in literature[5]-[6]. Cascade
multilevel inverter requires less number of components compared to diode clamped and flying
capacitor multilevel inverters. Asymmetric cascaded multilevel topologies reduce number of
switches [7] in which each DC source drives at different voltage level. Since in active power
filter application there is no need of active power output from the inverter, a separate DC source
for each converter bridge is not required [8].
2. OPERATION OF ASYMMETRIC CASCADED SEVEN LEVEL INVERTER (ACSLI)
BASED SHUNT ACTIVE POWER FILTER
SAPF measures the harmonic content in load current and injects the compensation current at
the point of common coupling to suppress the harmonics in the load current and to improve
power factor[1]. This paper presents a seven level inverter based SAPF which consists of two
H-bridge cells connected in series and driven by separate DC sources of different voltages. The
SAPF is connected in parallel with the load as shown in Figure 1.
The voltage capability of the semiconductor devices and the switching speed of high
voltage devices used in the proposed system will define the number of total cells that must be
connected in series in each phase to compensate the harmonic currents. A combination of 3 kV
and 1.5 kV DC bus voltages are used in this topology to synthesize stepped waveforms with
seven voltage levels via -4.5 kV, -3 kV, -1.5 kV, 0, 1.5 kV, 3 kV, 4.5 kV at the each phase leg
output. The higher voltage levels (± 3kV) are synthesized using GTO inverters while lower
voltage levels (± 1.5kV) are synthesized using IGBT inverters. The number of output phase
voltage levels “m” in this asymmetric cascaded multilevel inverter is given by m=2s+1, where
‘s’ is the number of separate DC sources.

1
 Figure 1 Seven level inverter based APF.

The principle characteristic of the cascaded topology is suitable for active filter
applications in high and medium voltage systems. The proposed control scheme uses p-q theory
for reference compensation current estimation and Neuro controller for dc bus control at LV cell
and carrier based pulse width modulation techniques for gating signal generation. The control
scheme is simulated using MATLAB/SIMULINK.

3. INSTANTANEOUS POWER THEORY BASED REFERENCE CURRENT

GENERATOR:
The proposed instantaneous real-power (p) theory operates in steady-state or transient as
well as for generic voltage and current power systems that allowing to control the active power
filters in real-time. The active filter should supply the oscillating portion of the instantaneous
active current of the load and hence makes source current sinusoidal[9]-[10].

The p-q theory performs a Clarke transformation of a stationary system of coordinates a-

b- c to an orthogonal reference system of co-ordinates α-β. In a-b-c coordinates axes are fixed
on the same plane, apart from each other by 120o.. The instantaneous space vectors voltage and
current Va ,ia are set on the a-axis, Vb , ib are on the b axis, and Vc , ic are on the c-axis. These
space vectors are easily transformed into α-β coordinates. The instantaneous source voltages vsa,
vsb, vsc are transformed into the α-β coordinate voltages vα, vβ by Clarke transformation as
follows:
𝑉𝛼 1 −1/2 −1/2 𝑉𝑠𝑎
[𝑉 ] =2/3[ ] [𝑉𝑠𝑏 ] (1)
𝛽 0 √3/2 −√3/2 𝑉
𝑠𝑐
Similarly, the instantaneous source current isa,isb ,isc also transformed into the α-β coordinate
currents iα , iβ by Clarke transformation that is given as:
𝐼𝛼 1 −1/2 −1/2 𝐼𝑠𝑎
[𝐼 ] =2/3[ ] [𝐼𝑠𝑏 ] (2)
𝛽 0 √3/2 −√3/2 𝐼
𝑠𝑐
Where α and β axes are the orthogonal coordinates. Vα , iα are on the α-axis, and Vβ , iβ are on
the β-axis.
Real-Power (p) calculation:
The instantaneous real-power calculated from the α-axis and β- axis of the current and voltage
are given by the conventional definition as:
𝑃𝑎𝑐 =𝑉𝛼 𝐼𝛼 +𝑉𝛽 𝐼𝛽 (3)
This instantaneous real-power Pac is passed to first order Butterworth design based 50 Hz low
2
 pass filter (LPF) for eliminating the higher order components; it allows the fundamental
component only. These LPF indicates ac components of the real-power losses and it is denoted
as Pac. The DC power loss is calculated from the comparison of the dc-bus capacitor voltage of
the cascaded inverter and desired reference voltage. The proportional and integral gains (PI-
Controller) are determining the dynamic response and settling time of the dc-bus capacitor
voltage. The DC component power losses can be written as
K
PDC(loss) =[VDC,ref − VDC ] [K p + sI ] (4)
The instantaneous real-power ( p) is calculated from the AC component of the real-power loss
Pac and the DC power loss PDC ( Loss ) ) ; it can be defined as follows:
𝑃 = ̅̅̅̅
𝑃𝑎𝑐 + 𝑃𝐷𝐶(𝐿𝑜𝑠𝑠) (5)
The instantaneous current on the α-β coordinates of icα and icβ are divided into two kinds of
instantaneous current components; first is real-power losses and second is reactive power losses,
but this proposed controller Computes only the real-power. So the α-β co-ordinate currents Icα,
Icβ are calculated from the Vα, Vβ voltages with instantaneous real-power P only and the reactive
power q is assumed to be zero. This approach reduces the calculations and shows better
performance than the conventional methods. The α-β coordinate currents can be calculated as
𝐼𝑐𝛼 1 𝑉𝛼 𝑉𝛽 𝑃
[𝐼 ] =𝑉 2 +𝑉 2 {[ ] ( )} (6)
𝑐𝛽 𝛼 𝛽 𝑉𝛽 −𝑉𝛼 0
From this equation, we can calculate the orthogonal coordinate’s active-power current. The α -
axis of the instantaneous active current is written as:
𝑉 𝑃
𝑖𝛼𝑃 = 𝑉 2𝛼+𝑉 2 (7)
𝛼 𝛽
Similarly, the β -axis of the instantaneous active current is written as:
𝑉 𝑃
𝛽
𝑖𝛽𝑃 = 𝑉 2 +𝑉 2 (8)
𝛼 𝛽
Let the instantaneous powers p(t) in the α -axis and the β - axis is represented as pα and pβ
respectively. They are given by the definition of real-power as follows:
𝑃(𝑡) = 𝑉𝛼𝑝 (𝑡)𝑖𝛼𝑝 + 𝑉𝛽𝑝 (𝑡)𝑖𝛽𝑝 (𝑡) (9)
From this equation (9), substitute the orthogonal coordinates α -axis active power (7) and β -
axis active power (8); we can calculate the real-power p(t ) as follows:
𝑉 𝑝 𝑉 𝑝
𝑝(𝑡) = 𝑉𝛼 (t) [𝑉 2𝛼+𝑉 2 ] + 𝑉𝛽 (𝑡) [𝑉 2𝛽+𝑉 2 ] (10)
𝛼 𝛽 𝛼 𝛽
The AC and DC component of the instantaneous power p(t ) is related to the harmonics
currents. The instantaneous real-power generates the reference currents required to compensate
the distorted line current harmonics and reactive power.

4. SIMULATION OF MV TEST SYSTEM WITH PROPOSED 7-LEVEL SHAPF

COMPENSATION
The MV test system consists of a three phase AC source of voltage 4500V(peak), 50 Hz
frequency connected to a nonlinear diode rectifier load through a source and line combined
reactance of 15mH/phase. The R-L load on the DC side of diode rectifier has 20 Ω and 0.1 mH
respectively. The complete Simulink model of the MV test system with proposed ACSLISAF
compensation is modelled using MATLAB/Simulink environment and is depicted in Fig. 2.

3
 Va,Ia
Discrete, [B]
Ts = 5e-005 s.
Goto1
Out1 Ia Conn1
Isabc pow ergui
Out2 Ib LOAD CURRENTS

Out3 Ic
Vsabc
Out4 Va Conn2

Out5 Vb

Out6
i
Vc +
-
Conn1 Conn3
A +
i
Conn2 -
B
i NONLINEAR DIODE RECTIFIER LOAD
Conn3 +
C -
3-PHASE AC SOURCE

Out1 ta1
Out2 ta2
Out3 ta3

i
-
VA
If aref
TO PHASE-A
Out4 ta4 [A]

+
Out5 ta5
ILabc2 Out6 ta6 Goto
Out7 ta7
Out8 ta8
Out9 tb1
VB
Out10 tb2
[B] Out11 tb3
If bref Out12 tb4
TO PHASE-B
From Out13 tb5
Out14 tb6
Out15 tb7
VC
[A] Out16 tb8
Out17 tc1 A
From1 If abc Out18 tc2
Out19 tc3
If cref Out20 tc4
TO PHASE-C C VSI OUTPUT
Out21 tc5
-
Out22 tc6
Out23 tc7
Out24 tc8
B
time
REFERENCE COMPENSATION CURRENT ESITIMATOR
3-PHASE SEVEN LEVEL INVERTER
CSFSHPWM Clock
To Workspace

Fig. 2 Simulation model of MV test system with proposed 7-level SHAPF compensation.
The proposed ACSLISAF compensation consists of an asymmetric cascaded seven level
inverter (ACSLI) and its overall control system including p-q theory, Carrier switching
frequency sub-harmonic PWM technique and NeuroController.
4.1 Three Phase ACSLI model
Each phase of ACSLI consists of two H-bridge cells (LV cell and HV cell) in series and
each H-bridge cell is constructed using 4 thyristor switches with anti-parallel diodes. The two
H-bridges have separate energy storage devices on DC side. The DC voltages selected for LV
and HV cells are 1.5 kV and 3 kV. Since VHV is two times VLV, it can produce seven levels in
its output wave form. On DC side of 3 kV cell a DC source is used as storage device and a
capacitor of 4000 μF is used on the DC side of 1.5 kV cell. The DC-bus capacitor value is taken
large enough to minimize the variation of its voltage based on the general principle that
capacitor time constant to be ten times than that of fundamental period. The ACSLI is
connected at the point of common coupling through an interfacing inductor (Lf) and capacitor
(Cf) whose values are Lf = 2 mH, Cf=100 μF to filter the noise.
4.2 Control Strategy of ACSLI
The control strategy of ACSLI includes p-q theory for reference compensation current
estimation and carrier based PWM techniques for gating signal generation and NeuroController
for voltage regulation at LV cell capacitor.
4.2.1 p-q theory for estimating reference compensating currents
The simulation details of subsystem blocks for calculating various parameters are
described in the following sections.
4.2.1.1 ClarkTransformation

4
 Fig.4 Block Diagram for Clark Transformation and p calculation.

Fig 5 Clark transformation block diagram for both Vα, Vβ, Iα and Iβ
4.2.1.2: Calculation of :
According to p-q theory real and imaginary power can be separated into two parts:
Real power:
Imaginary power:
Where 𝑝̃ and 𝑞̃ are average power due to component 𝑖𝑎𝑝 ̅̅̅̅ and 𝑖𝑎𝑞
̅̅̅̅ respectively. 𝑝 ̃ and 𝑞̃ are
oscillating power due to components 𝑖𝑎𝑝 ̃ and 𝑖𝑎𝑞 ̃ respectively. And 𝑖 − (𝑖𝑎𝑝 ̃ + 𝑖𝑎𝑞 ̃ ) will
produces a purely sinusoidal waveform.But in order to achieve unity power factor APF
must compensate for 𝑞̃ from component 𝑖𝑎𝑞 ̃ .Thus 𝑖 − (𝑖𝑎𝑝 ̃ + 𝑖𝑎𝑞 ̃ + 𝑖𝑎𝑞
̅̅̅̅ ) will produce
purely sinusoidal waveform with unity power factor. Thus, inverse transformation 𝑖𝑎𝑝 ̅̅̅̅
will produce reference current𝑖𝑠∗ for each phase.𝑖̅̅̅̅
𝑎𝑝 can be deduced from 𝑝̅ which is filtered out
using low pass filter from p.

Fig.6 Block Diagram for calculation of p

5
 Fig.7 𝒑̅ from p using low pass filter
4.2.1.3: Reference Current Calculation:
Reference currents are calculated from inverse Clark transformation.

Fig.8: Block Diagram of Isα, Isβ

Fig.9: Block Diagram for calculating Ia*, Ib* and Ic*

4.2.2 Neuro Controller

In this paper, Neuro Controller is used to regulate the DC capacitor voltage of LV cell. The
input-output data necessary for the off-line training of the neural network have been found in
the proposed work using the DC capacitor voltage error of the HCSLI. The data set value is
made sufficiently rich to ensure stable mode operation, since no additional learning will take
place after training.
A back-propagation algorithm is used for training of the created network. The LEARNGDM
function which has a gradient descent with momentum weight / bias learning is used in this
work. Learning occurs according to the learning parameters: learning rate=0.01 and momentum
constant t = 0.9. MSE is the performance criteria used in this work that evaluates the network
according to the mean of the square of the error between the target and computed output. The
minimum MSE that can be achieved in this work is 1e-6. For a back-propagation training
algorithm, the derivative of the activation function is essential. Therefore, the activation
function selected must be differentiable. The sigmoid function satisfies this requirement and it is
the commonly used soft-limiting activation function. It is also quite common to use linear
output nodes to make learning easier and using a linear activation function in the output layer
does not ‘squash’ (compress) the range of output. Hence, a bipolar sigmoid activation function
and a linear activation function are used for the hidden and output layers respectively. Trials
6
have been carried out to obtain maximum accuracy with a minimum number of neurons per
layer[11].
The feed forward neural network developed consists of one neuron in the input layer, four
neurons in the hidden layer and one neuron in the output layer. The optimum number of neurons
for the hidden layer is selected as four (TABLE I) since the number of epochs for training the
neural network is reduced considerably. The tansig function is found to be better than the logsig
activation function for the hidden layer since the logsig function takes (TABLE II)
approximately 200 more epochs than the tansig function. The input to the NC is DC capacitor
voltage error (e) of SAPF. The output of the NC is the corrected reference signals.

TABLE I Choice of hidden neurons

Number of hidden Number of epochs for training the
neurons network
1 Performance goal not met
2 Performance goal not met
3 ≈ 400
4 ≈ 100
5 ≈ 320
6 ≈ 360
7 ≈ 400
8 ≈ 420

TABLE II Choice of bipolar sigmoid transfer function as activation function for hidden
layer
Number of Number of epochs with Number of epochs with logsig
hidden neurons tansig activation function activation function
1 Performance goal not met Performance goal not met
2 Performance goal not met Performance goal not met
3 ≈ 400 ≈ 410
4 ≈ 100 ≈ 200
5 ≈ 320 ≈ 420
6 ≈ 360 ≈ 460
7 ≈ 400 ≈ 480
8 ≈ 420 ≈ 485

4.2.3 Carrier Based PWM Techniques

Fig.10 shows Simulink model of CSFSHPWM technique with (m-1) carriers with the same
frequency fc, same amplitude Ac and are level disposed. The reference waveform has peak to
peak amplitude Am, frequency fm, and it is zero centered at the middle of the carrier set. The
reference is continuously compared with each of the carrier signals. If the reference is greater
than “s” carrier signal, then the active device corresponding to that carrier is switched off[12].
In multilevel inverters, the amplitude modulation index “Ma” and the frequency ratio “Mf” are
defined as
Ma = Am / (m-1) Ac (7)
Mf = fc / fm (8)
Different modulation techniques used for producing gating signals for multilevel inverters are
presented in the literature such as Selective harmonic elimination method, Space vector PWM
method and Carrier based PWM methods out of which most popularly used carrier based PWM
techniques are used in this paper for generating switching signal for seven level VSI due to their
advantages such as less computation, fast response and applicable for multilevel inverters with
large number of levels. The carrier based PWM techniques that are used in this paper are i)
Phase disposition PWM(PD-PWM) ii) phase opposition PWM(PO-PWM) iii) Phase opposition
disposition PWM(POD-PWM) iv) Phase opposition disposition optimal PWM(POD-PWM-O)
7
v) Alternate phase opposition disposition PWM(APOD-PWM vi) Alternate phase opposition
disposition optimal PWM(APOD-O-PWM) vii) Variable switching frequency carrier
subharmonic PWM(VSFC-SHPWM) viii) Variable switching frequency carrier optimal
subharmonic PWM(VSFC-O-SHPWM).
K
s
To Workspace2
To Workspace 1
OR

7
NOT Ta 7
8
Ta 8
OR

Ta 6 6

NOT

Ta 5 5

<=
AND

3 Ta 3

NOT

time 2
4 Ta 4 Clock
To Workspace
NOT

1 Ta 1
1 AND

2 Ta 2

Fig. 10 Simulink model of CSFSHPWM for phase –a.

In Fig. 10, six triangular signals each of frequency 2 kHz and magnitude 0.33 are taken as
carrier signals and a sinusoidal voltage wave form with peak amplitude 0.8 obtained from
compensating reference current estimator is used as modulating signal. Carrier signals for
multilevel applications are in the form of level-shifted to each other or phase-shifted. In level-
shifted PWM, the carrier signals have the same phase and peak-to-peak amplitude and they are
in vertical positions to each other. In phase-shifted PWM the phase of each carrier shifts in a
proper angle to reduce the harmonic content of the output voltage. Triangular waveforms are
used as carrier signals. The carrier signals and modulating signal for 7-level inverter for
different modulation methods are presented.
4.2.3.1 Phase disposition PWM (PD-PWM)
In PD-PWM modulation, all the carrier signals are in phase and are level shifted as shown in
Fig. 11 for a 7-level inverter with ma=0.8 and mf=40. In this technique, the odd sidebands
around the even carrier multiples, and the even sidebands around the odd carrier harmonics can
be easily seen in the output phase voltage spectrum. Also, only the multiples of three away from
the carrier multiples cancel in the line voltage.

8
 1

0.8

0.6

Magnitude(pu) 0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(sec)

Fig:11 PD-PWM technique(subharmonic)Reference signals and carrier signals.

4.2.3.2 Phase disposition PWM-Optimal (PD-PWM-O)
In PD-PWM-O method third harmonic is injected in to sinusoidal reference signal and the
resulting waveform will be used as modulating signal where as the carrier signals will be same
as those in PD-PWM method as shown in Fig. 12.
1

0.8

0.6

0.4
Magnitude(pu)

0.2

-0.2

-0.4

-0.6

-0.8

-1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(sec)

Fig:12 PD-PWM technique(optimal)Reference signals and carrier signals

4.2.3.3 Phase opposition disposition PWM (POD-PWM):
In POD-PWM technique the carrier signals above zero are in phase and those below zero are
180◦ out of phase with carrier signals above zero. Fig.13 shows the POD-PWM technique for a
7-level inverter with ma=0.8 and mf=40. In POD, the output phase voltage has quarter-wave
symmetry, if mf is even. If mf is odd, then the output waveform has odd symmetry. In this
modulation, dominant harmonics are on the sideband of the first carrier (mf ±1) and the phase
voltage harmonic at the carrier frequency is not considerable. Hence, similar to APOD-PWM,
POD modulation contains significant harmonics in the line voltage spectrum, especially in the
first carrier band. Comparing to APOD, this modulation has more harmonic distribution along
the harmonic orders. This is because, the APOD technique places more harmonic energy into
the multiples of three away from the carrier multiples than POD. These triple sideband
harmonics cancel on a three-phase system, hence performance of the APOD is improved
compared to POD.
9
 1

0.8

0.6

0.4
Magnitude(pu)
0.2

-0.2

-0.4

-0.6

-0.8

-1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(sec)

Fig.13 Reference and carrier signals for POD-PWM technique.

4.2.3.4 Phase opposition disposition PWM –Optimal (POD-PWM-O)
In POD-PWM-O method carrier signals are same as those in POD-PWM but the modulating
signal is obtained by injecting third harmonic in to sinusoidal wave form and will be as shown
in Fig. 14.
1

0.8

0.6

0.4
magnitude(pu)

0.2

-0.2

-0.4

-0.6

-0.8

-1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(sec)

Fig.14 POD-PWM technique (optimal) reference and carrier signals.

4.2.3.5 Alternate phase opposition disposition PWM (APOD-PWM)
In this modulation, carrier signals are out of phase with their neighbours by 180◦ and
sinusoidal modulating signal is used. Fig. 15 shows carrier and reference signals of APOD-
PWM technique for a 7-level inverter with ma=0.8 and mf=40. APOD modulation does not
produce a first carrier harmonic. Instead the dominant harmonics are channelled into the
sidebands around the first carrier harmonic. Since only the triple sidebands away from the
carrier frequency cancel in a three phase system, APOD modulation contains some considerable
harmonic energy in the line voltage spectrum. In addition, output voltage has quarter wave
symmetry, if mf is even. If mf is odd then the output waveform has odd symmetry.

10
 1

0.8

0.6

MAgnitude(pu) 0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(sec)

Fig. 15 APOD-PWM technique (sub harmonic) :Reference and carrier signals

waveform.
4.2.3.6 Alternate phase opposition disposition PWM-Optimal (APOD-PWM-O)
In APOD-PWM-O method carrier signals are same as those in APOD-PWM method but the
modulating signal is obtained by injecting third harmonic in to sinusoidal wave form and will be
as shown in Fig. 16.

0.8

0.6

0.4
Magnitude(pu)

0.2

-0.2

-0.4

-0.6

-0.8

-1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(sec)

Fig. 16 APOD-PWM technique (optimal) :Reference and carrier signals waveform.

4.2.3.7 Variable Switching Frequency PWM (VSF PWM)
In this technique for a m level inverter, (m-1) carrier signals with different switching
frequencies but with same amplitude are used with sinusoidal reference signals as shown in Fig.
17. The carriers are in phase across for all the bands. In this technique, significant harmonic
energy is concentrated at the carrier frequency. But since it is a co-phasal component, it doesn’t
appear in line to line voltage.

11
 0.8

0.6

0.4

0.2
Magnitude(pu)

-0.2

-0.4

-0.6

-0.8
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(sec)

Fig. 17 Variable switching frequency (sub harmonic)PWM reference signals and

carrier waves.
4.2.3.8 Variable Switching Frequency PWM –Optimal (VSF PWM-O)
It is similar to VSF PWM except that third harmonic is injected in to the reference signal
as shown in Fig. 18. The resulting flat topped modulating signal allows over modulation while
maintaining excellent AC term and DC term spectra. This is an alternative to improve the output
voltage without entering the over modulation range. So any carriers employed for this reference
will enhance the output voltage by 15% without increasing the harmonics.

0.8

0.6

0.4

0.2
Magnitude(pu)

-0.2

-0.4

-0.6

-0.8
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time (sec)

Fig. 18. Variable switching frequency (optimal) reference signals and carrier waves.
12
5. RESULTS AND DISCUSSION
The Specifications of the elements used in Simulink model are given in Table III.
Table III: Specifications of elements
System parameters
Source voltage(peak) Vsa,Vsb,Vsc 4500V
Source frequency f 50Hz
Source impedance L 15mH
Diode rectifier load 0.1mH
inductance
Diode rectifier load 20Ω
resistance
Seven level SAF parameters
DC HV bus Voltage Vdchv 3 kV
DC LV bus Voltage Vdclv 1.5 kV
DC LV bus capacitor 4000µF
AC side inductance 2mH
AC side capacitance 100µF

5.1 SIMULATION RESULTS OF THE TEST SYSTEM WITHOUT ANY

COMPENSATION
The simulation results of the test system consisting 3-phase AC source connected to R-L load
through a transmission line and diode rectifier load are presented in this section. The load
current is very much distorted as shown in Fig. 19 due to diode rectifier load. Due to this source
current is also distorted as shown in Fig. 20. The THD in source current of phase-a is 12.39 %
as shown in Fig. 21.

250

200

150

100
load current(A)

50

-50

-100

-150

-200

-250
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time(s)

Figure 19 Load current without any compensation

13
 250

200

150

100
source current(A)

50

-50

-100

-150

-200

-250
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time(s)

Figure 20. Source current without any compensation

Figure 21. Harmonic spectrum of line current without filter for phase-a.

5.2 SIMULATION RESULTS WITH ACSLI SAF COMPENSATION

The simulation results of the test system with SAF compensation consisting NeuroController, p-
q theory and different carrier based PWM techniques are presented in this section. The three
phase source current, SAF compensated current, inverter output voltage and harmonic spectrum
of Phase-a line current are shown in Fig. 22, Fig. 23 and Fig. 24 respectively.

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 600

400

200

Current(Amp)
0

-200

-400

-600

-800
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05
time(sec)

Figure 22. Source current with SAF compenasation.

600

400

200
Filter current(A)

-200

-400

-600
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time(s)

Figure 23. SAF compensating current.

5000

4000

3000

2000
Voltage(Volts)

1000

-1000

-2000

-3000

-4000

-5000
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time(sec)

Figure 24. Seven level Inverter output voltage.

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 Figure 25. Harmonic spectrum of source current (phase-a) with SAF.
The THD in source current for different carrier based PWM techniques are obtained and are
presented in Table IV. From Table IV it is observed that VSF-PWM is more superior in
compensating harmonics in load current compared to all other carrier based PWM techniques
mentioned.

Table. IV Source current THD comparison for different carrier based PWM techniques.

% THDi
Carrier based PWM Ia Ib Ic
technique
Without SAF 12.39 12.39 12.39
With SAF(PD-PWM) 3.33 3.55 3.49
With SAF(PD-PWM-O) 3.50 3.69 3.54
With SAF(POD-PWM) 3.59 3.31 3.49
With SAF(POD-PWM-O) 3.30 3.51 3.46
With SAF(APOD-PWM) 3.28 3.55 3.44
With SAF(APOD-PWM-O) 3.36 3.49 3.56
With SAF(VSF-PWM) 3.21 3.29 3.35
With SAF(VSF-PWM-O) 3.52 3.77 3.68

6. CONCLUSIONS
The asymmetric cascaded seven level inverter based shunt active power filter is suitable
for power line conditioning of medium voltage power systems. The p-q theory based
reference current estimating technique worked effectively and the sinusoidal PWM method
effectively produced the gating signals to the inverter switches to produce seven level output
voltage. The seven level APF system including the proposed control method reveal that the
cascaded active power filter effectively compensates the harmonics. The measured total
harmonic distortion of the source currents is 3.51 % that is in compliance with IEEE
519-1992 and IEC 61000-3 standards for harmonics. Also the performance of SAF with VSF-
PWM is superior when compared with other carrier based sinusoidal PWM techniques.

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