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Encounter® Conformal®

Low Power User Guide


Product Version 7.1
August 2007
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Encounter Conformal Low Power User Guide

Contents
1
Introduction to Conformal Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Low Power Equivalency Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Low Power Extended Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logical and Physical Netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Structural Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Rule-Based Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Common Power Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Low Power Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Dynamic Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Level Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Multi-Voltage Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Signal Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
State Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Voltage Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2
Running Low Power Equivalency Checks . . . . . . . . . . . . . . . . . . . . . 15
Low Power Equivalency Checking Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Starting the Low Power (EC) Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Setting Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Running Low Power Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
State Retention Cell Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Isolation Cell and Level-Shifter Cell Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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LowPower Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LowPower Diagnosis Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Sample Dofile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CPF Low Power Cell Insertion Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reading the CPF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Performing Low Power Cell Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power Domain Schematic Color Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3
Running Low Power Extended Checks . . . . . . . . . . . . . . . . . . . . . . . . 35
Low Power Functional Checking Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Starting Conformal Low Power (Extended Checks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Specifying Low Power Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Validating Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power Control Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4
Running Logical Netlist Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Setting Options and Reading Logical Netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Design Verification Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Defining Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Defining Low Power Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Defining Isolation Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Isolation Cell Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Level Shifter Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Isolation and Level Shifter Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5
Running Physical Netlist Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Setting Options and Reading Physical Netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Reading in the LEF, Library and Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Handling Special Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Design Verification Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Defining Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

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Black Boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Defining Power Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Defining Power Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Defining Retention Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Defining Isolation Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Level Shifter Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Combination of Level Shifter and Isolation Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Defining Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Switch Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Analyzing Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6
Low Power Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Low Power Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
CPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Logical Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Functional Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Running Low Power Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Viewing Source Code and Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Functional Verification Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Isolation Functional Failure - True Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Isolation Functional Failure - X Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Power Domain Crossing Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Debugging Combinational Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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1
Introduction to Conformal Low Power

■ Overview on page 6
■ Low Power Equivalency Checking on page 6
■ Low Power Extended Checking on page 7
❑ Logical and Physical Netlists on page 7
❑ Structural Checking on page 7
❑ Rule-Based Checking on page 8
❑ Functional checking on page 8
■ Common Power Format on page 8
■ Low Power Concepts on page 9
❑ Clock Gating on page 9
❑ Dynamic Power on page 9
❑ Level Shifting on page 10
❑ Multi-Voltage Supplies on page 10
❑ Power Domain on page 11
❑ Power Gating on page 11
❑ Power Switching on page 12
❑ Signal Gating on page 12
❑ State Retention on page 12
❑ Voltage Domain on page 13

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Introduction to Conformal Low Power

Overview
Designers increasingly expect longer battery life and higher performance. Due to increased
leakage, devices created using 90-nanometer and smaller process nodes consume as much
power when they are not in use as when they are being used. Designers can optimize for
leakage and dynamic power, which reduces energy use and lowers cooling and packaging
costs. Additional advanced low power methods offer further power savings, but significantly
complicate the verification process.

The Encounter® Conformal® Low Power software enables you to verify correct
implementation of these low power design techniques and validate your silicon using formal
techniques (versus simulation) early in the design process. It also decreases the risk of
missed bugs which are often missed, before a product goes out the door. Conformal Low
Power is the only solution in the industry providing full-chip low power functional verification.

Conformal Low Power accepts RTL/gate-level netlists with or without explicit power or ground
nets, and accepts user-defined power pins, power domains, power switches, level-shifter
cells, isolation cells, and state retention cells.

Low Power Equivalency Checking


Conformal Low Power Equivalency Checking ensures the implementation tools do not
introducing low power optimization problems by verifying the following:
■ Retention implementation—checks that the value of state is retained when the power is
switched off or changed to a low value.
■ Isolation Boundary—checks the logic inserted between two power domains to prevent
floating signals from a powered-off domain to a powered-on domain.
■ Level-Shifter Boundary—checks for any change the voltage level when going from one
power domain to another.

Conformal Low Power Equivalency Checking also supports low power cells insertion at the
Golden side by parsing the Common Power Format (CPF) file. This ensures that the design
and implementation tools maintain their logic integrity during optimization.

For more information, see Chapter 2, “Running Low Power Equivalency Checks”.

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Introduction to Conformal Low Power

Low Power Extended Checking


You can use the Conformal Low Power Extended Checking software for logical and physical
netlists to perform structural checks, user-defined rule based checks, and functional checks.
All three types of checking are necessary to completely check the design.

Logical and Physical Netlists


Conformal Low Power logical netlist checking works on netlists without power and ground
connections. It checks level shifter locations and isolation cell types and locations. Conformal
Low Power physical netlist checking works on netlists with power and ground connections. It
completes checks for level shifter, isolation, and state retention cells.

For more information, see Chapter 4, “Running Logical Netlist Checks” and Chapter 5,
“Running Physical Netlist Checks”.

Structural Checking
A structural check is anything we can do that only involves looking at the connectivity and
traversing through simple inverter and buffer gates. The structural check does not analyze
any logic to do the checks.
■ ISO7 checks flag missing isolation between switchable to non-switchable domains
■ Primitives with no power domain or multiple power domain (data or setup problem)
■ Nets with no drivers
■ Obvious redundant isolation (between two non-switchable domains)
■ Power ports not connected to a power domain
■ Power and ground domain shorts
■ Power and power domain shorts
■ Level shifter power ports connection errors (to wrong voltage)
■ Isolation cell power port connection (not to correct domain based on receiver)
■ Power switch cell port checking

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Rule-Based Checking
You can specify how you expect isolation or retention to be implemented by defining valid
rules for checking isolation and retention cells.

Functional checking
The structural checks are automatic and done when analyzing the power domain. Analyze
power domain also performs the user-defined rule based checks if there are any enabled.
Once the structural checks have passed and all errors have been addressed, the next step is
functional validation when the software completes the checking.
■ Isolation is inserted properly as needed in all cases.
■ Isolation control is asserted during power down of the module being isolated
■ Retention cells are controlled properly with respect to clock, retention control signal, and
the control that powers down the domain where the retention cell exists.

Common Power Format


The Common Power Format (CPF) is intended to address the current limitation in the design
automation tool flow by enabling the capture of the designer’s intent for advanced power
management techniques. CPF provides support for all design and technology-related power
constraints to be captured in a single file format for use throughout the RTL to GDSII design
flow including verification, validation, synthesis, test, physical implementation, and signoff
analysis.

The automation enabled through CPF infrastructure support will be the answer to the growing
power management design challenges faced by the industry. The introduction of CPF and its
support will bring productivity gains and improved quality of silicon to designers without
requiring any change to current legacy RTL.

For more information, see the following documents for Common Power Format (CPF):
■ Common Power Format Language Reference
You can open this from the Main Conformal window by choosing Help – CPF
Reference Manual.
■ Common Power Format User Guide
You can open this from the Main Conformal window by choosing Help – CPF User
Guide.

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Low Power Concepts

Clock Gating
Clock Gating is when logic that receives signals from clock gated latches and registers do not
switch. No dynamic power is consumed. Clock gating minimizes switching. In many designs,
data is loaded into registers infrequently, but the clock signal continues to switch at every
clock cycle often driving a large capacitive load. You can save a significant amount of power
by identifying when the registers are inactive and by disabling the clock during these periods.

Not Clock Clock


Gated Gated Gated

Dynamic Power
Dynamic power is the power dissipated by an instantaneous short-circuit connection between
the voltage supply and the ground when the gate transitions, and the switching power
dissipated when charging or discharging internal and net capacitances.

Isolation
Isolation is a power management technique that prevents undriven outputs of switched OFF
blocks from causing electrical problems in active blocks. Active isolation provides driven value
to active logic, setting a logic cell input to a level that makes all other inputs a don’t care, i.e.
the voltage level of the other data inputs do not have any impact on the internal nets or the
outputs. Serious problems occur if in-active logic is not isolated.

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Level Shifting
Level shifting is a technique to transport a signal from one voltage value to a higher or lower
voltage value. A level-shifter is a cell that is used as a boundary for signals that cross voltage
domains. A low to high crossing always requires a level shifter to prevent an abnormally high
power consumption. It is common to use level shifter which is a buffer powered by the higher
voltage for a high to low voltage domain crossing. Serious problems occur if signals go from
a low to high voltage domain without proper level shifting.

Multi-Voltage Supplies
Level shifters are required when a lower voltage signal drives a gate supplied by a higher
voltage. These cells are placed between a source and receiver powered by different voltages
to protect the receiver from too high or too low voltage. A level shifter requires both voltages
internally to function.

Vlo Vlo Vhi Vhi

Low High
Level-
Voltage Voltage
Shifter
Domain Domain

When a higher voltage signal drives a gate supplied by a lower voltage, a level shifter might
not be used. When it is, it will use the lower voltage for the output stage and not use either
lower or higher voltage for the input stage.

Vhi Vhi Vlo Vlo

High Lo
Level-
Voltage Voltage
Shifter
Domain Domain

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Power Domain
A power domain is all circuits whose power source has the same voltage (same supply net).
All circuits which share the same power source, and if switchable, share the same power
enabling and disabling control. In the following illustration, all blocks are in separate power
domains:

Power Gating
Power gating is a technique to save leakage power, which switches a power domain’s
connection to a power source OFF, as shown in the following illustration:

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Power Switching
A Power Switch is a PMOS device between a power pin and the power to a module. When
this transistor is turned off, the power domain of the supplied circuit is disabled. The power
output net of a power switch is known as a switched power domain. The module power is
turned OFF by turning OFF the PMOS device.

Signal Gating
Signal is a technique to reduce dynamic power consumption by stopping the switching of
signal value when they are not needed. Signal Gating is a common technique for RAM
address and data pins. This makes the inputs to the logic receiving the gated signal a
constant and eliminates dynamic power consumption.

Signal Clock Clock


Gated Gated Gated

State Retention
State retention is a power management technique that saves states before a block is powered
down. This is the process of saving an important state of a memory element such as a latch
or flip flop before the main power or ground of the module is switched off. The circuit which
saves the state will require non-interruptible power and ground to ensure state preservation.

In the following illustration, Sleep = Ret is asserted during low clock then VDD is switched
OFF. After the Wake - VDD is switched ON, Ret is de-asserted during low clock:

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Voltage Domain
A voltage domain is all circuits whose power source has the same voltage (same supply
voltage value). In the following illustration, Blocks 1, 3, and 4 are in a 1.2v voltage domain,
while Block 2 is in a 1.0v voltage domain:

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2
Running Low Power Equivalency Checks

■ Low Power Equivalency Checking Flow on page 16


■ Starting the Low Power (EC) Software on page 17
■ Setting Low Power Options on page 17
■ Running Low Power Checks on page 17
❑ State Retention Cell Checking on page 18
❑ Isolation Cell and Level-Shifter Cell Checking on page 21
■ LowPower Manager on page 23
■ LowPower Diagnosis Manager on page 28
■ Sample Dofile on page 30
■ CPF Low Power Cell Insertion Flow on page 31
❑ Reading the CPF File on page 32
❑ Performing Low Power Cell Insertion on page 33
❑ Power Domain Schematic Color Coding on page 33

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Running Low Power Equivalency Checks

Low Power Equivalency Checking Flow


This section describes the tasks involved in running low power, as illustrated in Figure 2-1.
This is a standard flow for equivalency checking, which includes the addition of low power
checks. The white boxes indicate the tool actions, and the gray boxes indicate the user
actions. You can also see the Sample Dofile on page 30.

Figure 2-1 Low Power Equivalency Checking Flow

Read design and library

Specify design constraints


and modeling options

Set Low Power Options See Setting Low Power Options on page 17

Mapping

Low Power Check See Running Low Power Checks on page 17

Low Power Diagnosis See LowPower Diagnosis Manager on page 28

Compare This also performs a low power equivalence check


for isolation cells and level-shifter cells.

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Starting the Low Power (EC) Software


To start the software in non-graphical mode, run the following command:
lec –NOGui –lp

To start the software in graphical mode, run the following command:


lec [-Gui] –lp

Setting Low Power Options


You can enable low power check options with the SET LOWPOWER OPTION command. You
can choose to automatically enable one or all of the following low power checks:
Note: By default, SET LOWPOWER OPTION does not automatically enable low power checks.
■ State retention cells—used to retain the value of state when the power is switched off or
changed to a low value.
■ Isolation cells—used to isolate signals coming from an inactive power domain, and going
to an active power domain. Isolation cell (or logic) refers to special logic inserted between
two power domains to prevent floating signals from a powered-off domain to a powered-
on domain.
■ Level-shifter cells—used to change the voltage level when going from one power domain
to another.

For example, you can use the following command to enable low power checks for state
retention cells and isolation cells:
set lowpower option -retention -isolation

Running Low Power Checks


You can run low power checks for state retention cells, isolation cells, and level-shifter cells.
You can run each of these checks separately or combined by running the CHECK LOWPOWER
CELLS command. The following sections describe these checking types in more detail:
■ State Retention Cell Checking on page 18
■ Isolation Cell and Level-Shifter Cell Checking on page 21

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State Retention Cell Checking


For state retention cells, low power checking does the technology mapping check to ensure
that the sequential elements (DFFs or DLATs) are technology mapped in accordance with the
retention mapping rules during synthesis. These retention mapping rules include all the user
rules added with the ADD RETENTION MAPPING command and the default rule added by
the system.

You can define the state retention mapping rules with the ADD RETENTION_MAPPING
command.

Default Rules

The following three default rules are added by the system:


Note: For any sequential pairs, only one of the default rules take effect.
■ Default: Checks that the tag name used in the Golden design is mapped to a non-state
retention cell in the Revised design. A non-state retention cell is a cell that does not have
a power_gating_cell attribute. This rule is normally applied during RTL to gate-level
checks.
■ Default1: Checks that the power_gating_cell attribute in the Golden design is
exactly the same as the power_gating_cell in the Revised design. This check
ensures that non-state retention cells (regular DFFs or DLATs) are mapped to non-state
retention cells, or state retention cells are mapped to state retention cells. This rule is
normally applied during gate-level to gate-level checks.
■ Default2: Checks that the tag name used in the Golden design is exactly the same as
the tag name used in the Revised design. This rule is normally applied during RTL to RTL
checks.

Defining Tag and Attributes

For Verilog, the tag is defined as a label in the always block. For VHDL, the tag is defined
as a label in the process block. The label can be a user-specified string or an empty string.
■ For Verilog, the following is an example of a label lp_sel assigned to a tag:
always @(posedge clk)
begin : lp_sel
q <= d;
end

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■ For Verilog, the following is an example of an empty label assigned to a tag:


always @(posedge clk)
begin
q <= d;
end

■ For VHDL, the following is an example of a label lp_sel assigned to a tag:


begin
lp_sel : process(clk,we,addr,din,dout)
begin

In the synthesis LIBERTY library, the attributes are defined using the power_gating_cell,
is_isolation_cell, and is_level_shifter keywords. In the simulation library
(Verilog or VHDL), the attributes are defined using the ADD LOWPOWER CELLS command.
■ The following is an example of the power_gating_cell attribute defined in the
synthesis library:
cell (RET_DFF1) {
version : 1.0;
cell_leakage_power : 7E+03;
area : 15.10;
power_gating_cell : "LPRET_DFF1";

■ The following is an example of the power_gating_cell attribute defined in the


simulation library:
add lowpower cells RET_DFF1 -retention -attribute LPRET_DFF1

Defining User Rules

The following are examples of user-defined rules using the ADD RETENTION MAPPING
command:

Tag-Based Verification Example

The following command verifies that all registers with a tag label lp_sel* are implemented
with a state retention cell whose power_gating_cell attribute is LPRET_DFF1:
add retention mapping R0 -tag lp_sel* -attribute LPRET_DFF1

Module-Based Verification Example

The following command verifies that all registers in module blockA are implemented with a
state retention cell whose power_gating_cell attribute is LPRET_DFF1:
add retention mapping R1 -module dma -attribute LPRET_DFF1

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Instance-Based Verification Example

The following command verifies that all registers with instance name /U0/*/fifo_dma* are
implemented with a state retention cell whose power_gating_cell attribute is
LPRET_DFF2:
add retention mapping R2 -instance "/U0/*/fifo_dma*" -attribute LPRET_DFF2

Conditions for Added Rules

When adding these user-defined rules, the following conditions apply:


■ User-added rules always override the default rule.
For a description of the default rules that are added by the system, see the CHECK
LOWPOWER CELLS command
■ If a sequential element (DFF or DLAT) is covered by more than one rule, the last added
rule takes effect—it overrides all other rules.
■ The sequential elements which are not covered by any of the user-added rules are
automatically covered by the default rules.

Checking the Status

If at any time a state retention mapping rule is added or deleted, the status of all the
sequential pairs resets to ’Unknown’. You will need to run the CHECK LOWPOWER CELLS
command to set the status of the sequential pairs.

The following is an example of a default summary report after running the following
commands:
> set lowpower option -retention
> check lowpower cells
================================================================================
Summary Golden Revised
DFF DLAT DFF DLAT
================================================================================
Passed 8808 62 8808 62
Failed 0 0 0 0
Not Checked 0 0 0 0
--------------------------------------------------------------------------------
Total 8808 62 8808 62
================================================================================

================================================================================
Rule Name Passed Failed
================================================================================
R1 8808 0

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R2 62 0
--------------------------------------------------------------------------------
Total 8870 0
================================================================================

In the example, the reports shows the following:

Passed Reports all the sequential pairs that passed the default rule or user rule.
In the example report, the 8808 Passed DFF and 62 Passed DLAT
sequential elements are consistent between the Golden and Revised
Designs. The DFF is covered by rule R1, and DLAT by R2.
Failed Reports all the sequential pairs that failed the default rule or user rule.
Not Checked Specifies that the low power check was not done or was interrupted. In
addition, this status applies to the sequential points that were not mapped.
These unmapped sequential points can belong to either the Golden or
Revised design, and can be reported using the REPORT UNMAPPED
POINTS -Retention command.

Isolation Cell and Level-Shifter Cell Checking


For Isolation cells and Level-shifter cells, low power checking does the technology mapping
check and equivalence check.

You can assign isolation or level-shifter cells either through a LIBERTY attribute, or with the
ADD LOWPOWER CELLS command. For example, in the LIBERTY file, you can use the
following attributes:
is_isolation_cell : true;
is_level_shifter : true;

If using the Verilog library, you can assign these cells with the following commands:
add lowpower cells LS_BMF -level_shifter
add lowpower cells ISO_AND -isolation

Checking the Status

The technology mapping check ensures that for each low power cell (isolation cell or level-
shifter cell) in the Golden design, there is a corresponding low power cell in the Revised
design. To establish the correspondence, the Conformal software inserts key points (cut
gates) at the output of low power cells and performs name-based mapping. If it does not find
mapping for a low power cut gate, it sets the status of the corresponding low power cell to
Failed; otherwise, the status is set to Passed.

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The equivalence check ensures that for the mapped low power cell pair, the logic feeding
them is equivalent in both the Golden and Revised designs. To perform equivalence checking,
the isolation and level-shifter cells will be added to compare points, and these will be proven
equivalent or non-equivalent during compare (when running the COMPARE command).
Note: The CHECK LOWPOWER CELLS command performs only the technology mapping
check for isolation cells and level-shifter cells. The EC checking results are received after
running the COMPARE command.

After performing the low power check, a status summary is printed for all low power cells. The
following is an example of a default summary report after running the following commands:
> set lowpower options -isolation -level_shifter_cells
> check lowpower cells
================================================================================
Isolation Cells
================================================================================
Status Golden Revised
--------------------------------------------------------------------------------
Passed 64 64
Failed 0 0
Not Checked 0 0
--------------------------------------------------------------------------------
Total 64 64
================================================================================
Level Shifters
================================================================================
Status Golden Revised
--------------------------------------------------------------------------------
Passed 8 8
Failed 0 0
Not Checked 0 0
--------------------------------------------------------------------------------
Total 8 8
================================================================================

In this example, the reports shows the following:

Passed The 64 Passed isolation cells and 8 Passed level-shifter cells are
consistent between the Golden and Revised Designs.
Failed No (zero) isolation or level-shifter cell failed the technology mapping
check.
Not Checked No (zero) check was not completed or interrupted.

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LowPower Manager
Use the LowPower Manager to display unmapped and checked points, check key points, and
report the status of each checked point (Pass | Fail | Not-Checked).
➤ Choose Tools – LowPower Manager, or click on the LowPower Manager icon.

The LowPower Manager includes two columns. The left column contains Golden design
information and the right column contains Revised design information. Each column is

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divided into two sections. The top section is the Unmapped points portion and the bottom
section is the LowPower check portion.

By default, when you rest the cursor over a point, Conformal displays an information box that
identifies the point by name and lists pertinent details about it.

The LowPower Manager is divided into the following sections:


■ Unmapped Points—Lists all of the unmapped points in the mapping manager for Golden
and Revised designs.
■ LowPower Cell—Displays the following information depending on the low power cell
type: state retention cells, isolation cells, or level-shifter cells.
❑ State Retention Cells
The Statistic field specifies the number pairs that passed (in green), failed (in red),
or were not checked. The Rule field specifies the system rule or user-added rules.
The indicators for state retention cell types are described as follows:

Passed — The sequential pair passed the system rule or any of the
user added rules.
Failed — The sequential pair failed the system rule or any of the user
added rules.
Not Checked— The the low power check was not done or was
interrupted.

See State Retention Cell Checking on page 18 for more information.


❑ Isolation and Level-Shifter Cells
For isolation and level-shifter cells, this section checks that for each isolation cell in
the Golden design, there is a corresponding isolation cell in the Revised design.
The Statistic field specifies the number pairs that passed (in green), failed (in red),
or were not checked. The indicators for isolation cell types are described as follows:

Passed — The low power isolation or level-shifter cell passed the


technology mapping check between the Golden and Revised design.
Failed — The low power isolation or level-shifter cell failed the technology
mapping check between the Golden and Revised design.
Not Checked— The low power check was not done or was interrupted.

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See Isolation Cell and Level-Shifter Cell Checking on page 21 for more information.

Setting Preferences

Click the Preferences pull-down menu on the menu bar to specify the following viewing
preferences:

Unmapped Points On Customizes the display to show unmapped points.


Checked Points On Customizes the display to show checked points.
Sort by Rule Sorts the displayed gates by rule.
Sort by Name Sorts the displayed gates by name.
Sort by ID Sorts the displayed gates by ID.
Library Name On Display the suffixes when viewing mapped points.
Renaming Rule On Displays renamed rule names. This is especially useful for
determining how renaming rules affect a group of keypoints.

Refreshing the Window

Click the Refresh button to return the displayed gates to their original numerical order.
Note: When you change Pass/Fail Icon preferences, Conformal prompts you to refresh the
window.

Filtering the Display

Use the Find Check Points form to display points that match a specified string. Conformal
bases the filter on instance names.

To find a single point, refer to Finding Key Points on page 26.


Note: Conformal supports wildcards. For example, type *17* to display all points that
include 17 in either their name.

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➤ Click the Filter icon.

Filter Check Points Form Fields and Options

Check Rule Checks the rule in the filter.


Note: For state retention cells only.
Filter Specifies a string.
Display All Returns to the original display.

Note: If you click the Refresh button on the menu bar of the LowPower Manager, the original
unfiltered display returns.

Finding Key Points

Do the following in the LowPower Cell sections to locate points that contain the
specified search string.

1. Click the Find icon button located in the upper right corner of the appropriate section, or
press Ctrl-f. The section-specific Find form opens (for example, Find: Checked
Points).
2. Type any string or partial string of a key point name in the Find field.
3. Click the Find Forward or Find Backward check box to specify the direction of the
search.
4. Click the Case Sensitive check box, if applicable.
5. Click the Find button to search for the name.

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6. Repeat step 5 to find the next point that fulfills the search criteria.

Displaying Specified Classes of Points

In the LowPower Cell section, use the following procedure to display specified
classes of points.

1. Click the Class icon located in the upper right corner of the LowPower Cell section.
2. Choose one or more of the classes.
All displays all of the categories (Pass, Fail, and Not-Checked). Disable All deselects
all of the categories.

Running the Low Power Check

To run the technology mapping check or the equivalence check, or both, depending on the
low power cell type, click on the green check mark to the right of the Class button.

For more information on low power checking, see Running Low Power Checks on page 17.

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LowPower Diagnosis Manager


You can use the LowPower Diagnosis Manager to display the error candidates for both the
Golden and Revised designs for state retention cells.
1. Click on a mapped point in the LowPower Manager.
2. Right-click and choose Diagnose from the pop-up menu.

The LowPower Manager is divided into the following sections:


■ Checked Point—Displays the mapped low power cell pair in both the Golden and
Revised designs. According to the rule on which the mapped point passes or fails, the

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Golden side could be Module, Instance, Tag or Power Gating Cell Attribute and the
Revised side could be a Tag or Power Gating Cell Attribute.
■ Rule Name—Specifies all the rules for the state retention cell.
■ Instance, Module, or Tag—Specifies the instance, module, or tag name of the rule.
■ Attribute—Specifies the attribute of the rule.
The text color indicates the status of state retention cells. Green indicates that the
sequential pair passed the system rule or any of the user added rules. Red indicates that
the sequential pair failed the system rule or any of the user added rules.

Viewing a Schematic of a Point

Use the following procedure to select a point in the LowPower Cell section of the LowPower
Manager and view a schematic of the selected point.
1. Click a point in either the Golden or Revised column in the LowPower Cell section.
2. Right-click and choose Schematics from the pop-up menu.
The schematic viewer opens and highlights the selected point.

From the LowPower Diagnosis Manager, you can open the schematic by clicking the
Schematic button from the Menu Bar.

Locating a Point in the Schematic (Drag-and-Drop)

Use the following procedure in the LowPower Cell section of the LowPower Manager as a
convenient way to locate and highlight a specified point in the schematic. This feature also
works in the reverse drag-and-drop order (drag from the Flatten Schematics window to a
section in the LowPower Diagnosis Manager).

Tip
Begin this procedure with the schematic viewer open and the Mapping Manager
active.
1. Click and hold the middle mouse button over a point in the LowPower Cell section.
2. Drag the point from the LowPower Diagnosis Manager to the Flatten Schematic window.
When you click with the middle button, the LowPower Diagnosis Manager displays the
name of the point you clicked in an ivory text box. As you move the point to the new

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window, the background of the text box changes to black if the object is in a window
where you can drop items.
3. Release the middle mouse button, and the point is highlighted in the Flatten Schematic.

Sample Dofile
The following is an example of a Conformal dofile that includes the Conformal Low Power
Equivalency Checking flow.
// Read ASIC vendor library
read library ../library/lib/LP.lib -liberty -both
// Read RTL and gated-level netlist
read design ./rtl/top.v -golden
read design ./netlist/top_final.v -revised
// Report design information
report design data
report black box
// Enable isolation check, level-shifter check, and state retention check
// This requires Conformal LP license
set lowpower option -auto
// Define design constraints
add pin constraint 0 SCAN_EN -both
add pin constraint 0 RET -both
// Check all registers of the module "blockA" with LP attribute
// LPRET_DFF1 implementation
add retention mapping R1 -module blockA -attribute LPRET_DFF1
set system mode lec
// Run lowpower checks
check lowpower cells
// Run flatten EC comparison
add compare point -all
compare
usage

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CPF Low Power Cell Insertion Flow


This section describes the standard flow for CPF low power cell insertion.

Figure 2-2 CPF Low Power Cell Insertion Flow

Read design and library

Read the CPF File See Reading the CPF File on page 32

Perform low power cells


insertion based on CPF See Performing Low Power Cell Insertion on
definition

Specify design constraints


and modeling options

Mapping (perform state


retention cell checking)

Compare

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Reading the CPF File


The CPF file defines the low power intent for the designs. Cadence recommends reading in
all the CPF files with a single READ CPF command. Any subsequent READ CPF commands
will replace all the low power information issued by the previous READ CPF command.

After parsing the CPF files, you can perform low power cell insertion on the Golden design by
running the COMMIT CPF -insert command. You can insert the following low power cell
types:
■ level shifter cells
■ retention cells
■ isolation cells
■ combined level shifter and isolation cells (combo cells)

Cadence recommends specifying the design constraints after reading in and committing the
CPF files because some design constraints specified on power boundary crossing nets could
be lost after the low power cells have been inserted.

During mapping, the state retention cell checking will be done automatically. The state
retention mapping rules are derived from the following CPF commands in the CPF files:
■ define_state_retention_cell
■ create_state_retention_rule

You can use the REPORT LOWPOWER DATA command to report the status of state retention
cell checking between the Golden and Revised designs.

After the low power cells (which were specified in the CPF files), are inserted in the Golden
design, the subsequent COMPARE command will check the functional equivalency between
the Golden and Revised designs.
Note: Level shifter and isolation cell checking are disabled in the CPF low power cell insertion
flow.

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Performing Low Power Cell Insertion


In Equivalency Checking, use the COMMIT CPF -insert command to insert low power cells
defined in the CPF files.

The following shows an example of a dofile that inserts low power cells after reading in two
CPF files named rtl.cpf and my_library.cpf:
read library -liberty my_library.lib -both
read design rtl.v -verilog -golden
read cpf rtl.cpf my_library.cpf
commit cpf -insert
read design gate.v -verilog -revised
add compare point -all
compare

Power Domain Schematic Color Coding


After successfully reading in CPF files, all the instances in the schematic viewer from the main
LEC window are color coded with power domain definition.
Note: In the Hierarchical (Module) schematic viewer, the power domain color coding is on by
default. In the Flattened Schematic viewer, you can enable this feature by selecting Show
Power Domain in the Preferences menu.

In the following figure, instances counter_inst and state_inst are colored blue,
indicating they belong to same power domain. The low power cells inserted by the Conformal
Low Power software, pd_inst_2 and pd_inst_3, have their own color coding.

pd_inst_2
pd_control2
state_inst
state
counter_inst pd_inst_3

counter pd_control1

If you move the mouse pointer over counter_inst, it will display the domain name, voltage
that it operates on, and if it is a switchable domain or an always-on domain.

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For example, the following figure shows that its domain name is PD1, and its voltage is 0.8
and is an always-on domain:

counter_inst
counter

instance: counter_inst
module definition: counter
instances: 10
nets: 35
Power Domain: PD1
Voltage: 0.8 (always on)

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Running Low Power Extended Checks

■ Low Power Functional Checking Flow on page 36


■ Starting Conformal Low Power (Extended Checks) on page 37
■ Specifying Low Power Checks on page 38
■ Validating Low Power on page 39
■ Power Control Modules on page 39

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Low Power Functional Checking Flow


This section describes the tasks involved in running low power for the Conformal Extended
Checking software. The following diagrams show a standard flow for functional checking,
which includes the addition of low power. In the flow diagrams, the white boxes indicate the
tool actions, and the gray boxes indicate the user actions.

Figure 3-1 shows the Setup mode part of the Low Power flow.

Figure 3-1 Low Power Extended Checking Flow (Setup Mode)

Setup Mode

Data entry for


design and library

Parse netlist and


check for errors

Define low power


cells and power pins

Specify design
Constraints

Analyze power See Analyzing Power Domains on page 58


domain

Define clock
initialization
sequence

Verify Mode

Figure 3-2 continues the flow after switching to Verify mode:

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Figure 3-2 Low Power Extended Checking Flow (Verify Mode)

Verify Mode

Modeling and Flattening

Add Power Check See Specifying Low Power Checks on page 38

Validate See Validating Low Power on page 39

Debug See Low Power Manager on page 60

Design No
Debug
Passed?

Yes

DONE

Starting Conformal Low Power (Extended Checks)


To start the software in non-graphical mode, run the following command:
lec -verify –NOGui –lp

To start the software in graphical mode, run the following command:


lec -verify [-Gui] –lp

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Specifying Low Power Checks


You can use the SET LOWPOWER OPTION command to specify the tool environment or global
behavior of the low power checks. Some of these checks are for the following:
■ Netlist Style—used to indicate that the design is a physical netlist (with power
connectivity), or that the design is a logical netlist (without power and ground nets). To
specify a physical or logical netlist, respectively, use the following commands:
set lowpower option –netlist_style physical
set lowpower option –netlist_style logical

■ Isolation Cells—used to perform standard or advanced isolation cell rule checks.


Advanced isolation checks identify all valid electrical errors and is less constraining than
the standard check. Use the following command:
set lowpower option -isolation_check advanced

You can specify the need for on-to-off isolation. In logical netlist, anytime there is an
isolation rule specified between two domains, the isolation cells between them will not
be flagged as redundant if they can be on-to-off (that is, on-to-off isolation is assumed to
be needed between them). Use the following command:
set lowpower option -on_to_off_iso

In addition, you can specify the global limit on the number of isolation control pins driven
by the same signal. Use the following command:
set lowpower option -isolation_limit <limit>

■ State Retention Cells—used to specify the global limit on the number of retention control
pins driven by the same signal. Use the following command:
set lowpower option -retention_limit <limit>

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Validating Low Power


For the Low Power flow, you can use the REPORT VALIDATED DATA command to report
validated results of added power checks. The following shows an abbreviated portion of the
syntax for low power:
REPort VAlidated Data
[ -ALL
| -ISOlation
| -CROssing
| -RETention

With the -ISOlation option, you can report only isolation cells, including isolation assertion
checks.
With the -CROssing option, you can report only crossing failures. You can include all or
specific crossing from the specified power domain(s), which are the starting (source) and he
ending (destination) power domain(s) of the crossing failures.

With the -RETention option, you can report only state retention cells, including the clock
value functional check.

For the complete syntax and command description, see REPORT VALIDATED DATA in the
Encounter Conformal Extended Checks Reference Manual.

Power Control Modules


When the design includes a power control module, you can run a complete Formal proof. The
initialization sequence of this controller is required for a successful Formal check. It might also
be necessary to cut inputs to the power controller to separate this controller from the design
function.

When the design does not include a power control module, and the power control are input
ports, you must express the relationships of these inputs with a
$constraint(expression) statement in the netlist or as an append to module in a
separate file. For example, if poweron1 and poweron2 relationships are 00, 01, and 11, this
means that 10 does not occur and you would use the following expression:
$constraint(!(poweron1&&!poweron2);

Based on this expression, Low Power will check the validity of the isolation between the
domains controlled by these ports, and find any errors where the isolation fails under this
constraint.
Note: Open Verification Library (OVL) can also be used as constraints to express such
relationships.

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Running Logical Netlist Checks

The Conformal Low Power logical netlist checking works on netlists without power and ground
nets. It checks level shifters locations and isolation cell types and locations.

Figure 4-1 Logical Netlist Low Power Checking Flow

Set Options

Library Read Netlists


and
Design
Define Domains

Define Low Power


Cells

Add Rules

Analyze Power Domain

Functional Setup

Reports
Checks and Debug
and
Logs

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Setting Options and Reading Logical Netlists


The first step in running the low power checking is to specify the tool environment for a logical
netlist with the following command:
set lowpower option –netlist_style logical

Then you will need to read in the libraries and the designs. For example:
read library lib1.lib -liberty
read library lib2.v -verilog -append
read design des1.vhd -vhd -noelaborate
read design des2.v -verilog

Design Verification Setup


Use the SET LOWPOWER OPTION command to specify the tool environment for global
behavior of low power checks. For isolation cell checking, use the following option:
-isolation_check advanced

Depending on the voltage crossing check requirement, there are three options you can use
for level-shifter cell checking:
-ignore_high_to_low [<tolerance>]
-ignore_low_to_high [<tolerance>]
-level_shifter_check connect

Defining Power Domains


You can use the ADD POWER DOMAIN command to define the power domain of a specified
instance or module. If module is specified, the Conformal low power software will define a
different power domain for each instantiation of this module.
Note: In the logical netlist style, you can use this command to define power domains for all
instances.

The following shows an example dofile:


add power domain pdom1 -voltage 1.2 -instance x1 –standby
add power domain pdom2 -voltage 1.2 -instance x2
add power domain pdom3 -voltage 1.5 -instance x3
add power association –pin datain* -domain pdom2
add power association –pin dataout* -domain pdom3

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Power Domain Example

Default domain is 1.0v


In pins driven by 1.0v
X1 is a local 1.2v
Out pins drive to 1.5v

The following shows the command entry for the example design information:
add power domain TopD -voltage 1.0 –module TOP
add power association –pin In* –domain TopD
add power domain LocD -voltage 1.2 -instance X1
add power association –pin Out* -virtual v15 1.5

Defining Low Power Cells


Example dofile commands
add isolation cell iso_hi -Isopins iso
add level shifter ls_lh 1.0 1.2 –data_in A –data_out Y

You can identify isolation and level shifter cells by writing a script to read the Liberty file and
identify cells with the is_isolation_cell or is_level_shifter attribute.
Note: The Conformal Low Power Verify mode does not identify these cells automatically like
the Equivalency Checking application does.

Defining Isolation Rules


Use the ADD ISOLATION RULE command to define an isolation rule for every pair of power
domains for the Conformal Low Power software to check for isolation cells.

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Isolation Cell Checks


These checks are related to power domain crossings without proper isolation, and improper
use of power domain cells. The following shows an example.

X1 can be put into standby mode


X2 can not be put into standby mode
Need isolation at X2 for nets from X1
Isolation state must be high (OR)
Wrong domain for n1 isolation
Wrong isolation type for n3
Missing isolation for n4

To find isolation errors for this example:


add power domain pd1 -voltage 1.0 -instance X1 -standby
add power domain pd2 -voltage 1.0 -instance X2 -nostandby
add isolation cell Iso0 –isopin iso
add isolation cell iso1 –isopin iso
add isolation rule r1 –source pd1 –dest pd2 –type HIGH –location destination
analyze power domain

Level Shifter Checks


Level shifting is a technique to transport a signal from one voltage value to a higher or lower
voltage value.

X1 is a 1.0v domain
X2 is a 1.2v domain
X3 is a 1.2v domain

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To find errors for this example:


add power domain lv -voltage 1.0 -instance X1
add power domain hv1 -voltage 1.2 -instance X2
add power domain hv2 -voltage 1.2 -instance X3
add level shifter LS 1.0 1.2 –data_in A –data_out Y
analyze power domain

Isolation and Level Shifter Cells


The following shows a combined isolation and level shifter cell definition.
■ Level shifter and isolation checks are done independently
■ Define inputs driven by level shifter input voltage with the -data_in option
■ Define inputs driven by level shifter output voltage with the -data_out option

X1 is a 1.0 Voltage Domain


X2 is a 1.2 Voltage Domain

If X3 is a 1.0 voltage domain, run the following command:


add level shifter IsoLH 1.0 1.2 –data_in A Iso –data_out Y

If X3 is a 1.2 voltage domain, run the following command:


add level shifter IsoLH 1.0 1.2 –data_in A –data_out Iso Y

Define isolation cell for isolation checking:


add isolation cell IsoLH –isopin Iso

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5
Running Physical Netlist Checks

The Conformal Low Power physical netlist checking works on netlists with power and ground
nets. It completes checks for level shifter, isolation, and state retention cells. Physical netlist
checks include power gating and power connectivity.

Figure 5-1 Physical Netlist Low Power Checking Flow

Set Options

LEF,
Library Read Netlists
and
Design
Define Domains

Define Low Power


Cells

Add Rules

Analyze Power
Domain

Functional Setup

Reports
Checks and Debug
and
Logs

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Running Physical Netlist Checks

Setting Options and Reading Physical Netlists


The first step in running the low power checking is to specify the tool environment for a
physical netlist with the following command:
set lowpower option –netlist_style physical

Then you will need to read in the libraries and the designs. The data requirements for the
libraries are as follows:
■ Verilog netlist with full power connectivity
This includes top-level power pins, power pins at every level of the hierarchy, and power
pins for standard cells and macro blocks.
■ Accurate power switch models
These can be modeled as a tri-state buffer. For example:
bufif1 (VDD_OUT, VDD_IN, ENable)

Reading in the LEF, Library and Design


1. Use the READ LEF FILE command to read in the LEF file.
For each library cell in the LEF database with matching library cell, use the READ LEF
FILE command to report library cell with ports that are not in the LEF file, report non-
power or ground ports in the LEF file and not in library, and add all ports in the LEF file,
and not in library to library cell.
read lef file <path* ...>

2. Use the READ LIBRARY command to read in the Library


read library <path* ...>

3. Use the READ DESIGN command to read in the design.


read design <path* ...>

Handling Special Cells


Identify special physical cells by performing the following actions:
1. Run the Low Power library flow with the existing library.
2. Read the library and design.
3. Analyze missing module definition errors.

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Design Verification Setup


Use the SET LOWPOWER OPTION command to specify the tool environment for global
behavior of low power checks. For isolation cell checking, use the following option:
-isolation_check advanced

Depending on the voltage crossing check requirement, there are three options you can use
for level-shifter cell checking:
-ignore_high_to_low [<tolerance>]
-ignore_low_to_high [<tolerance>]
-level_shifter_check connect

Defining Power Domains


You can use the ADD POWER DOMAIN command to define the power domain of a specified
instance or module. (If module is specified, the Conformal low power software will define a
different power domain for each instantiation of this module.)
Note: In the physical netlist style, you should only use this command to define power
domains for blackboxed instances. The power domains of other instances are automatically
derived from the power nets that supply power to those instances.

You can define power domains and their power connectivity with the following ADD POWER
commands:
■ Define power domain for power pin groups:
add power pin <domain> <primary_pin> -voltage <voltage>
[-nonstandby | -standby <expr>]

■ Add power domains for black boxed cells:


add power domain <domain> <voltage> <cell_name> -module

■ Define top-level ground ports


specify ground pins <pin_name>

■ Associate power domains for top level data ports:


add power association -pin <pin* ...> -domain <domain>
add power association -pin <pin* ...> -virtual <domain> <voltage>

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■ Associate power domains for top level data ports and black box cell data ports:
add power assoc <cell_name> -power <pwr_pin> <pin* ...>

Power pin v10 is 1.0v


In pins driven by 1.0v
Power pin v12 is 1.2v
Out pins drive to 1.5v

The above example shows this command entry:


add power pin vlo v10 -voltage 1.0
add power association -pin In* -domain vlo
add power pin vhi v12 -voltage 1.2
add power domain v15 1.5
add power association -pin Out* -domain v1.5

Black Boxes
Black boxes can connect to multiple power domains. You can define power domain with
default always on power pin to have the tool check that the net connected to this pin is always
on. Then associate the data and power pins to the power domain.

The following example shows a black box to power domain vbb

Using this example, you would check that the net connected to the always_on pin is always
on:
add power domain vbb -voltage <V> -module IP1 -power V2

Then associate the data and power pins:

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add power association IP1 -power V1 C* D* -power V2 X* Y* Z*

Defining Power Cells


The following section show command examples for defining power switches, retention
isolation cells, and level-shifter cells.

Defining Power Switches


When defining power switches, you only need to define power pins and enables. You do not
need to define feedthroughs and unrelated pins because these, and other functions, are
analyzed by the Conformal low power software.

Use the ADD POWER SWITCH command to define power switches. For example:
add power switch PSW VDD VSW -standby Ei
add power switch PSW VDD VSW -standby Ei -control_power VDC -max_enable_bias 0.4

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Defining Retention Cells


Use the ADD RETENTION CELL command to define retention cells, retention function, and
power pins. For example:
add retention cell SR_DFF -ret Ret -Clock_off !Clk -power VDD VDDC -data D

VDD is for gated power net


VDDC is for always on power net
Ret is active high retention control

Defining Isolation Cells


Use the ADD ISOLATION CELL command to define a dedicated low power isolation cell, or
a standard cell as an isolation cell to allow the isolation to control any input pin. You can use
a dedicated isolation cell only for isolation, and you can use a standard isolation cell for
isolation as well as regular logic.

Dedicated Isolation Cells

The following shows an example of defining dedicated low power isolation cells:
add isolation cell Iso_An1 -isopin IsoB -vdd VDD -vddiso VDDC

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add isolation cell Iso_An2 -isolate !IsoB -vdd VDD A

Standard Isolation Cells


You can define standard low power isolation cells that you can use to allow the isolation to
control any input pin. The synthesized design can use these cells as regular logic. The
isolation structural and functional checking will ignore any standard cell not used as
isolation.
For example:
add isolation cell SC_AND2 -nondedicated -vdd VDD -vss VSS

Identifying Isolation Cells

The Liberty library usually contains some information on isolation cells. You can use the
following script to help define isolation cells:
cat <liberty_directory>/*.lib | awk ’{ \
if ($1 == "cell") cell = $3; \
if ($1 == "pin") pin = $3; \
if ($1 == "isolation_pin") { \
printf("cell=%s pin=%s\n",cell,pin);} \
}’

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Level Shifter Cells


Use the ADD LEVEL SHIFTER command to define the cells that are used to shift voltage
signal levels and specify the input and output voltage-level power pin of the level shifter. For
example:
add level shifter lshift1 <vin> <vout> -vdd_in VI -vdd_out VO -data_in A -data_out Y

add level shifter lshift2 <vin> <vout> -vdd_out VDD -data_in A -data_out Y

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Combination of Level Shifter and Isolation Cells


The following commands show the usage for a combination of level shifter and isolation cells:
add level shifter LS 0.9 1.2 -data_in A -data_out E Y -vdd_in VI -vdd_out VO
add isolation cell LS -isopin E -vdd VO -extra_power VI -vss VSS

add level shifter LS 0.9 1.2 -data_in A E -data_out Y -vdd_in VI -vdd_out VO


add isolation cell LS -isopin E -vdd VO -extra_power VI -vss VSS

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Defining Rules
After adding the power domains, you can specify how you expect isolation or retention to be
implemented by defining valid rules for checking isolation and retention cells, using the ADD
ISOLATION RULE and ADD RETENTION RULE commands.

For example, if you define a retention rule with the following command:
add retention rule rule1 -retention a1/Y -instance i0 i1

And there is a situation such as in the following illustration:

Y
a0

RET RET RET

i0 i1 i2

a1

the Conformal software will issue a RETRULE1.1 message for retention cell instance i1
because its retention control RET is not connected to a1/Y.

Switch Rules
A switch rule specifies the enabling condition of the switches driving the specified domain or
the output power or ground net. You can use the ADD SWITCH RULE command to define a
switch rule to be verified for the specified output domain.

In the following example, there is one external power net POWER_IN that drives a switched
power net POWER_SWITCHED through a set of parallel switches. The switched power net
POWER_SWITCHED powers the domain D. The switches have a single enable pin EN, that
should be driven by the pin ctrl/OUT.

For this example, the switch rule can be specified in any of the following ways:
add switch rule r0 -DOMain D -ENAble ctrl/OUT
add switch rule r0 -DOMain D -POWER_IN POWER_IN -ENAble ctrl/OUT
add switch rule r0 -POWER_OUT POWER_OUT -POWER_IN POWER_IN -ENAble ctrl/OUT

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add switch rule r0 -POWER_OUT POWER_OUT -ENAble ctrl/OUT

POWER_IN IN OUT POWER_OUT

OUT EN

IN OUT

EN
TO
IN OUT Domain D

EN

In the following example, the switch has multiple enable pins. So, rules should specify the
hierarchical instance pin that should control each of these pins, as follows:
add switch rule r1 -domain D -ENABLE_pin EN1_IN -SWITCH_PIN EN1
add switch rule r2 -domain D -ENABLE_pin EN2_IN -SWITCH_PIN EN2

PIN IN
POWER_OUT
EN1_IN EN1 Domain D

EN2_IN EN2

The following is a more complicated scenario where multiple power nets drive the same
output domain through multiple parallel switches with multiple switch enable pins. The output
power net POWER_OUT is driven by two switches sw1 and sw2. The input powers of sw1
and sw2 come from external power net PIN1 and PIN2 respectively.

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In this case, four rules should be specified, and the input power net must be specified for each
rule.
add switch rule r11 -power_out POWER_OUT -enable EN1_1 -switch_pin EN1 \
-power_in PIN1
// for EN1 of sw1
add switch rule r12 -power_out POWER_OUT -enable EN2_1 -switch_pin EN2 \
-power_in PIN1
// for EN2 of sw1
add switch rule r21 -power_out POWER_OUT -enable EN1_1 -switch_pin EN1 \
-power_in PIN2 +
// for EN1 of sw2
add switch rule r22 -power_out POWER_OUT -enable EN2_1 -switch_pin EN2 \
-power_in PIN2
// for EN2 of sw2.

PIN1 IN
POWER_OUT
EN1_IN EN1SW1

EN2_IN EN2
Domain D

PIN2 IN

EN1_IN EN1SW2

EN2_IN EN2

Analyzing Power Domains


Once the design netlist is read in and all special low power cells are reported, you can use
the ANALYZE POWER DOMAIN command to calculate the power domain information for the
design and performs structural checks for isolation cells, always on cells, and power domain
cells.

When bringing up the schematic view, the power domains are color coded. The colors
represent different switch domains and voltage domains. Blue (by default) represents the
continuous power domain.

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6
Low Power Diagnosis

■ Low Power Manager on page 60


❑ CPF on page 60
❑ Logical Check on page 62
❑ Functional Check on page 63
❑ Running Low Power Checks on page 64
❑ Viewing Source Code and Schematics on page 64
■ Functional Verification Debugging on page 65
❑ Isolation Functional Failure - True Failure on page 65
❑ Isolation Functional Failure - X Assignments on page 66
❑ Power Domain Crossing Failure on page 67
■ Debugging Combinational Loops on page 68

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Low Power Diagnosis

Low Power Manager


To access the Low Power feature, click on the Power Rule Manager icon located on the icon
bar in the main window, or select Power Rule Manager from the Tools drop-down menu.

This will bring up the Low Power Manager. In this form there are the following three tabs:
■ CPF
■ Logical Check
■ Functional Check

For each category, the tab displays a red circle or a green circle to
indicate whether messages were generated in that category. If you
prefer, Conformal displays check marks (red X or green check).

CPF
The following shows an example of the Low Power Manager’s CPF (Common Power Format)
page with the CPF Power Domain tab selected:
Note: The CPF tab is only active after the CPF files have been read.

By default, the Low Power Manager displays only the CPF quality checks with violations. To
view a complete list of the various rules as well as detailed rule violation information, click
Option and choose View – All.

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The following panels are in the CPF page:


■ CPF Power Domain—reports any of the check violations for power domain cells that
were defined with the create_power_domain CPF command.
■ CPF Isolation—reports any of the check violations for isolation cells that were defined
with the create_isolation_rule CPF command.
■ CPF Level Shifter—reports any of the check violations for level-shifter cells that were
defined with the create_isolation_rule CPF command.
■ CPF Retention—reports any of the check violations for state retention cells that were
defined with the create_state_retention_rule CPF command.
■ CPF Power Ground— reports any of the check violations for power and ground nets
that were defined with the create_power_nets and create_ground_nets CPF
commands.
■ CPF Miscellaneous—reports any miscellaneous check violations for low power objects
that were defined with CPF commands.

For the description of a rule message, click on the message to display the description at the
bottom of the Low Power Manager. For more information on a message, see the “Common
Power Format Rule Checks” chapter in the Encounter Conformal Low Power
Reference Guide, or type ‘help <rule>’ in the command line.

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Logical Check
The following shows an example of the Low Power Manager’s Logical Check page with the
Power Domain tab selected:

By default, the Low Power Manager displays only the rule checks with violations. To view a
complete list of the various rules as well as detailed rule violation information, click Option
and choose View – All.

The following panels are in this Logical Check page:


■ Power Domain—reports any of the logical (or structural) check violations for power
domain cells that were added with the ADD POWER DOMAIN command.
■ Power Switch—reports any of the logical (or structural) check violations for power
switch modules that were added with the ADD POWER SWITCH command.
■ Isolation Cell—reports any of the logical (or structural) check violations for isolation
cells that were added with the ADD ISOLATION CELL command.
■ Always_on Cell—reports any of the logical (or structural) check violations for
always_on cells that were added with the ADD ALWAYS_ON CELL command.
■ Retention Cell—reports any of the logical (or structural) check violations for state
retention cells that were added with the ADD RETENTION CELL command.
■ Level Shifter—reports any of the logical (or structural) check violations for level-shifter
cells that were added with the ADD LEVEL SHIFTER command.

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■ Transistor Usage—reports any of the logical (or structural) check violations for pre-
defined rules at the transistor level.
■ Structural—lists all of the checks for structural low power design errors.

For each cell, you can click the cell row to highlight the cell name and description, then click
the right mouse button to bring up the pull-down menu where you can select from the
following options:
■ Severity—Changes the message severity level. You can choose Warning, Error,
Ignore, or Note.
■ Report—displays the status of the predefined rules. You can select on of the following:
❑ Summary—displays a complete list of the predefined rule messages that
Conformal Equivalence Checker has generated for your design.
❑ Verbose—expands the display to include the messages and full path(s) of the low
power cell(s).

Functional Check
The following shows an example of the Low Power Manager’s Functional Check page with
the Isolation Cell tab selected:

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The following panels are in this Functional Check page:


■ Isolation Cell—Lists all the isolation cell instances for which functional checks were
performed. Green indicates that the functional check property passed. Red indicates that
the functional check property failed.
■ Retention Cell—Lists all the state retention cell instances for which functional checks
were performed.
■ Crossing—Lists all of the local power domain crossings for which functional checks
were performed. These are the starting (source) power domain(s) of the crossing
failures.

Running Low Power Checks


For each cell or crossing, you can click the row to highlight the name, then click the right
mouse button to bring up the pull-down menu where you can select from the following options:
■ Add Power Check—applies the power check to the selected low power object.
■ Delete Power Check—removes the power check from the selected low power object.
■ Report Power Check—reports the power check information on the selected low power
object.
■ Diagnose—diagnoses failures reported after doing functional checks on the selected
low power object.
■ Report Validated Data—displays information about validation results of added power
checks.

Viewing Source Code and Schematics


You can investigate these violations using the source code or schematics from the Low Power
Manager to highlights the relevant line of code or highlights the relevant schematic object,
respectively.

To open either the Source Code or Schematic viewer, use the following steps:
1. Click the + symbol preceding the cell to fully expand the entry.
2. Click an occurrence to select and highlight it.
3. Right-click and choose Source Code or Schematics from the pop-up menu.

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Functional Verification Debugging


This section describes the debugging of three issues in functional verification mode:
■ Isolation Functional Failure - True Failure on page 65
■ Isolation Functional Failure - X Assignments on page 66
■ Power Domain Crossing Failure on page 67

Isolation Functional Failure - True Failure


This isolation functional failure is for true failures, in most cases.
1. In the Conformal main window, click the Low Power Manager icon to open the Low
Power Manager.
2. In the Low Power Manager, click the Functional Check tab.
3. Select the module in the module panel, and right click on the errors (represented by red
dots) on the Instance panel.
4. Click Diagnose option from the pull-down menu.
This opens the Waveform Viewer and show the diagnosis information for the selected
instance, as shown in the following output:

Cause of failure:
At time 0 power of input pin ’A’ was off
but isolation condition was not asserted

Counter example:
Time Unit 0:
1’b0 => 3: count
1’b0 => 3: count

Time Unit 2:
1’b0 => 3: count

Power source of input pin ’A’:


domain2/pd2/VO
Isolation expression: EN
Key point(s):
Gate: ctrlr/PE2 (domain2/pd2/EN), Id: 28, Value 1’b0
Gate: 1’b0 (domain2/pd3_iso/EN), Id: 93, Value 1’b0

// Use the ’REPort GAte’ command to access simulation results

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In the output example, the isolation control was not asserted when the input signal
driving pin A of isolation cell was turned off. Hence, there is a failure in the isolation
function. This is due to one of the following reasons:
❑ Bad isolation logic in the power control circuitry
❑ The power control might generate the isolation condition properly, but the signal
might be inverted, or gated before connecting to the isolation enable pin of the
isolation cell (ECO is one part of the flow that could cause this).

Isolation Functional Failure - X Assignments


Another possible scenario where functional failure could occur is bad initialization. For
example, the following log file shows a diagnosis of an isolation failure:

Isolation control assert check of ’domain2/pd3_iso’ is Fail


Cause of failure:
At time 0 power of input pin ’A’ was off
but isolation condition was not asserted

Counter example:
1’b0 => 3: count

X Assignments
1’b0 => 12: ctrlr/count_reg[0]
1’b0 => 13: ctrlr/count_reg[1]
1’b1 => 14: ctrlr/count_reg[2]

Power source of input pin ’A’:


domain2/pd2/VO
Isolation expression: EN
Key point(s):
Gate: ctrlr/PE2 (domain2/pd2/EN), Id: 29, Value 1’b0
Gate: ctrlr/ISO2 (domain2/pd3_iso/EN), Id: 26, Value 1’b0

// Use the ’REPort GAte’ command to access simulation results

The log shows that there are some X assignments on some of the flops in this path. This is
due to bad initialization in the init.seq or the VCD file. If you see such a log, the first thing
you should do is inspect the “reset control” in the init sequence file. The following depicts one
such error:
0 0 -BBOX
0 1 VDD
0 0 VSS
//0 0 RST_N
2000

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The RST_N line of init seq file is commented, which indicates that the design will not be RESET
properly before the verification takes place. This causes X assignments. One of the primary
reasons the RESET could be missed is because of the difficulty to trace this signal all the way
down to the power control logic. The signal that is intended to be used by the RTL might be
floating due to changes that happened during the place and route flow. It is important to check
this or the results of functional verification will not be accurate.

Power Domain Crossing Failure


This issue is relatively easier to debug. The power domain crossing involves missing isolation
cells. The debugging steps are similar.
1. In the Conformal main window, click the Low Power Manager icon to open the Low
Power Manager.
2. In the Low Power Manager, click the Functional Check tab.
3. Select the Crossing tab.
4. Select the instance name in the Domain Source panel.
5. Right click on the errors (represented by red dots) on the instance (from/to) panel.
6. Click Diagnose from the pull-down menu.

Diagnosis information

This will show the diagnosis information for the selected instance on the Conformal verify
window.

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At time 2, the power driving 2nd input of gate ’domain3/pd3_or/x1’ is down


but the other input cannot isolate the floating input

Gate type of ’domain3/pd3_or/x1’: OR

Counter example:
Time Unit 0:
1’b0 => 3: count
1’b0 => 5: din1
1’b1 => 4: din2
1’b0 => 6: sleep

X Assignments
1’b0 => 80: $LOOP1
1’b0 => 18: domain1/pd1_flop/Q_reg/Q

Time Unit 2:
1’b1 => 3: count

Power source of input 2 (floating input):


domain2/pd2/VO
Key point(s):
Gate: ctrlr/PE2 (domain2/pd2/EN), Id: 29, Value 1’b0
Gate: topAND/x1 (input 1), Id: 54, Value 1’b0

// Use the ’REPort GAte’ command to access simulation results

The log shows that the problem cell is an OR gate. The second input of this OR gate is driven
by a switched power supply. The log also shows that the input 1 of this OR gate is driven by
an instance topAND/x1, whose value is a 1’b0. The problem here is, we need a 1’b1 in
order to block the floating signal from propagating through the OR gate. Hence, there is no
proper domain isolation in this case.

Debugging Combinational Loops


Combinational loops (STRC1.1, STRC1.2, CLP_STRC1.1, CLP_STRC1.2) can be difficult to
debug. The following is a two-step approach to understand the complete debugging process
of combinational loops.
1. In the Conformal main window, click the Low Power Manager icon to open the Low
Power Manager.
2. In the Low Power Manager, click the Logical Check tab.
3. Click on the Structural tab.

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4. Select any of the violations (for example, CLP_STRC1.1), and expand the list to select
one of the violating instances.

Right click on the instance name and choose Schematic – Show Module Schematic to
open the schematic as shown in the following figure.

The command to report this on text window is:


report rule check CLP_STRC1.1 -verbose.

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The result of the command in this case is:


CLP_STRC1.1: Low power cell in strong combinational loop
Severity: Error Occurrence: 1
1: Pin ’A’ of ’m2/xicomb’ (ISO_OR) is in a strong combinational loop

From the schematic, it is apparent that the ISO_OR cell is involved in a combinational loop,
and because this is a small path, you can also traverse the path manually to see the
combinational loop. But in a real design, tracing this path is not as easy.

In order to do this, use the REPORT PATH -loop command as follows:


report path -loop m2/xicomb/x2 -strong

where x2 is the instance beneath the ISO_OR module.

When you run this command, the software gives a complete path of the combinational loop.
In this example, there are two paths to the loop, and both are listed here:
Strong combinational loop from m2/xicomb/x2 (18):
OR : m2/xicomb/x2 (18) ? ORIGIN
BUS : m2/xicomb/a1$BUS (10)
BUF : $ID32 (32)
BUF : m2/xb1/x1 (19) ? PATH 1
BUS : m2/xcombLoop/X$BUS (11) ? PATH 2
BUF : $ID31 (31)
BUF : m2/xcombLoop2/x1 (17)
OR : m2/xicomb/x2 (18) ? ORIGIN

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Index
A rules 43
isolation cells
attribute adding 52
defined 19 dedicated 52
Liberty library 53
standard 53
B
Black boxes 50 L
LEF 48
C level shifter cells
adding 54
clock gating level shifting 10
definition of 9 command example 44
Common Power Format (CPF) 8 level-shifter
CPF 8 definition of 17
CPF files, reading 32 level-shifting
CPF low power cell insertion 31 boundaries 6
logical netlists
checking 41
D defined 7
definition of 38
default rules (EC) power domains
Default 18 defining 42
Default1 18 tool environment 42
Default2 18 LowPower Manager (EC) 23
Diagnosis Manager (EC) 28
dofile example
for EC session 30 M
drag-and-drop
from Mapping Manager to module-based verification 19
schematic 29 multi-voltage supplies
dynamic power 9 definition of 10

I N
icons, in main GUI netlists
Diagnosis Manager 28 logical 7
information box physical 7
display in Low Power Manager 24
isolation
advanced checks 38 P
boundaries 6
definition of 9, 17, 38 physical netlists

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checking 47 tag-based verification 19


defined 7
definition of 38
power domains, adding 49 V
tool environment 48
power control modules 39 validated results report 39
power domains voltage domain
analyzing 58 definition of 13
black box connections 50
definition of 11
power gating
definition of 11
power switches
adding 51
power switching
definition of 12
preferences for windows
LowPower Manager, set for 25

R
retention
adding 52
definition of 17, 38
implementation 6
rule-based checks 8
isolation rule 56
retention rule 56
switch rule 56
rules
user-added 20

S
schematic, open from
Mapping Manager 29
signal gating
definition of 12
starting the EC software 17
starting the Low Power software 37
state retention
definition of 12
structural checks 7, 8

T
tag
defined 18

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