Beruflich Dokumente
Kultur Dokumente
Contents
1
Introduction to Conformal Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Low Power Equivalency Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Low Power Extended Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logical and Physical Netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Structural Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Rule-Based Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Common Power Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Low Power Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Dynamic Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Level Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Multi-Voltage Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Signal Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
State Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Voltage Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2
Running Low Power Equivalency Checks . . . . . . . . . . . . . . . . . . . . . 15
Low Power Equivalency Checking Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Starting the Low Power (EC) Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Setting Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Running Low Power Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
State Retention Cell Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Isolation Cell and Level-Shifter Cell Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
LowPower Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LowPower Diagnosis Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Sample Dofile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CPF Low Power Cell Insertion Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reading the CPF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Performing Low Power Cell Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power Domain Schematic Color Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3
Running Low Power Extended Checks . . . . . . . . . . . . . . . . . . . . . . . . 35
Low Power Functional Checking Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Starting Conformal Low Power (Extended Checks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Specifying Low Power Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Validating Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power Control Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4
Running Logical Netlist Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Setting Options and Reading Logical Netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Design Verification Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Defining Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Defining Low Power Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Defining Isolation Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Isolation Cell Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Level Shifter Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Isolation and Level Shifter Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5
Running Physical Netlist Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Setting Options and Reading Physical Netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Reading in the LEF, Library and Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Handling Special Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Design Verification Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Defining Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Black Boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Defining Power Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Defining Power Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Defining Retention Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Defining Isolation Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Level Shifter Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Combination of Level Shifter and Isolation Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Defining Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Switch Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Analyzing Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6
Low Power Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Low Power Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
CPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Logical Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Functional Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Running Low Power Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Viewing Source Code and Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Functional Verification Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Isolation Functional Failure - True Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Isolation Functional Failure - X Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Power Domain Crossing Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Debugging Combinational Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
1
Introduction to Conformal Low Power
■ Overview on page 6
■ Low Power Equivalency Checking on page 6
■ Low Power Extended Checking on page 7
❑ Logical and Physical Netlists on page 7
❑ Structural Checking on page 7
❑ Rule-Based Checking on page 8
❑ Functional checking on page 8
■ Common Power Format on page 8
■ Low Power Concepts on page 9
❑ Clock Gating on page 9
❑ Dynamic Power on page 9
❑ Level Shifting on page 10
❑ Multi-Voltage Supplies on page 10
❑ Power Domain on page 11
❑ Power Gating on page 11
❑ Power Switching on page 12
❑ Signal Gating on page 12
❑ State Retention on page 12
❑ Voltage Domain on page 13
Overview
Designers increasingly expect longer battery life and higher performance. Due to increased
leakage, devices created using 90-nanometer and smaller process nodes consume as much
power when they are not in use as when they are being used. Designers can optimize for
leakage and dynamic power, which reduces energy use and lowers cooling and packaging
costs. Additional advanced low power methods offer further power savings, but significantly
complicate the verification process.
The Encounter® Conformal® Low Power software enables you to verify correct
implementation of these low power design techniques and validate your silicon using formal
techniques (versus simulation) early in the design process. It also decreases the risk of
missed bugs which are often missed, before a product goes out the door. Conformal Low
Power is the only solution in the industry providing full-chip low power functional verification.
Conformal Low Power accepts RTL/gate-level netlists with or without explicit power or ground
nets, and accepts user-defined power pins, power domains, power switches, level-shifter
cells, isolation cells, and state retention cells.
Conformal Low Power Equivalency Checking also supports low power cells insertion at the
Golden side by parsing the Common Power Format (CPF) file. This ensures that the design
and implementation tools maintain their logic integrity during optimization.
For more information, see Chapter 2, “Running Low Power Equivalency Checks”.
For more information, see Chapter 4, “Running Logical Netlist Checks” and Chapter 5,
“Running Physical Netlist Checks”.
Structural Checking
A structural check is anything we can do that only involves looking at the connectivity and
traversing through simple inverter and buffer gates. The structural check does not analyze
any logic to do the checks.
■ ISO7 checks flag missing isolation between switchable to non-switchable domains
■ Primitives with no power domain or multiple power domain (data or setup problem)
■ Nets with no drivers
■ Obvious redundant isolation (between two non-switchable domains)
■ Power ports not connected to a power domain
■ Power and ground domain shorts
■ Power and power domain shorts
■ Level shifter power ports connection errors (to wrong voltage)
■ Isolation cell power port connection (not to correct domain based on receiver)
■ Power switch cell port checking
Rule-Based Checking
You can specify how you expect isolation or retention to be implemented by defining valid
rules for checking isolation and retention cells.
Functional checking
The structural checks are automatic and done when analyzing the power domain. Analyze
power domain also performs the user-defined rule based checks if there are any enabled.
Once the structural checks have passed and all errors have been addressed, the next step is
functional validation when the software completes the checking.
■ Isolation is inserted properly as needed in all cases.
■ Isolation control is asserted during power down of the module being isolated
■ Retention cells are controlled properly with respect to clock, retention control signal, and
the control that powers down the domain where the retention cell exists.
The automation enabled through CPF infrastructure support will be the answer to the growing
power management design challenges faced by the industry. The introduction of CPF and its
support will bring productivity gains and improved quality of silicon to designers without
requiring any change to current legacy RTL.
For more information, see the following documents for Common Power Format (CPF):
■ Common Power Format Language Reference
You can open this from the Main Conformal window by choosing Help – CPF
Reference Manual.
■ Common Power Format User Guide
You can open this from the Main Conformal window by choosing Help – CPF User
Guide.
Clock Gating
Clock Gating is when logic that receives signals from clock gated latches and registers do not
switch. No dynamic power is consumed. Clock gating minimizes switching. In many designs,
data is loaded into registers infrequently, but the clock signal continues to switch at every
clock cycle often driving a large capacitive load. You can save a significant amount of power
by identifying when the registers are inactive and by disabling the clock during these periods.
Dynamic Power
Dynamic power is the power dissipated by an instantaneous short-circuit connection between
the voltage supply and the ground when the gate transitions, and the switching power
dissipated when charging or discharging internal and net capacitances.
Isolation
Isolation is a power management technique that prevents undriven outputs of switched OFF
blocks from causing electrical problems in active blocks. Active isolation provides driven value
to active logic, setting a logic cell input to a level that makes all other inputs a don’t care, i.e.
the voltage level of the other data inputs do not have any impact on the internal nets or the
outputs. Serious problems occur if in-active logic is not isolated.
Level Shifting
Level shifting is a technique to transport a signal from one voltage value to a higher or lower
voltage value. A level-shifter is a cell that is used as a boundary for signals that cross voltage
domains. A low to high crossing always requires a level shifter to prevent an abnormally high
power consumption. It is common to use level shifter which is a buffer powered by the higher
voltage for a high to low voltage domain crossing. Serious problems occur if signals go from
a low to high voltage domain without proper level shifting.
Multi-Voltage Supplies
Level shifters are required when a lower voltage signal drives a gate supplied by a higher
voltage. These cells are placed between a source and receiver powered by different voltages
to protect the receiver from too high or too low voltage. A level shifter requires both voltages
internally to function.
Low High
Level-
Voltage Voltage
Shifter
Domain Domain
When a higher voltage signal drives a gate supplied by a lower voltage, a level shifter might
not be used. When it is, it will use the lower voltage for the output stage and not use either
lower or higher voltage for the input stage.
High Lo
Level-
Voltage Voltage
Shifter
Domain Domain
Power Domain
A power domain is all circuits whose power source has the same voltage (same supply net).
All circuits which share the same power source, and if switchable, share the same power
enabling and disabling control. In the following illustration, all blocks are in separate power
domains:
Power Gating
Power gating is a technique to save leakage power, which switches a power domain’s
connection to a power source OFF, as shown in the following illustration:
Power Switching
A Power Switch is a PMOS device between a power pin and the power to a module. When
this transistor is turned off, the power domain of the supplied circuit is disabled. The power
output net of a power switch is known as a switched power domain. The module power is
turned OFF by turning OFF the PMOS device.
Signal Gating
Signal is a technique to reduce dynamic power consumption by stopping the switching of
signal value when they are not needed. Signal Gating is a common technique for RAM
address and data pins. This makes the inputs to the logic receiving the gated signal a
constant and eliminates dynamic power consumption.
State Retention
State retention is a power management technique that saves states before a block is powered
down. This is the process of saving an important state of a memory element such as a latch
or flip flop before the main power or ground of the module is switched off. The circuit which
saves the state will require non-interruptible power and ground to ensure state preservation.
In the following illustration, Sleep = Ret is asserted during low clock then VDD is switched
OFF. After the Wake - VDD is switched ON, Ret is de-asserted during low clock:
Voltage Domain
A voltage domain is all circuits whose power source has the same voltage (same supply
voltage value). In the following illustration, Blocks 1, 3, and 4 are in a 1.2v voltage domain,
while Block 2 is in a 1.0v voltage domain:
2
Running Low Power Equivalency Checks
Set Low Power Options See Setting Low Power Options on page 17
Mapping
For example, you can use the following command to enable low power checks for state
retention cells and isolation cells:
set lowpower option -retention -isolation
You can define the state retention mapping rules with the ADD RETENTION_MAPPING
command.
Default Rules
For Verilog, the tag is defined as a label in the always block. For VHDL, the tag is defined
as a label in the process block. The label can be a user-specified string or an empty string.
■ For Verilog, the following is an example of a label lp_sel assigned to a tag:
always @(posedge clk)
begin : lp_sel
q <= d;
end
In the synthesis LIBERTY library, the attributes are defined using the power_gating_cell,
is_isolation_cell, and is_level_shifter keywords. In the simulation library
(Verilog or VHDL), the attributes are defined using the ADD LOWPOWER CELLS command.
■ The following is an example of the power_gating_cell attribute defined in the
synthesis library:
cell (RET_DFF1) {
version : 1.0;
cell_leakage_power : 7E+03;
area : 15.10;
power_gating_cell : "LPRET_DFF1";
The following are examples of user-defined rules using the ADD RETENTION MAPPING
command:
The following command verifies that all registers with a tag label lp_sel* are implemented
with a state retention cell whose power_gating_cell attribute is LPRET_DFF1:
add retention mapping R0 -tag lp_sel* -attribute LPRET_DFF1
The following command verifies that all registers in module blockA are implemented with a
state retention cell whose power_gating_cell attribute is LPRET_DFF1:
add retention mapping R1 -module dma -attribute LPRET_DFF1
The following command verifies that all registers with instance name /U0/*/fifo_dma* are
implemented with a state retention cell whose power_gating_cell attribute is
LPRET_DFF2:
add retention mapping R2 -instance "/U0/*/fifo_dma*" -attribute LPRET_DFF2
If at any time a state retention mapping rule is added or deleted, the status of all the
sequential pairs resets to ’Unknown’. You will need to run the CHECK LOWPOWER CELLS
command to set the status of the sequential pairs.
The following is an example of a default summary report after running the following
commands:
> set lowpower option -retention
> check lowpower cells
================================================================================
Summary Golden Revised
DFF DLAT DFF DLAT
================================================================================
Passed 8808 62 8808 62
Failed 0 0 0 0
Not Checked 0 0 0 0
--------------------------------------------------------------------------------
Total 8808 62 8808 62
================================================================================
================================================================================
Rule Name Passed Failed
================================================================================
R1 8808 0
R2 62 0
--------------------------------------------------------------------------------
Total 8870 0
================================================================================
Passed Reports all the sequential pairs that passed the default rule or user rule.
In the example report, the 8808 Passed DFF and 62 Passed DLAT
sequential elements are consistent between the Golden and Revised
Designs. The DFF is covered by rule R1, and DLAT by R2.
Failed Reports all the sequential pairs that failed the default rule or user rule.
Not Checked Specifies that the low power check was not done or was interrupted. In
addition, this status applies to the sequential points that were not mapped.
These unmapped sequential points can belong to either the Golden or
Revised design, and can be reported using the REPORT UNMAPPED
POINTS -Retention command.
You can assign isolation or level-shifter cells either through a LIBERTY attribute, or with the
ADD LOWPOWER CELLS command. For example, in the LIBERTY file, you can use the
following attributes:
is_isolation_cell : true;
is_level_shifter : true;
If using the Verilog library, you can assign these cells with the following commands:
add lowpower cells LS_BMF -level_shifter
add lowpower cells ISO_AND -isolation
The technology mapping check ensures that for each low power cell (isolation cell or level-
shifter cell) in the Golden design, there is a corresponding low power cell in the Revised
design. To establish the correspondence, the Conformal software inserts key points (cut
gates) at the output of low power cells and performs name-based mapping. If it does not find
mapping for a low power cut gate, it sets the status of the corresponding low power cell to
Failed; otherwise, the status is set to Passed.
The equivalence check ensures that for the mapped low power cell pair, the logic feeding
them is equivalent in both the Golden and Revised designs. To perform equivalence checking,
the isolation and level-shifter cells will be added to compare points, and these will be proven
equivalent or non-equivalent during compare (when running the COMPARE command).
Note: The CHECK LOWPOWER CELLS command performs only the technology mapping
check for isolation cells and level-shifter cells. The EC checking results are received after
running the COMPARE command.
After performing the low power check, a status summary is printed for all low power cells. The
following is an example of a default summary report after running the following commands:
> set lowpower options -isolation -level_shifter_cells
> check lowpower cells
================================================================================
Isolation Cells
================================================================================
Status Golden Revised
--------------------------------------------------------------------------------
Passed 64 64
Failed 0 0
Not Checked 0 0
--------------------------------------------------------------------------------
Total 64 64
================================================================================
Level Shifters
================================================================================
Status Golden Revised
--------------------------------------------------------------------------------
Passed 8 8
Failed 0 0
Not Checked 0 0
--------------------------------------------------------------------------------
Total 8 8
================================================================================
Passed The 64 Passed isolation cells and 8 Passed level-shifter cells are
consistent between the Golden and Revised Designs.
Failed No (zero) isolation or level-shifter cell failed the technology mapping
check.
Not Checked No (zero) check was not completed or interrupted.
LowPower Manager
Use the LowPower Manager to display unmapped and checked points, check key points, and
report the status of each checked point (Pass | Fail | Not-Checked).
➤ Choose Tools – LowPower Manager, or click on the LowPower Manager icon.
The LowPower Manager includes two columns. The left column contains Golden design
information and the right column contains Revised design information. Each column is
divided into two sections. The top section is the Unmapped points portion and the bottom
section is the LowPower check portion.
By default, when you rest the cursor over a point, Conformal displays an information box that
identifies the point by name and lists pertinent details about it.
Passed — The sequential pair passed the system rule or any of the
user added rules.
Failed — The sequential pair failed the system rule or any of the user
added rules.
Not Checked— The the low power check was not done or was
interrupted.
See Isolation Cell and Level-Shifter Cell Checking on page 21 for more information.
Setting Preferences
Click the Preferences pull-down menu on the menu bar to specify the following viewing
preferences:
Click the Refresh button to return the displayed gates to their original numerical order.
Note: When you change Pass/Fail Icon preferences, Conformal prompts you to refresh the
window.
Use the Find Check Points form to display points that match a specified string. Conformal
bases the filter on instance names.
Note: If you click the Refresh button on the menu bar of the LowPower Manager, the original
unfiltered display returns.
Do the following in the LowPower Cell sections to locate points that contain the
specified search string.
1. Click the Find icon button located in the upper right corner of the appropriate section, or
press Ctrl-f. The section-specific Find form opens (for example, Find: Checked
Points).
2. Type any string or partial string of a key point name in the Find field.
3. Click the Find Forward or Find Backward check box to specify the direction of the
search.
4. Click the Case Sensitive check box, if applicable.
5. Click the Find button to search for the name.
6. Repeat step 5 to find the next point that fulfills the search criteria.
In the LowPower Cell section, use the following procedure to display specified
classes of points.
1. Click the Class icon located in the upper right corner of the LowPower Cell section.
2. Choose one or more of the classes.
All displays all of the categories (Pass, Fail, and Not-Checked). Disable All deselects
all of the categories.
To run the technology mapping check or the equivalence check, or both, depending on the
low power cell type, click on the green check mark to the right of the Class button.
For more information on low power checking, see Running Low Power Checks on page 17.
Golden side could be Module, Instance, Tag or Power Gating Cell Attribute and the
Revised side could be a Tag or Power Gating Cell Attribute.
■ Rule Name—Specifies all the rules for the state retention cell.
■ Instance, Module, or Tag—Specifies the instance, module, or tag name of the rule.
■ Attribute—Specifies the attribute of the rule.
The text color indicates the status of state retention cells. Green indicates that the
sequential pair passed the system rule or any of the user added rules. Red indicates that
the sequential pair failed the system rule or any of the user added rules.
Use the following procedure to select a point in the LowPower Cell section of the LowPower
Manager and view a schematic of the selected point.
1. Click a point in either the Golden or Revised column in the LowPower Cell section.
2. Right-click and choose Schematics from the pop-up menu.
The schematic viewer opens and highlights the selected point.
From the LowPower Diagnosis Manager, you can open the schematic by clicking the
Schematic button from the Menu Bar.
Use the following procedure in the LowPower Cell section of the LowPower Manager as a
convenient way to locate and highlight a specified point in the schematic. This feature also
works in the reverse drag-and-drop order (drag from the Flatten Schematics window to a
section in the LowPower Diagnosis Manager).
Tip
Begin this procedure with the schematic viewer open and the Mapping Manager
active.
1. Click and hold the middle mouse button over a point in the LowPower Cell section.
2. Drag the point from the LowPower Diagnosis Manager to the Flatten Schematic window.
When you click with the middle button, the LowPower Diagnosis Manager displays the
name of the point you clicked in an ivory text box. As you move the point to the new
window, the background of the text box changes to black if the object is in a window
where you can drop items.
3. Release the middle mouse button, and the point is highlighted in the Flatten Schematic.
Sample Dofile
The following is an example of a Conformal dofile that includes the Conformal Low Power
Equivalency Checking flow.
// Read ASIC vendor library
read library ../library/lib/LP.lib -liberty -both
// Read RTL and gated-level netlist
read design ./rtl/top.v -golden
read design ./netlist/top_final.v -revised
// Report design information
report design data
report black box
// Enable isolation check, level-shifter check, and state retention check
// This requires Conformal LP license
set lowpower option -auto
// Define design constraints
add pin constraint 0 SCAN_EN -both
add pin constraint 0 RET -both
// Check all registers of the module "blockA" with LP attribute
// LPRET_DFF1 implementation
add retention mapping R1 -module blockA -attribute LPRET_DFF1
set system mode lec
// Run lowpower checks
check lowpower cells
// Run flatten EC comparison
add compare point -all
compare
usage
Read the CPF File See Reading the CPF File on page 32
Compare
After parsing the CPF files, you can perform low power cell insertion on the Golden design by
running the COMMIT CPF -insert command. You can insert the following low power cell
types:
■ level shifter cells
■ retention cells
■ isolation cells
■ combined level shifter and isolation cells (combo cells)
Cadence recommends specifying the design constraints after reading in and committing the
CPF files because some design constraints specified on power boundary crossing nets could
be lost after the low power cells have been inserted.
During mapping, the state retention cell checking will be done automatically. The state
retention mapping rules are derived from the following CPF commands in the CPF files:
■ define_state_retention_cell
■ create_state_retention_rule
You can use the REPORT LOWPOWER DATA command to report the status of state retention
cell checking between the Golden and Revised designs.
After the low power cells (which were specified in the CPF files), are inserted in the Golden
design, the subsequent COMPARE command will check the functional equivalency between
the Golden and Revised designs.
Note: Level shifter and isolation cell checking are disabled in the CPF low power cell insertion
flow.
The following shows an example of a dofile that inserts low power cells after reading in two
CPF files named rtl.cpf and my_library.cpf:
read library -liberty my_library.lib -both
read design rtl.v -verilog -golden
read cpf rtl.cpf my_library.cpf
commit cpf -insert
read design gate.v -verilog -revised
add compare point -all
compare
In the following figure, instances counter_inst and state_inst are colored blue,
indicating they belong to same power domain. The low power cells inserted by the Conformal
Low Power software, pd_inst_2 and pd_inst_3, have their own color coding.
pd_inst_2
pd_control2
state_inst
state
counter_inst pd_inst_3
counter pd_control1
If you move the mouse pointer over counter_inst, it will display the domain name, voltage
that it operates on, and if it is a switchable domain or an always-on domain.
For example, the following figure shows that its domain name is PD1, and its voltage is 0.8
and is an always-on domain:
counter_inst
counter
instance: counter_inst
module definition: counter
instances: 10
nets: 35
Power Domain: PD1
Voltage: 0.8 (always on)
3
Running Low Power Extended Checks
Figure 3-1 shows the Setup mode part of the Low Power flow.
Setup Mode
Specify design
Constraints
Define clock
initialization
sequence
Verify Mode
Verify Mode
Design No
Debug
Passed?
Yes
DONE
You can specify the need for on-to-off isolation. In logical netlist, anytime there is an
isolation rule specified between two domains, the isolation cells between them will not
be flagged as redundant if they can be on-to-off (that is, on-to-off isolation is assumed to
be needed between them). Use the following command:
set lowpower option -on_to_off_iso
In addition, you can specify the global limit on the number of isolation control pins driven
by the same signal. Use the following command:
set lowpower option -isolation_limit <limit>
■ State Retention Cells—used to specify the global limit on the number of retention control
pins driven by the same signal. Use the following command:
set lowpower option -retention_limit <limit>
With the -ISOlation option, you can report only isolation cells, including isolation assertion
checks.
With the -CROssing option, you can report only crossing failures. You can include all or
specific crossing from the specified power domain(s), which are the starting (source) and he
ending (destination) power domain(s) of the crossing failures.
With the -RETention option, you can report only state retention cells, including the clock
value functional check.
For the complete syntax and command description, see REPORT VALIDATED DATA in the
Encounter Conformal Extended Checks Reference Manual.
When the design does not include a power control module, and the power control are input
ports, you must express the relationships of these inputs with a
$constraint(expression) statement in the netlist or as an append to module in a
separate file. For example, if poweron1 and poweron2 relationships are 00, 01, and 11, this
means that 10 does not occur and you would use the following expression:
$constraint(!(poweron1&&!poweron2);
Based on this expression, Low Power will check the validity of the isolation between the
domains controlled by these ports, and find any errors where the isolation fails under this
constraint.
Note: Open Verification Library (OVL) can also be used as constraints to express such
relationships.
4
Running Logical Netlist Checks
The Conformal Low Power logical netlist checking works on netlists without power and ground
nets. It checks level shifters locations and isolation cell types and locations.
Set Options
Add Rules
Functional Setup
Reports
Checks and Debug
and
Logs
Then you will need to read in the libraries and the designs. For example:
read library lib1.lib -liberty
read library lib2.v -verilog -append
read design des1.vhd -vhd -noelaborate
read design des2.v -verilog
Depending on the voltage crossing check requirement, there are three options you can use
for level-shifter cell checking:
-ignore_high_to_low [<tolerance>]
-ignore_low_to_high [<tolerance>]
-level_shifter_check connect
The following shows the command entry for the example design information:
add power domain TopD -voltage 1.0 –module TOP
add power association –pin In* –domain TopD
add power domain LocD -voltage 1.2 -instance X1
add power association –pin Out* -virtual v15 1.5
You can identify isolation and level shifter cells by writing a script to read the Liberty file and
identify cells with the is_isolation_cell or is_level_shifter attribute.
Note: The Conformal Low Power Verify mode does not identify these cells automatically like
the Equivalency Checking application does.
X1 is a 1.0v domain
X2 is a 1.2v domain
X3 is a 1.2v domain
5
Running Physical Netlist Checks
The Conformal Low Power physical netlist checking works on netlists with power and ground
nets. It completes checks for level shifter, isolation, and state retention cells. Physical netlist
checks include power gating and power connectivity.
Set Options
LEF,
Library Read Netlists
and
Design
Define Domains
Add Rules
Analyze Power
Domain
Functional Setup
Reports
Checks and Debug
and
Logs
Then you will need to read in the libraries and the designs. The data requirements for the
libraries are as follows:
■ Verilog netlist with full power connectivity
This includes top-level power pins, power pins at every level of the hierarchy, and power
pins for standard cells and macro blocks.
■ Accurate power switch models
These can be modeled as a tri-state buffer. For example:
bufif1 (VDD_OUT, VDD_IN, ENable)
Depending on the voltage crossing check requirement, there are three options you can use
for level-shifter cell checking:
-ignore_high_to_low [<tolerance>]
-ignore_low_to_high [<tolerance>]
-level_shifter_check connect
You can define power domains and their power connectivity with the following ADD POWER
commands:
■ Define power domain for power pin groups:
add power pin <domain> <primary_pin> -voltage <voltage>
[-nonstandby | -standby <expr>]
■ Associate power domains for top level data ports and black box cell data ports:
add power assoc <cell_name> -power <pwr_pin> <pin* ...>
Black Boxes
Black boxes can connect to multiple power domains. You can define power domain with
default always on power pin to have the tool check that the net connected to this pin is always
on. Then associate the data and power pins to the power domain.
Using this example, you would check that the net connected to the always_on pin is always
on:
add power domain vbb -voltage <V> -module IP1 -power V2
Use the ADD POWER SWITCH command to define power switches. For example:
add power switch PSW VDD VSW -standby Ei
add power switch PSW VDD VSW -standby Ei -control_power VDC -max_enable_bias 0.4
The following shows an example of defining dedicated low power isolation cells:
add isolation cell Iso_An1 -isopin IsoB -vdd VDD -vddiso VDDC
The Liberty library usually contains some information on isolation cells. You can use the
following script to help define isolation cells:
cat <liberty_directory>/*.lib | awk ’{ \
if ($1 == "cell") cell = $3; \
if ($1 == "pin") pin = $3; \
if ($1 == "isolation_pin") { \
printf("cell=%s pin=%s\n",cell,pin);} \
}’
add level shifter lshift2 <vin> <vout> -vdd_out VDD -data_in A -data_out Y
Defining Rules
After adding the power domains, you can specify how you expect isolation or retention to be
implemented by defining valid rules for checking isolation and retention cells, using the ADD
ISOLATION RULE and ADD RETENTION RULE commands.
For example, if you define a retention rule with the following command:
add retention rule rule1 -retention a1/Y -instance i0 i1
Y
a0
i0 i1 i2
a1
the Conformal software will issue a RETRULE1.1 message for retention cell instance i1
because its retention control RET is not connected to a1/Y.
Switch Rules
A switch rule specifies the enabling condition of the switches driving the specified domain or
the output power or ground net. You can use the ADD SWITCH RULE command to define a
switch rule to be verified for the specified output domain.
In the following example, there is one external power net POWER_IN that drives a switched
power net POWER_SWITCHED through a set of parallel switches. The switched power net
POWER_SWITCHED powers the domain D. The switches have a single enable pin EN, that
should be driven by the pin ctrl/OUT.
For this example, the switch rule can be specified in any of the following ways:
add switch rule r0 -DOMain D -ENAble ctrl/OUT
add switch rule r0 -DOMain D -POWER_IN POWER_IN -ENAble ctrl/OUT
add switch rule r0 -POWER_OUT POWER_OUT -POWER_IN POWER_IN -ENAble ctrl/OUT
OUT EN
IN OUT
EN
TO
IN OUT Domain D
EN
In the following example, the switch has multiple enable pins. So, rules should specify the
hierarchical instance pin that should control each of these pins, as follows:
add switch rule r1 -domain D -ENABLE_pin EN1_IN -SWITCH_PIN EN1
add switch rule r2 -domain D -ENABLE_pin EN2_IN -SWITCH_PIN EN2
PIN IN
POWER_OUT
EN1_IN EN1 Domain D
EN2_IN EN2
The following is a more complicated scenario where multiple power nets drive the same
output domain through multiple parallel switches with multiple switch enable pins. The output
power net POWER_OUT is driven by two switches sw1 and sw2. The input powers of sw1
and sw2 come from external power net PIN1 and PIN2 respectively.
In this case, four rules should be specified, and the input power net must be specified for each
rule.
add switch rule r11 -power_out POWER_OUT -enable EN1_1 -switch_pin EN1 \
-power_in PIN1
// for EN1 of sw1
add switch rule r12 -power_out POWER_OUT -enable EN2_1 -switch_pin EN2 \
-power_in PIN1
// for EN2 of sw1
add switch rule r21 -power_out POWER_OUT -enable EN1_1 -switch_pin EN1 \
-power_in PIN2 +
// for EN1 of sw2
add switch rule r22 -power_out POWER_OUT -enable EN2_1 -switch_pin EN2 \
-power_in PIN2
// for EN2 of sw2.
PIN1 IN
POWER_OUT
EN1_IN EN1SW1
EN2_IN EN2
Domain D
PIN2 IN
EN1_IN EN1SW2
EN2_IN EN2
When bringing up the schematic view, the power domains are color coded. The colors
represent different switch domains and voltage domains. Blue (by default) represents the
continuous power domain.
6
Low Power Diagnosis
This will bring up the Low Power Manager. In this form there are the following three tabs:
■ CPF
■ Logical Check
■ Functional Check
For each category, the tab displays a red circle or a green circle to
indicate whether messages were generated in that category. If you
prefer, Conformal displays check marks (red X or green check).
CPF
The following shows an example of the Low Power Manager’s CPF (Common Power Format)
page with the CPF Power Domain tab selected:
Note: The CPF tab is only active after the CPF files have been read.
By default, the Low Power Manager displays only the CPF quality checks with violations. To
view a complete list of the various rules as well as detailed rule violation information, click
Option and choose View – All.
For the description of a rule message, click on the message to display the description at the
bottom of the Low Power Manager. For more information on a message, see the “Common
Power Format Rule Checks” chapter in the Encounter Conformal Low Power
Reference Guide, or type ‘help <rule>’ in the command line.
Logical Check
The following shows an example of the Low Power Manager’s Logical Check page with the
Power Domain tab selected:
By default, the Low Power Manager displays only the rule checks with violations. To view a
complete list of the various rules as well as detailed rule violation information, click Option
and choose View – All.
■ Transistor Usage—reports any of the logical (or structural) check violations for pre-
defined rules at the transistor level.
■ Structural—lists all of the checks for structural low power design errors.
For each cell, you can click the cell row to highlight the cell name and description, then click
the right mouse button to bring up the pull-down menu where you can select from the
following options:
■ Severity—Changes the message severity level. You can choose Warning, Error,
Ignore, or Note.
■ Report—displays the status of the predefined rules. You can select on of the following:
❑ Summary—displays a complete list of the predefined rule messages that
Conformal Equivalence Checker has generated for your design.
❑ Verbose—expands the display to include the messages and full path(s) of the low
power cell(s).
Functional Check
The following shows an example of the Low Power Manager’s Functional Check page with
the Isolation Cell tab selected:
To open either the Source Code or Schematic viewer, use the following steps:
1. Click the + symbol preceding the cell to fully expand the entry.
2. Click an occurrence to select and highlight it.
3. Right-click and choose Source Code or Schematics from the pop-up menu.
Cause of failure:
At time 0 power of input pin ’A’ was off
but isolation condition was not asserted
Counter example:
Time Unit 0:
1’b0 => 3: count
1’b0 => 3: count
Time Unit 2:
1’b0 => 3: count
In the output example, the isolation control was not asserted when the input signal
driving pin A of isolation cell was turned off. Hence, there is a failure in the isolation
function. This is due to one of the following reasons:
❑ Bad isolation logic in the power control circuitry
❑ The power control might generate the isolation condition properly, but the signal
might be inverted, or gated before connecting to the isolation enable pin of the
isolation cell (ECO is one part of the flow that could cause this).
Counter example:
1’b0 => 3: count
X Assignments
1’b0 => 12: ctrlr/count_reg[0]
1’b0 => 13: ctrlr/count_reg[1]
1’b1 => 14: ctrlr/count_reg[2]
The log shows that there are some X assignments on some of the flops in this path. This is
due to bad initialization in the init.seq or the VCD file. If you see such a log, the first thing
you should do is inspect the “reset control” in the init sequence file. The following depicts one
such error:
0 0 -BBOX
0 1 VDD
0 0 VSS
//0 0 RST_N
2000
The RST_N line of init seq file is commented, which indicates that the design will not be RESET
properly before the verification takes place. This causes X assignments. One of the primary
reasons the RESET could be missed is because of the difficulty to trace this signal all the way
down to the power control logic. The signal that is intended to be used by the RTL might be
floating due to changes that happened during the place and route flow. It is important to check
this or the results of functional verification will not be accurate.
Diagnosis information
This will show the diagnosis information for the selected instance on the Conformal verify
window.
Counter example:
Time Unit 0:
1’b0 => 3: count
1’b0 => 5: din1
1’b1 => 4: din2
1’b0 => 6: sleep
X Assignments
1’b0 => 80: $LOOP1
1’b0 => 18: domain1/pd1_flop/Q_reg/Q
Time Unit 2:
1’b1 => 3: count
The log shows that the problem cell is an OR gate. The second input of this OR gate is driven
by a switched power supply. The log also shows that the input 1 of this OR gate is driven by
an instance topAND/x1, whose value is a 1’b0. The problem here is, we need a 1’b1 in
order to block the floating signal from propagating through the OR gate. Hence, there is no
proper domain isolation in this case.
4. Select any of the violations (for example, CLP_STRC1.1), and expand the list to select
one of the violating instances.
Right click on the instance name and choose Schematic – Show Module Schematic to
open the schematic as shown in the following figure.
From the schematic, it is apparent that the ISO_OR cell is involved in a combinational loop,
and because this is a small path, you can also traverse the path manually to see the
combinational loop. But in a real design, tracing this path is not as easy.
When you run this command, the software gives a complete path of the combinational loop.
In this example, there are two paths to the loop, and both are listed here:
Strong combinational loop from m2/xicomb/x2 (18):
OR : m2/xicomb/x2 (18) ? ORIGIN
BUS : m2/xicomb/a1$BUS (10)
BUF : $ID32 (32)
BUF : m2/xb1/x1 (19) ? PATH 1
BUS : m2/xcombLoop/X$BUS (11) ? PATH 2
BUF : $ID31 (31)
BUF : m2/xcombLoop2/x1 (17)
OR : m2/xicomb/x2 (18) ? ORIGIN
Index
A rules 43
isolation cells
attribute adding 52
defined 19 dedicated 52
Liberty library 53
standard 53
B
Black boxes 50 L
LEF 48
C level shifter cells
adding 54
clock gating level shifting 10
definition of 9 command example 44
Common Power Format (CPF) 8 level-shifter
CPF 8 definition of 17
CPF files, reading 32 level-shifting
CPF low power cell insertion 31 boundaries 6
logical netlists
checking 41
D defined 7
definition of 38
default rules (EC) power domains
Default 18 defining 42
Default1 18 tool environment 42
Default2 18 LowPower Manager (EC) 23
Diagnosis Manager (EC) 28
dofile example
for EC session 30 M
drag-and-drop
from Mapping Manager to module-based verification 19
schematic 29 multi-voltage supplies
dynamic power 9 definition of 10
I N
icons, in main GUI netlists
Diagnosis Manager 28 logical 7
information box physical 7
display in Low Power Manager 24
isolation
advanced checks 38 P
boundaries 6
definition of 9, 17, 38 physical netlists
R
retention
adding 52
definition of 17, 38
implementation 6
rule-based checks 8
isolation rule 56
retention rule 56
switch rule 56
rules
user-added 20
S
schematic, open from
Mapping Manager 29
signal gating
definition of 12
starting the EC software 17
starting the Low Power software 37
state retention
definition of 12
structural checks 7, 8
T
tag
defined 18