ISSCC 2005 / SESSION 4 / TD: MIXED-DOMAIN SYSTEMS / 4.
4.4 A VLSI Analog Computer/Math
Co-Processor for a Digital
Computer
Glenn E. R. Cowan, Robert C. Melville, Yannis P. Tsividis
Columbia University, New York, NY
Analog computers of the 1960s were physically large, tedious to
program, and required significant user expertise. However, once
programmed, they rapidly solved a variety of mathematical prob-
lems, notably differential equations, without time-domain dis-
cretization artifacts [1]. Analog computers were superseded by
digital ones long ago; the technical community has hardly con-
sidered the advantages that modern VLSI techniques could
impart to analog computers. Reported in this paper are the
results of an attempt to investigate whether analog computers
could be revived in a modern VLSI context, with significant
advantages as complements to digital computers. A single-chip
VLSI analog computer (AC), capable of handling large-order
problems (e.g., nonlinear differential equations of up to 80th order)
is presented. This AC is meant to operate in a symbiotic environ-
ment with a digital computer (Fig. 4.4.1), complementing the lat-
ter and acting as a co-processor to it. The combination has sever-
al features: (a) tight coupling to the digital computer through an
A/D-D/A interface which facilitates a pre-computation calibration
process, (b) digital programmability through a standard on-
screen Simulink interface, (c) real-time simulations and real-time
observation of the effects of mathematical parameter changes, (d)
fast approximate solutions to difficult mathematical problems,
sometimes much faster than is possible with a digital computer,
and with guaranteed convergence to physical solutions, (e) capa-
bility of passing an approximate solution as a first guess to a dig-
ital computer, thus speeding up a numerical solution, and (f)
interfacing to measurement instruments.
Analog circuits can solve ordinary differential equations (ODEs)
of the form x = f (x, u, t) where x is a state-variable vector of
length n, u is an input vector of length m and f is a length n vec-
tor of possibly nonlinear functions. To solve the ODE, an AC
needs n integrators, m inputs, and sufficient circuitry to imple-
ment f or an adequate approximation of it. Several techniques for
converting partial differential equations (PDEs) to ODEs of the
above form exist, e.g., method of lines.
The reported IC contains 416 functional blocks as detailed in Fig.
4.4.6 and a large number of signal-routing switches. Variables are
represented by differential currents (i.e., the circuits are current-
in/current-out) and hence signals are added by connecting multi-
ple signal routes together. Cross-coupling of a differential signal
allows it to be inverted or subtracted from another signal. The
chip contains 160 blocks that allow a signal to be fanned out to at
most three other blocks. Extensive use of weak inversion circuits
keeps power dissipation low despite the large amount of circuitry
(the chip area is 1cm2). High-speed computation is still possible
with the ensuing low currents, due to the inherent speed advan-
tages of analog computation.
The circuits are divided into a 4×4 array of identical macroblocks
(MBs) (Fig. 4.4.7). Each block’s input is connected to a wire run-
ning horizontally (Fig. 4.4.2) and each block’s output is connected
to a wire running vertically. These wires extend outside of the MB
to allow for connection between blocks in other MBs. For simplic-
ity each block is shown with one input and one output. Each wire
represents a pair of wires, carrying a differential current. There
is an array of CMOS pass-transistor switches and SRAM that
holds their states wherever two groups of wires cross. In Fig.
82 • 2005 IEEE International Solid-State Circuits Conference
4.4.2, the solid, bold line shows how the output of block X is rout-
ed to the input of block Y within the same MB. To route a block’s
output to the input of a block not in the same MB, shared, global
wires are used. The dotted, bold line in Fig. 4.2.2 shows how the
output of a block in MB W is routed to the input of a block in MB
Z.
Digital programmability has been incorporated into most blocks.
For example, the programmable mirrors ( labeled A:B and B:A in
Fig. 4.4.3) allow for variable input and output bias/signal ranges,
while maintaining a fixed bias of 1µA to the core. Composite
devices ARRAY1, ARRAY2, and ARRAY3 generate the different
bias currents, while remaining in a nearly constant level of inver-
sion. The core contains two differential to single-ended log-
domain integrators similar to [2]. With M1 and M2 off, the volt-
age necessary to cancel the integrator’s offsets (input and output)
can be sampled through M3 and M4 and stored on CHold1 and
CHold2. The integrator also features common-mode feedback, a
DAC for tuning ITUNE, and a memory block for storing range set-
tings and the DAC’s input.
The 100mm2 AC chip dissipates 300mW. Performance is summa-
rized in Figure 4.4.6. The rest of the paper presents representa-
tive results of solutions using the AC. Figure 4.4.4 shows results
for a one-dimensional heat equation solved using the method of
lines on the AC. The spatial variable, x, was discretized into 16
points, requiring 14 integrators; each end is defined by a bound-
ary condition. For a one degree step at one end, the maximum dif-
ference between the AC’s solution and a numerical solution com-
puted using MATLAB was 0.025 degrees, with the former taking
1.2ms. The same approach was extended to the solution of a 45th
order two-dimensional heat equation; the rms steady-state error
is 2.6%. Such errors may be reduced by improving the calibration
techniques.
A second example is a transient noise simulation. Such simula-
tions take a long time on a digital computer because including
wideband noise necessitates small time steps and the generation
of meaningful statistics can necessitate a long simulation inter-
val. Figure 4.4.5 shows results for a simple example. There is a
good agreement between the AC and MATLAB simulations while
MATLAB simulation takes 96s (running on a Sun Blade 1000)
whereas the AC takes 4s - a factor of 24 times faster. This simu-
lation used only one MB, allowing for 15 other simulations to take
place simultaneously and a potential speed-up of nearly 400.
As a third example the AC’s periodic solution of Duffing’s equa-
tion has been used as the initial guess to reduce the number of
iterations of a Newton-Raphson based steady-state ODE solver
(based on algorithms in [3]) from 37 to 5 and its computation time
from 12.5s to 0.76s.
The work in progress, in consultation with applied mathemati-
cians and numerical analysts, is to apply the AC to the study of
problems such as nonlinear stochastic PDEs and real-time con-
trol of chemical reactions, for which existing numerical methods
are problematic.
Acknowledgments:
The authors thank Y. Kevrekidis, D. Keyes, B. Ogunnaike, S. de la Veaux,
and M. Weinstein for their valuable suggestions, MOSIS for fabrication
and packaging, and NSERC for graduate student funding.
References:
[1] G.A. Korn and T.M. Korn, Electronic Analog and Hybrid Computers,
McGraw-Hill Book Company, 1964.
[2]M. Punzenberger and C. Enz, “A New 1.2V BiCMOS Log-Domain
Integrator for Companding Current-Mode Filters,” Proc. ISCAS, pp. 125-
128, May, 1996.
[3] K. Kundert, J. White, and A. Sangiovanni-Vincentelli, Steady-State
Methods for Simulating Analog and Microwave Circuits, Kluwer, 1990.
0-7803-8904-2/05/$20.00 ©2005 IEEE.
 ISSCC 2005 / February 7, 2005 / Salon 8 / 3:15 PM

Matlab & Simulink

Data
acquisition
4
card ( in a PC )
Analog computer /
Other
math co processor
Test equipment
computational ( Optional, for real
programs
time simulation and
( accelerated by
observation )
analog computer’s
solution )

Figure 4.4.1: Analog computation environment. Figure 4.4.2: Block diagram of the analog computer.
iin1- + 1uA

iin2- + 1uA

icore- + 1uA

d( iout+ - iout-) = KITUNE( iin+ - iin- )

dt
iin1+ = iin2+ = B/A*(iin+)
iout+ = A/B*(i +)
ITUNE core

10-bit Mirror Image T(1,t)

Integrator Core
DAC (Offset cancellation and 1
bias circuits duplicated above)
ITUNE x=1 t
iin1+ + 1uA

iin2+ + 1uA

icore+ + 1uA

iout+ For 100nA bias

Vdd
iin+ For 1uA bias T(0,t)
A:B B:A x
IBIAS
x=0 t
M1 M2 M4
M3 2
w T ( x, t )
D T ( x, t )
CHold2 w2x
CHold1
ARRAY1 ARRAY2 V 1 V2 where T is the
For 20uA bias temperature along the
ARRAY3 rod and D is 0.0178
Nine transistors connected in
Offset cancellation one of three ways.

Figure 4.4.3: Integrator core, input and output circuitry. Figure 4.4.4: Results for a 1-D heat equation.

Supply voltage 2.5 V core, 3.3 V digital I/O

Results for: Technology TSMC025 ( CM025, one poly, five metal )
Statistics for the solution of x
Die area 100mm2
dx df ( x) 1.5

 n(t ) . . PDF of x, Simulink

NoisePDF
PDFof x, Analog Computer Number of integrators 80
dt dx .
Scaled noise PDF, f(x), PDFs of x

_ _ Noise PDF
f(x) f(x) Number of VGAs / two-input multipliers 80
where n(t) is noise with a PDF of x, Matlab
MATLAB
Number of fanout blocks 160
probability density 1 PDF of x, AC
Number of programmable nonlinear blocks 64 or 32 (1)
function (PDF) shown on Number of logarithmic blocks 16
the right and f(x)= 0.19x4 Number of exponential blocks 16
+ 0.014x3 -0.25x2 (also
Total number of functional blocks 416
shown on the right). 0.5

Number of analog inputs 64

Number of analog outputs 64

The solution for x was Integrator time constant range 5 - 60Ps

0
computed using Matlab
MATLAB Fanout blocks RMS deviation from unity gain 0.2%
and the AC and is VGA linearity for unity gain and a gain of 2.5(2) 0.044%, 0.11%
summarized by PDFs, Power dissipation, with all circuits active 300mW
shown on the right. −0.5
−2 −1.5 −1 −0.5 0 0.5 1 1.5 2 (1) The 64 programmable nonlinear blocks can each implement sign, absolute value or
saturation. When used in pairs, they can implement minimum, maximum, greater than,
x less than, gate, track and hold, or sample and hold.
(2) RMS nonlinearity over +/- 60% of the input range across all VGAs.

Figure 4.4.5: Simple differential equation with noise. Figure 4.4.6: Performance summary.
Continued on Page 586

DIGEST OF TECHNICAL PAPERS • 83

 ISSCC 2005 PAPER CONTINUATIONS

Figure 4.4.7: Chip micrograph.

586 • 2005 IEEE International Solid-State Circuits Conference 0-7803-8904-2/05/$20.00 ©2005 IEEE.