Beruflich Dokumente
Kultur Dokumente
09657-001
Built-in adaptive debouncer GND
Wide operating temperature: −40°C to +125°C Figure 1.
Thin, 2 mm × 2 mm × 0.55 mm 8-lead LFCSP package
APPLICATIONS
Table 1. NVM ±8% Resistance Tolerance Family
Mechanical potentiometer replacement
Portable electronics level adjustment Model Resistance (kΩ) Position Interface
Audio volume control AD5110 10, 80 128 I2 C
Low resolution DAC AD5111 10, 80 128 Up/down
LCD panel brightness and contrast control AD5112 5, 10, 80 64 I2 C
Programmable voltage to current conversion AD5113 5, 10, 80 64 Up/down
Programmable filters, delays, time constants AD5116 5, 10, 80 64 Push button
Feedback resistor programmable power supply AD5114 10, 80 32 I2 C
Sensor calibration AD5115 10, 80 32 Up/down
GENERAL DESCRIPTION
The AD5116 provides a nonvolatile digital potentiometer due to contact bounce (commonly found in mechanical
solution for 64-position adjustment applications, offering switches). The debouncer is adaptive, accommodating a
guaranteed low resistor tolerance errors of ±8% and up to variety of push buttons.
±6 mA current density in the A, B, and W pins. The low resistor The AD5116 can automatically save the last wiper position into
tolerance, low nominal temperature coefficient, and high EEPROM, making it suitable for applications that require a
bandwidth simplify open-loop applications, as well as tolerance power-up in the last wiper position, for example, audio
matching applications. equipment.
The new low A-W and B-W resistance feature minimizes The AD5116 is available in a 2 mm × 2 mm 8-lead LFCSP
the wiper resistance in the extremes of the resistor array to package. The part is guaranteed to operate over the extended
typically 45 Ω. industrial temperature range of −40°C to +125°C.
A simple push button interface allows manual control with
just two external push button switches. The AD5116 is designed
with a built-in adaptive debouncer that ignores invalid bounces
DOCUMENTATION DISCUSSIONS
Application Notes View all AD5116 EngineerZone Discussions.
• AN-1291: Digital Potentiometers: Frequently Asked
Questions SAMPLE AND BUY
Data Sheet Visit the product page to see pricing options.
• AD5116: Single-Channel, 64-Position, Push Button, ±8%
Resistor Tolerance, Nonvolatile Digital Potentiometer
TECHNICAL SUPPORT
Data Sheet
Submit a technical question or find your regional support
User Guides
number.
• UG-324: Evaluation Board for the AD5116 Digital
Potentiometer
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
TOOLS AND SIMULATIONS
• AD5116 IBIS Model
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AD5116 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Test Circuits..................................................................................... 12
Applications ....................................................................................... 1 Theory of Operation ...................................................................... 13
Functional Block Diagram .............................................................. 1 RDAC Register............................................................................ 13
General Description ......................................................................... 1 EEPROM ..................................................................................... 13
Revision History ............................................................................... 2 Automatic Save Enable .............................................................. 13
Specifications..................................................................................... 3 End Scale Resistance Indicator ................................................. 14
Electrical Characteristics ............................................................. 3 RDAC Architecture .................................................................... 14
Interface Timing Specifications .................................................. 5 Programming the Variable Resistor ......................................... 14
Timing Diagrams.......................................................................... 5 Programming the Potentiometer Divider ............................... 15
Absolute Maximum Ratings ............................................................ 6 Terminal Voltage Operating Range ......................................... 15
Thermal Resistance ...................................................................... 6 Power-Up Sequence ................................................................... 15
ESD Caution .................................................................................. 6 Layout and Power Supply Biasing ............................................ 15
Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 16
Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 16
REVISION HISTORY
11/12—Rev. A to Rev. B
Changed Low Power Consumption from 2.5 mA to 2.5 µA....... 1
Changed IDD Unit from mA to µA, Table 2 .................................... 4
4/12—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Positive Supply Current, Table 2 ................................ 4
Changes to Ordering Guide .......................................................... 16
10/11—Revision 0: Initial Version
Rev. B | Page 2 of 16
Data Sheet AD5116
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
5 kΩ, 10 kΩ, and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ 1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution N 6 Bits
Resistor Integral Nonlinearity 2 R-INL RAB = 5 kΩ, VDD = 2.3 V to 2.7 V −2.5 ±0.5 +2.5 LSB
RAB = 5 kΩ, VDD = 2.7 V to 5.5 V −1 ±0.25 +1 LSB
RAB = 10 kΩ −1 ±0.25 +1 LSB
RAB = 80 kΩ −0.25 ±0.1 +0.25 LSB
Resistor Differential Nonlinearity2 R-DNL −1 ±0.25 +1 LSB
Nominal Resistor Tolerance ΔRAB/RAB −8 +8 %
Resistance Temperature Coefficient 3 (ΔRAB/RAB)/ΔT × 106 Code = full scale 35 ppm/°C
Wiper Resistance RW Code = zero scale 70 140 Ω
RBS Code = bottom scale 45 80 Ω
RTS Code = top scale 70 140 Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Integral Nonlinearity 4 INL −0.5 ±0.15 +0.5 LSB
Differential Nonlinearity4 DNL −0.5 ±0.15 +0.5 LSB
Full-Scale Error VWFSE RAB = 5 kΩ −2.5 LSB
RAB =10 kΩ −1.5 LSB
RAB = 80 kΩ −1 LSB
Zero-Scale Error VWZSE RAB = 5 kΩ +1.5 LSB
RAB =10 kΩ +1 LSB
RAB = 80 kΩ +0.25 LSB
Voltage Divider Temperature Coefficient3 (ΔVW/VW)/ΔT × 106 Code = half scale ±10 ppm/°C
RESISTOR TERMINALS
Maximum Continuous IA, IB, and IW Current3 RAB = 5 kΩ, 10 kΩ −6 +6 mA
RAB = 80 kΩ −1.5 +1.5 mA
Terminal Voltage Range 5 GND VDD V
Capacitance A, Capacitance B3, 6 CA, CB f = 1 MHz, measured to GND, 20 pF
code = half scale, VW = VA = 2.5 V
or VW = VB = 2.5 V
Capacitance W3, 6 CW f = 1 MHz, measured to GND, 35 pF
code = half scale, VA = VB = 2.5 V
Common-Mode Leakage Current3 VA = VW = VB 50 nA
DIGITAL INPUTS (PU AND PD)
Input Logic3
High VINH 2 V
Low VINL 0.8 V
Input Current3 IN ±1 µA
Input Capacitance3 CIN 5 pF
DIGITAL OUTPUT (ASE)
Output High Voltage3 VOH ISINK = 2 mA, VDD = 5 V 4.8 V
Output Current3 IO VDD = 5 V 16 mA
Three-State Leakage Current3 IOZ ±1 µA
Input Capacitance3 CIN 5 pF
Rev. B | Page 3 of 16
AD5116 Data Sheet
Parameter Symbol Test Conditions/Comments Min Typ 1 Max Unit
POWER SUPPLIES
Single-Supply Power Range 2.3 5.5 V
Positive Supply Current IDD VDD = 5 V 0.75 3.5 µA
VDD = 2.7 V 2.5 µA
VDD = 2.3 V 2.4 µA
EEMEM Store Current3, 7 IDD_NVM_STORE 2 mA
EEMEM Read Current3, 8 IDD_NVM_READ 320 µA
Power Dissipation 9 PDISS VIH = VLOGIC or VIL = GND 5 µW
Power Supply Rejection3 PSR ∆VDD/∆VSS = 5 V ± 10%
RAB = 5 kΩ −43 dB
RAB =10 kΩ −50 dB
RAB = 80 kΩ −64 dB
DYNAMIC CHARACTERISTICS3, 10
Bandwidth BW Code = half scale − 3 dB
RAB = 5 kΩ 4 MHz
RAB = 10 kΩ 2 MHz
RAB = 80 kΩ 200 kHz
Total Harmonic Distortion THD VA = VDD/2 + 1 V rms, VB = VDD/2,
f = 1 kHz, code = half scale
RAB = 5 kΩ −75 dB
RAB = 10 kΩ −80 dB
RAB = 80 kΩ −85 dB
VW Settling Time ts VA = 5 V, VB = 0 V, ±0.5 LSB error
band
RAB = 5 kΩ 2.5 µs
RAB = 10 kΩ 3 µs
RAB = 80 kΩ 10 µs
Resistor Noise Density eN_WB Code = half scale, TA = 25°C,
f = 100 kHz
RAB = 5 kΩ 7 nV/√Hz
RAB = 10 kΩ 9 nV/√Hz
RAB = 80 kΩ 20 nV/√Hz
FLASH/EE MEMORY RELIABILITY3
Endurance 11 TA = 25°C 1 MCycles
100 kCycles
Data Retention 12 50 Years
1
Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.8 × VDD/RAB.
3
Guaranteed by design and characterization, not subject to production test.
4
INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6
CA is measured with VW = VA = 2.5 V, CB is measured with VW = VB = 2.5 V, and CW is measured with VA = VB = 2.5 V.
7
Different from operating current; supply current for NVM program lasts approximately 30 ms.
8
Different from operating current; supply current for NVM read lasts approximately 20 µs.
9
PDISS is calculated from (IDD × VDD).
10
All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V.
11
Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C.
12
Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
Rev. B | Page 4 of 16
Data Sheet AD5116
INTERFACE TIMING SPECIFICATIONS
VDD = 2.3 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit Description
t1 8 ms Debounce time
t2 1 sec Manual to auto scan time
t3 140 ms Auto scan step
t4 ASE = 0 V, PD = GND, PU = GND 1 sec Auto save execute time
t5 ASE = VDD 8 ms Low pulse time to manual storage
tEEPROM_PROGRAM 1 15 50 ms Memory program time
tPOWER_UP 2 50 µs Power-on EEPROM restore time
1
EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles.
2
Maximum time after VDD is equal to 2.3 V.
TIMING DIAGRAMS
PD/PU (LOW)
t1 tEEPROM
t5
PROGRAM
PU
ASE
PD (LOW)
09657-005
RW
Figure 2. Manual Increment Mode Timing Figure 5. Manual Save Mode Timing
t1
t1 t3
PD
PU t2
RW = 45Ω
RW
PD (LOW)
09657-006
09657-003
RW ASE
Figure 3. Auto Increment Mode Timing Figure 6. End Scale Indication Timing
t1
t4 tEEPROM
PROGRAM
PD
RW
ASE (LOW)
09657-004
Rev. B | Page 5 of 16
AD5116 Data Sheet
Rev. B | Page 6 of 16
Data Sheet AD5116
VDD 1 8 ASE
A 2 AD5116 7 PU
TOP VIEW
W 3 (Not to Scale) 6 PD
B 4 5 GND
09657-007
NOTES
1. THE EXPOSED PAD IS INTERNALLY
FLOATING.
Rev. B | Page 7 of 16
AD5116 Data Sheet
0
0.04
–0.01
R-INL (LSB)
R-DNL (LSB)
0.02
–0.02
0 –0.03
5kΩ, –40°C
5kΩ, +25°C –0.04
–0.02 5kΩ, +125°C
10kΩ, –40°C
10kΩ, +25°C –0.05
–0.04 10kΩ, +125°C
80kΩ, –40°C –0.06
80kΩ, +25°C 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C
80kΩ, +125°C 80kΩ, –40°C 80kΩ, +25°C 80kΩ, +125°C
–0.06
09657-008
–0.07
09657-011
0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
CODE (Decimal) CODE (Decimal)
Figure 8. R-INL vs. Code Figure 11. R-DNL vs. Code
0.08 0.02
5kΩ, –40°C 5kΩ, –40°C 5kΩ, +25°C 5kΩ, +125°C
5kΩ, +25°C 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C
0.06 5kΩ, +125°C 0.01
10kΩ, –40°C
10kΩ, +25°C
0.04 10kΩ, +125°C 0
80kΩ, –40°C
80kΩ, +25°C
0.02 80kΩ, +125°C –0.01
INL (LSB)
DNL (LSB)
0 –0.02
–0.02
–0.03
–0.04
–0.04
–0.06
–0.05
–0.06
09657-012
0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
CODE (Decimal)
CODE (Decimal)
Figure 9. INL vs. Code Figure 12. DNL vs. Code
800
VDD = 2.3V 1.2
VDD = 3.3V TA = 25°C VDD = 5V
700 VDD = 5V VDD = 3.3V
VDD = 2.3V
1.0
600
SUPPLY CURRENT (nA)
500
0.8
400
0.6
300
200 0.4
100
0.2
0
–100
09657-010
0
–40 –25 –10 5 20 35 50 65 80 95 110 125
09657-013
Rev. B | Page 8 of 16
Data Sheet AD5116
0 0
0x20 0x20
–10 0x10
–10 0x10
0x08
0x08 –20
–20 0x04
0x04
0x02
GAIN (dB)
GAIN (dB)
0x02 –30
0x01
–30
0x01 0x00
–40
–40
0x00
–50
–50
–60
–60 –70
09657-014
09657-017
10k 100k 1M 10M 100M 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 14. 5 kΩ Gain vs. Frequency vs. Code Figure 17. 10 kΩ Gain vs. Frequency vs. Code
0 0
0x20
–10 0x10 –10
0x08
–20 –20
0x04
PHASE (Degrees)
0x02
–30 –30
GAIN (dB)
0x01
–40 0x00
–40
–50 –50
–60 –60
RAB = 10kΩ
–70 –70 FULL SCALE
HALF SCALE
QUARTER SCALE
–80 –80
09657-015
09657-018
10k 100k 1M 10k 100k 1M 10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 15. 80 kΩ Gain vs. Frequency vs. Code Figure 18. Normalized Phase Flatness vs. Frequency
200 200
VDD = 5V VDD = 5V
POTENTIOMETER MODE TEMPCO (ppm/°C)
160
160
140
140
120 120
100 100
80 80
60 60
40 40
20 20
0 0
09657-016
09657-019
0 10 20 30 40 50 60 0 10 20 30 40 50 60
CODE (Decimal) CODE (Decimal)
Figure 16. Rheostat Mode Tempco ΔRWB/ΔT vs. Code Figure 19. Potentiometer Mode Tempco ΔRWB/ΔT vs. Code
Rev. B | Page 9 of 16
AD5116 Data Sheet
0 0
VDD = 5V 5kΩ 5kΩ VDD = 5V
VA = 2.5V + 1VRMS 10kΩ 10kΩ VA = 2.5V + VIN
–10 –10 80kΩ VB = 2.5V
VB = 2.5V 80kΩ
CODE = HALF SCALE fIN = 1kHz
–20 NOISE FILTER = 22kHz –20 CODE = HALF SCALE
NOISE FILTER = 22kHz
–30
–30
THD + N (dB)
THD + N (dB)
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–100 –90
09657-023
09657-020
20 200 2k 20k 200k 0.001 0.01 0.1 1
FREQUENCY (Hz) AMPLITUDE (V rms)
Figure 20. Total Harmonic Distortion + Noise (THD + N) vs. Frequency Figure 23. Total Harmonic Distortion + Noise (THD + N) vs. Amplitude
80 0.35
5k + 250pF 80k + 150pF VDD = 5V
10k + 75pF 80k + 250pF VA = VDD
70 10k + 150pF 5k + 0pF 0.30
VB = GND
10k + 250pF 5k + 75pF
80k + 0pF 5k + 150pF 0.25 5kΩ
60 80k + 75pF 10k + 0pF 10kΩ
0.20
50
0.15
40
0.10
30
0.05
20
0
10
–0.05
09657-024
–0.10
09657-021
0 10 20 30 40 50 60 –1 1 3 5 7 9
CODE (Decimal) TIME (µs)
Figure 21. Maximum Bandwidth vs. Code vs. Net Capacitance Figure 24. Maximum Transition Glitch
5.5V
5V
3.3V
2.7V 1.0
120 2.3V 0.0020
CUMULATIVE PROBABILITY
PROBABILITY DENSITY
0.8
90 0.0015
0.6
60 0.0010
0.4
30 0.0005
0.2
0 0 0
09657-022
09657-047
0 1 2 3 4 5 6 –600 –500 –400 –300 –200 –100 0 100 200 300 400 500 600
VDD (V) RESISTOR DRIFT (ppm)
Figure 22. Incremental Wiper on Resistance vs. VDD Figure 25. Resistor Lifetime Drift
Rev. B | Page 10 of 16
Data Sheet AD5116
0
VDD = 5V ± 10% AC 5kΩ 7
VA = 4V 10kΩ 10kΩ
VB = GND 80kΩ 80kΩ
–10 HALF SCALE 5kΩ
6
TA = 25°C
–20
–30
4
–40
3
–50
2
–60
1
–70
09657-026
10 100 1k 10k 100k 1M 0
09657-029
0 10 20 30 40 50 60
FREQUENCY (Hz)
CODE (Decimal)
Figure 26. Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 29. Theoretical Maximum Current vs. Code
0.4 20
VDD = 5V TA = 25°C
VA = VDD 18
0.3
VB = GND
16
0.2
14
0.1 CURRENT (mA)
VOLTAGE (mV)
12
0
10
–0.1
8
–0.2 6
–0.3 4
–0.4 10kΩ 2
80kΩ
5kΩ 0
09657-027
09657-044
–0.5
0 0.6 1.2 1.8 2.5 0 1 2 3 4 5
TIME (µs) VDD (V)
Figure 27. Digital Feedthrough Figure 30. Maximum ASE Output Current vs. Voltage
0 8
5kΩ VDD = 3V
10kΩ
80kΩ 7
–10
6
–20
CURRENT (mA)
5
GAIN (dB)
–30
4
–40
3
–50
2
–60 1
–70 0
09657-028
09657-045
Figure 28. Shutdown Isolation vs. Frequency Figure 31. Maximum ASE Output Current vs. Temperature
Rev. B | Page 11 of 16
AD5116 Data Sheet
TEST CIRCUITS
Figure 32 to Figure 37 define the test conditions used in the Specifications section.
NC
DUT
IW VA
A
W V+ = VDD ± 10%
ΔVMS
B VDD A PSRR (dB) = 20 log ΔV
W DD
VMS V+ ~
ΔVMS%
B PSS (%/%) =
VMS ΔVDD%
09657-033
NC = NO CONNECT 09657-030
Figure 32. Resistor Position Nonlinearity Error Figure 35. Power Supply Sensitivity (PSS, PSRR)
(Rheostat Operation: R-INL, R-DNL)
A +15V
DUT V+ = VDD W
A 1LSB = V+/2N VIN
DUT
W B OP42 VOUT
V+ OFFSET
B GND
VMS
2.5V
09657-034
09657-031
–15V
Figure 33. Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 36. Gain and Phase vs. Frequency
VDD GND
NC 0.1V
DUT RW =
IWB GND
A VDD A ICM
W DUT
+ W
B IWB 0.1V
– GND B
VDD
GND TO VDD
09657-035
09657-032
Rev. B | Page 12 of 16
Data Sheet AD5116
THEORY OF OPERATION
The AD5116 digital programmable resistor is designed to steps are not equal to 1 LSB, and are not included in the INL,
operate as a true variable resistor for analog signals within DNL, R-INL, and R-DNL specifications.
the terminal voltage range of GND < VTERM < VDD. The resistor Whenever the minimum RWB (= RBS) is reached, the resistance
wiper position is determined by the RDAC register contents. stops decrementing. Any continuous holding of the PD to logic
The RDAC register is a standard logic register; there is no high simply elevates the supply current. When RAW reaches the
restriction on the number of changes allowed. minimum resistance (= RTS), continuous holding of PU only
The RDAC register can be programmed with any position elevates the supply current.
setting using the push button interface. Once a desirable wiper
EEPROM
position is found, this value can be stored in the EEPROM
memory. Thereafter, the wiper position is always restored to The AD5116 contains an EEPROM memory that allows
that position for subsequent power-up. The storing of EEPROM wiper position storage. Once a desirable wiper position is
data takes approximately 20 ms; during this time, the device found, this value can be saved into the EEPROM. Thereafter,
is locked and does not accept any new operation, thus the wiper position will always be set at that position for any
preventing any changes from taking place. future on-off-on power supply sequence.
The AD5116 is designed to support external push buttons AUTOMATIC SAVE ENABLE
(tactile switches) directly, as shown in Figure 1. At power-up, the AD5116 checks the level in the ASE pin. If the
RDAC REGISTER pin is pulled low, as shown in Figure 38, the automatic store is
enabled. If the pin is pulled high, as shown in Figure 39,
The RDAC register directly controls the position of the digital
automatic store is disabled and the RDAC register should be
potentiometer wiper. For example, when the RDAC register
stored manually. During the storage cycle, the device is locked
is 0x20, the wiper is connected to midscale of the variable
and does not accept any new operation preventing any changes
resistor. The RDAC register is controlled using the PD and PU
from taking place.
push buttons. The step-up and step-down operations require
the activation of the PU (push-up) and PD (push-down) pins. ASE
These pins have 100 kΩ internal pull-up resistors that PU and AD5116
PD activate at logic high. The following paragraphs explain how 100kΩ GND
to increment the RDAC register, but all the descriptions are
09657-036
valid to decrement the RDAC register, swapping PU by PD.
Manual Increment Figure 38. Automatic Store Enables
The AD5116 features an adaptive debouncer that monitors the Auto Save
duration of the logic high level of PU signal between bounces. If If there is no activity on inputs during 1 second, the AD5116
the PU logic high level signal duration is shorter than 8 ms, the stores the RDAC register data into EEPROM, as shown in
debouncer ignores it as an invalid incrementing command. Figure 4.
Whenever the logic high level of PU signal lasts longer than
Manual Store
8 ms, the debouncer assumes that the last bounce is met and,
therefore, increments the RDAC register by one step. The wiper The storage is controlled by the ASE pin, which is connected to
is incremented by one tap position, as shown in Figure 2. an adaptive debouncer. If the ASE pin is pulled low longer than
Auto Scan Increment 8 ms, the AD5116 saves the RDAC register data into EEPROM,
as shown in Figure 5.
If the PU button is held for longer than 1 second, continuously VDD
holding it activates auto scan mode, and the AD5116 increments
the RDAC register by one step every 140 ms until PU is
released. Typical timing is shown in Figure 3. VDD
100kΩ
Low Wiper Resistance Feature ASE
AD5116
The AD5116 includes extra steps to achieve a minimum wiper
09657-037
09657-040
B B B
activating PU or PD.
Figure 42. Rheostat Mode Configuration
ASE
AD5116
The nominal resistance between Terminal A and Terminal B,
100kΩ GND RAB, is available in 5 kΩ, 10 kΩ, and 80 kΩ and has 64 tap points
accessed by the wiper terminal. The 6-bit data in the RDAC
09657-038
To achieve optimum performance, Analog Devices, Inc., has RWB = RBS Bottom scale (1)
patented the RDAC segmentation architecture for all the digital D
potentiometers. In particular, the AD5116 employs a two-stage RWB (D ) = × RAB + RW From 0 to 64 (2)
64
segmentation approach as shown in Figure 41. The AD5116
where:
wiper switch is designed with the transmission gate CMOS
D is the decimal equivalent of the binary code in the 6-bit
topology and with the gate voltage derived from VDD.
RDAC register.
A
TS RAB is the end-to-end resistance.
RBS is the wiper resistance at bottom scale.
RL Similar to the mechanical potentiometer, the resistance of
the RDAC between the W terminal and the A terminal also
RL
SW produces a digitally controlled complementary resistance, RWA.
RW
RWA starts at the maximum resistance value and decreases as the
data loaded into the latch increases. The general equation for
W
this operation is:
RW
6-BIT
ADDRESS
RAW = RAB + RW Bottom scale (3)
RL
DECODER
64 − D
RAW (D ) = × RAB + RW From 0 to 63 (4)
RL 64
BS
RAW = RTS Top scale (5)
B where:
D is the decimal equivalent of the binary code in the 6-bit
09657-039
RDAC register.
RAB is the end-to-end resistance.
Figure 41. Simplified RDAC Circuit RW is the wiper resistance.
Top Scale/Bottom Scale Architecture RTS is the wiper resistance at top scale.
In addition, the AD5116 includes a new feature to reduce the Regardless of which setting the part is operating in, take care
resistance between terminals. These extra steps are called to limit the current between the A terminal to B terminal, W
bottom scale and top scale. At bottom scale, the typical wiper terminal to A terminal, and W terminal to B terminal, to the
resistance decreases from 70 Ω to 45 Ω. At top scale, the maximum continuous current or pulsed current specified in
resistance between Terminal A and Terminal W is decreased Table 4. Otherwise, degradation or possible destruction of
by 1 LSB and the total resistance is reduced to 70 Ω. The extra the internal switch contact can occur.
Rev. B | Page 14 of 16
Data Sheet AD5116
PROGRAMMING THE POTENTIOMETER DIVIDER any voltage to Terminal A, Terminal B, and Terminal W.
Voltage Output Operation Otherwise, the diodes are forward-biased such that VDD is
powered on unintentionally and can affect other parts of the
The digital potentiometer easily generates a voltage divider at
circuit. Similarly, VDD should be powered down last. The ideal
wiper-to-B and wiper-to-A that is proportional to the input
power-on sequence is in the following order: GND, VDD, and
voltage at A to B, as shown in Figure 43. Unlike the polarity of
VA/VB/VW. The order of powering VA, VB, and VW is not
VDD to GND, which must be positive, voltage across A-to-B, W-
important as long as they are powered on after VDD. The
to-A, and W-to-B can be at either polarity.
states of the PU and PD pins can be logic low or floating,
VIN
A but they should not be logic high during power-on.
W VDD
VOUT
09657-041
B
A
Figure 43. Potentiometer Mode Configuration
W
If ignoring the effect of the wiper resistance for simplicity,
connecting Terminal A to 5 V and Terminal B to ground B
09657-042
output voltage at VW, with respect to ground for any valid GND
input voltage applied to Terminal A and Terminal B, is: Figure 44. Maximum Terminal Voltages Set by VDD and VSS
RWB (D ) R (D ) LAYOUT AND POWER SUPPLY BIASING
VW (D ) = × VA + AW × VB (6)
RAB RAB
It is always a good practice to use compact, minimum lead
where: length layout design. The leads to the input should be as direct
RWB(D) can be obtained from Equation 1 or Equation 2. as possible with a minimum conductor length. Ground paths
RAW(D) can be obtained from Equation 3 to Equation 5 . should have low resistance and low inductance. It is also good
practice to bypass the power supplies with quality capacitors.
Operation of the digital potentiometer in the divider mode
Low equivalent series resistance (ESR) 1 μF to 10 μF tantalum
results in a more accurate operation over temperature. Unlike
or electrolytic capacitors should be applied at the supplies to
the rheostat mode, the output voltage is dependent mainly
minimize any transient disturbance and to filter low frequency
on the ratio of the internal resistors, RWA and RWB, and not the
ripple. Figure 45 illustrates the basic supply bypassing config-
absolute values. Therefore, the temperature drift reduces to
uration for the AD5116.
5 ppm/°C.
TERMINAL VOLTAGE OPERATING RANGE AD5116
VDD VDD
The AD5116 is designed with internal ESD diodes for
C2 + C1
protection. These diodes also set the voltage boundary of 10µF 0.1µF GND
Rev. B | Page 15 of 16
AD5116 Data Sheet
OUTLINE DIMENSIONS
1.70
1.60
2.00 1.50
BSC SQ 0.50 BSC
5 8
0.175 REF
07-11-2011-B
PLANE 0.25 0.20 REF
0.20
ORDERING GUIDE
Model 1, 2 RAB (kΩ) Resolution Temperature Range Package Description Package Option Branding Code
AD5116BCPZ5-RL7 5 64 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7G
AD5116BCPZ5-500R7 5 64 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7G
AD5116BCPZ10-RL7 10 64 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7F
AD5116BCPZ10-500R7 10 64 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7F
AD5116BCPZ80-RL7 80 64 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7H
AD5116BCPZ80-500R7 80 64 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7H
EVAL-AD5116EBZ Evaluation Board
1
Z = RoHS Compliant Part.
2
The EVAL-AD5116EBZ has an RAB of 10 kΩ.
Rev. B | Page 16 of 16