Sie sind auf Seite 1von 59

Data Types

HOW MUCH DO YOU KNOW?


Topics Coverage

 Scalar data types


 Signal, variable and constant

 Enumerated, real, integer and physical

 Composite data types


 Array and record
Main VHDL
Data Types
VHDL Data Types
Diagram
Basic Data Types

 Signal
 Interconnections between components through ports of the
component instantiation
 Variable
 Local, volatile storage for temporary data inside typical
process
 Constant
 Permanent reference to a specific value that is normally used
throughout entire design
 Global value
Signal

 Typical signal declaration:


 SIGNAL signal_name : signal_type [ := initial_value ];

Keyword
Can be more
than one

 Signal can be declared in any declaration sections.


 Signal declared in package declaration is also global
signal. It can be shared among entities.
Using Global Signal

 Example:
 PACKAGE operating_platform IS
SIGNAL vcc : std_logic := ‘1’;
SIGNAL ground : std_logic := ‘0’;
END operating_platform;
 USE work.operating_platform.vcc;
 USE work.operating_platform.ground;
 USE work.operating_platform.ALL;

 Care should be taken as to whether to include the


whole package or by specific reference.
Using Global Signal

 Signal declared within an entity can be referenced by


any architectures.
 Example: Signal that is global
within entity
 ENTITY clock_switch is
SIGNAL system_clk : std_logic := ‘0’;

ARCHITECTURE mux_switch of clock_switch is


SIGNAL a, b : std_logic;
… Local signals within
a <= b WHEN system_clk = ‘1’; architecture

Variable

 Typical variable declaration:


 VARIABLE variable_name : variable_type [ := variable_value]

Keyword Can be more


than one

 Use of variable is common in process and


subprogram.
 Variable feedback_error : real := 0.67;
Variables vs. Signals

Variable Signal

 Assignment of value is  Assignment of signal is


immediate. scheduled.
 Consume less memory  Consume more
than signal. memory in terms of
scheduling and
 Less amount of code to attributes.
maintain  Require WAIT to
synchronize
assignment.
Constant

 Typical constant declaration:


 CONTANT constant_name : type_name [ := initial_value ]

 It is an object used to assign specific value of certain


type.
 It is convenient in the sense that multiple instances
utilize the same values throughout entire design.
 With constant, the model is easier to update and
maintain.
 Example:
 CONSTANT pi : REAL := 3.1414;
Main Data Types

 Typical type declaration:


 TYPE type_name IS type_mark;

 Example:
 TYPE bit_32_bus IS ARRAY ( 0 to 31 ) OF std_logic;

 Type mark ranges from enumeration of all the values


of a type to complex record structure.
Main VHDL
Data Types
VHDL Data Types
Diagram
Type Categories

 Scalar type
 Integer

 Enumerated

 Real

 Physical

 Composite type
 Array

 Record

 Access type, equivalent of pointer


 File type, can be used to declare file object
Integer Type

 Applicable to all mathematical functions


 Ranges from -2,147,483,647 to 2,147,483,647 (231)
 Strongly typed language requires matching base
types or type-casting operation for assignment to
take place.
 Example:
 VARIABLE a : INTEGER;

a := 1.0;
a := 2;  Error during
compilation…Why?
Real Type

 Used for real number, carrying decimal point.


 Ranges from -1.0E+38 to 1.0E+38.
 Example:
 SIGNAL a : REAL;


a <= 1;
a <= 5.2 ns;
a <= 1.2; 
Enumerated Type

 Values of an enumerated type is always user-defined.


 They can be identifier or single character literal.
 Identifier: vcc, ground, abc…

 Character literal: ‘x’, ‘1’, ‘0’…

 Example:
 TYPE typ_val IS ( ‘X’, ‘0’, ‘1’, ‘Z’ );

or Each identifier occupies a


position number.
TYPE typ_val IS ( X, ‘0’, ‘1’, Z );
 Can be used to represent microprocessor instructions or states
in a state machine.
Enumeration Types (example)

architecture Version1 of ALU is


type OpCode is (Add, Neg, Load, Store, Jump, Halt)
signal S: opcode;
....

begin
IC1: Reg port map (..., S, ....);
IC2: Control port map (..., S, ...);
....
end;

Instr S
Control
Reg 3
Enumeration Types

 Synthesis

 Creates a bus with sufficient number of bits to encode all


elements in enumeration type

 The first element will be coded as 0.


Multi-Valued Logic Types
(disguised enumerated type)

-- In package STD.STANDARD ....

type Boolean is (False, True);


type Bit is ('0', '1'); Enumerated type

-- In package IEEE.STD_LOGIC_1164 ...

type Std_Ulogic is
('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');

Still enumerated
type
Initial Values of Enumerated Type

 Signals and variables are initialised at the start of


simulation

 Default value is leftmost value of type

 type Boolean is (False, True);


 signal ab : boolean; -- default value is “false”.
 type Std_Ulogic is
 ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
 Signal cd : std_ulogic; -- default value is ‘U’.

 Synthesis IGNORES initial values


Initial Values of Enumerated Type

More examples:

type Opcode is (Add, Neg, Load, Store, Jump, Halt);


signal S: Opcode; -- Initial value Add

signal Clock, Reset: Std_logic; -- Initial value 'U'

variable Var1: Std_logic_vector(0 to 1); -- Initial value "UU"

variable Var2: Std_logic_vector(0 to 1) := "01";

signal N: Opcode := Halt;

constant Size: Integer := 16;

constant Zero: Std_logic_vector := "0000";


Physical Type

 Used to represent physical quantities.


 Declaration provides for a base unit and range.
 Example:
 TYPE voltage IS RANGE 0 to 10000000
UNITS uv;
mv = 1000 uv;
v = 1000 mv;
Each unit identifier
END UNITS; must be unique.

 TIME is one of the predefined physical type in


VHDL.
Main VHDL
Data Types
VHDL Data Types
Diagram
Array Type

 Grouping of elements by similar type.


 Useful for linear structures modeling, like RAM and
ROM.
 The elements can be any types in VHDL.
 Example:
 TYPE databus IS ARRAY ( 0 TO 31 ) OF BIT;
VARIABLE k : databus;
VARIABLE m : BIT;
m := k(2);
 Base type of k and m must match.
Array of Arrays

 Example:
 TYPE data_line IS ARRAY ( 0 TO 3 ) OF std_logic;
TYPE mem_array IS ARRAY ( 0 TO 7 ) OF data_line;

 Assigning values to multi-dimension array requires that the


aggregate structure matches that of data type.

 data_line := ( ‘1’, ‘0’, ‘1’, ‘0’ );


Aggregate can be used
 Single value can be retrieved as such: to initialize constant.
CONSTANT memory : mem_array;
n := memory (1) (2);
Multidimensional Array

 Example:
 TYPE mem_data IS ARRAY ( 0 TO 7, 0 TO 3 ) OF std_logic;

CONSTANT rom : mem_data;


row
column
Unconstrained Array Types

 Range or size need not be specified during


declaration.
 Enable multiple subtypes to share common base
type.
 Useful in subprograms that subprogram per size is
not necessary.
 Example:
 TYPE bit_arr IS ARRAY ( NATURAL RANGE <> ) OF BIT’;
 NATURAL in Standard package has range from 0 to
integer’high
 For 32 bit system, the range is between 0 to 232 – 1.
Unconstrained Array Type

 Example:
 TYPE bit_arr IS ARRAY ( NATURAL RANGE <> ) OF BIT’;
SUBTYPE bit_8 IS bit_arr (0 TO 7 );
SUBTYPE bit_4 IS bit_arr ( 0 TO 3 );
Record Type

 Capable of grouping objects of multiple types.


 Elements can be accessed through field name.
 It behaves similarly to hush in Perl.
 Example:
 TYPE instr IS

RECORD
opc : REAL;
src : INTEGER;
dst : BIT;
END RECORD;
Accessing Record’s Elements

 Each field in record can be accessed in the following


way:
 variable y : instr;
 X := record_name.field_name;
 y.dst := ‘1’; …
 Signal X : bit; …
 X := y.dst; …

 The base type of both sides of the assigning statement must


match.
Complex Example on Record

TYPE word IS ARRAY ( 0 TO 3 ) OF std_logic;


TYPE t_word_array IS ARRAY ( 0 TO 15 ) OF word;
TYPE addr_type IS
RECORD
source : INTEGER;
key : INTEGER;
END RECORD;
TYPE data_packet IS
RECORD
addr : addr_type;
data : t_word_array;
checksum : INTEGER;
parity : BOOLEAN;
END RECORD;
Example Continue…

PROCESS (clk)
VARIABLE packet : data_packet;
BEGIN
packet.addr.key := 5;
packet.data(0) := (‘1’, ‘0’, ‘0’, ‘1’);
packet.data(10)(2) := ‘1’;
END PROCESS;
Main VHDL
Data Types
VHDL Data Types
Diagram
Access Type

 It is an address, or a handle, to an object.


 It is used much like a pointer in Pascal or C.
 It is useful in modeling objects with dynamic nature,
like dynamic queues or fifos.
 It can only be used in sequential process.
 It uses only variable as its type.
 It is not synthesizable for now.
 It has 2 pre-defined functions: ‘new’ and ‘deallocate’.
Access Type

 ‘new’ allocates object’s size memory and returns


access value.
 Analogy to pointer in C:
 It gets an address for the memory
 ‘deallocate’ takes in access value and returns
memory to system.
Example on Access Type

PROCESS (y)
TYPE fifo IS ARRAY ( 0 TO 3 ) OF std_logic;

TYPE fifo_el_access IS ACCESS fifo;


VARIABLE fifo_ptr : fifo_el_access := NULL;
VARIABLE temp_ptr : fifo_el_access := NULL;
BEGIN
temp_ptr := new fifo;
temp_ptr.ALL := ( ‘1’, ‘0’, ‘1’, ‘0’ );
temp_ptr.ALL(0) := ‘0’;
fifo_ptr := temp_ptr; Both points to the same object.
fifo_ptr.ALL := temp_ptr.ALL; -- which can be redundant.
END PROCESS;
Both have same values in elements
File Type

 Although a file object type is considered a subset of


the variable object type, it can’t be assigned using an
assigning statement as any variable type.
 A file object can be read from, written to and checked
against the end of file.
 File objects usually content one data type.
File Type I/O

 Important:
 File input and output cannot be synthesized
 This makes the file only for analysis, not for compilation or for
synthesis.
 I/O operations do not refer to I/O pins of FPGA chips
 There will also be no routing and fitting processes
Common Use of File Objects

 Test bench
 reads test inputs from a file

 applies them to the VHDL model under test

 and records model outputs for analysis


File Object Declaration

 Declaration of a file object is accompanied by the


identifying of its type.
 The type of the file object depends on the data it
stores; integer, string, real number,
std_logic_vector.
 Example:
 Type file_class_integer is file of integer; -- type declaration
before begin of architecture (preferably).
 File integer_file : file_class_integer; -- object declaration in
process after begin of architecture.
 In the example, “integer_file” is referred as file handle. It is a
pointer to a file.
File Object Declaration

 File object declaration will be like this:


 FILE file_name : file_type_name IS IN

“/directory_path/real_file_name”;

 In case of manipulating textual file type, TextIO


package has to be included.
 Use std.textio_vhdl87.all; or
 Use std.textio_vhdl93.all;
File Open and File Close

 File_open (integer_file: file_class_integer,


“some_file.txt”, read_mode);
 procedure FILE_OPEN (file file_handle: FILE_TYPE;
File_Name: in STRING; Open_Kind: in
FILE_OPEN_KIND:=READ_MODE);
 File_close (integer_file);
 procedure FILE_CLOSE(file file_handle: FILE_TYPE);
Explicit File Opening Example

-- declare a file type in the architecture declarative region


type IntegerFileType is file of integer;
process is
file data_in: IntegerFileType; -- declare the file handle
-- other declarations
begin
file_open(data_in, “myfile.txt”, read_mode);
--
-- body of process; reading and writing files and
-- performing computations
--
end process;
-- termination implicitly causes a call to FILE_CLOSE
File Object IO Procedure

 Two common procedures and one function


applicable to file type:
 READ ( file, data1 )
 procedure READ (file file_handle: FILE_TYPE; value: out
type);
 WRITE ( file, data2 )
 procedure WRITE (file file_handle: FILE_TYPE; value: in
type);
 ENDFILE ( file ), is a function that returns a Boolean value.
 function ENDFILE (file file_handle: FILE_TYPE) return
Boolean;
Implicit File Opening

 The file type declaration takes the following typical


format.
 TYPE file_type_name IS FILE OF <data_type>;
 Type test_vector is file of std_logic; …
 File my_test_vector : test_vector is in
“../../BEEUB/ENG3051M/logic/try_try”; …
 While ( not ( endfile ( my_test_vector ) ) ) loop
write ( my_test_vector, ‘1’ );
end loop;
Implicit File Opening (Another Example)

-- declare a file type in the architecture declarative region


type IntegerFileType is file of integer;
process is
-- implicitly open a file in file declaration
file data_in: IntegerFileType open read_mode is “my_file.txt”;
-- other declarations
begin
--
-- body of process; reading and writing files and
-- performing computations
--
end process;
-- termination implicitly causes a call to FILE_CLOSE
File Type Example
Type Conversion

Example:

library IEEE;
use IEEE.Std_logic_1164.all;

library Convert_Lib;
use Convert_Lib.Conversion.all: -- proprietary package

entity Enc_Mux is
port (A: in Std_logic_vector(7 downto 0);
B: in Std_logic_vector(2 downto 0);
F: out Std_logic_vector(2 downto 0);
G: out Std_logic);
end;
Type Conversion(2)

Example (cont.):
architecture Version1 of Enc_Mux is
begin
Priority_encoder: process (A)
begin
F <= "000";
for I in 0 to 7 loop
if A(I) = '1' then
F <= To_stdlogicvector(I, 3);--converting to std_logic
exit;
end if;
end loop;
end process Priority_encoder;

Mux: G <= A(To_integer(B)); --converting to integer


end;
Numeric_Std

Example:
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Numeric.all;
---------------------------------------------------
signal A, B, C: Signed(7 downto 0);
...
C <= A + B; -- valid assignment Operators
C <= A + 1; -- valid assignment
C <= A nand B; -- valid assignment
if A = -1 then ...
---------------------------------------------------
signal U: Unsigned(7 downto 0);
signal I: Integer; Conversion functions
...
I <= To_Integer(U); -- convert to integer
U <= To_Unsigned(I, 8); -- convert to unsigned bit
Numeric_Std(2)

More example:

signal V, W: Std_logic_vector(7 downto 0);


signal S: Signed(7 downto 0);
signal I;
...
S <= Signed(V) + Signed(W);
V <= Std_logic_vector(S); Type conversions

I <= To_Integer(Unsigned(V));
W <= Std_logic_vector(To_Unsigned(I, 8));
Packages with Conversion Functions

 STD.STANDARD
 Types: Integer, Boolean, Bit, Time, String...

 IEEE.STD_LOGIC_1164.ALL
 Types: Std_logic, Std_logic_vector

 Operators: and, nand, or, xor ….

 Implicit operators: = /= > >= < <=


Other Packages Properties

 Some proprietary packages


 Operators: + - (on Std_logic_vector)

 Conversions between Std_logic_vector and Integer

 Other proprietary packages


 Types: Signed, Unsigned

 Operators: + - = /= > >= < <=

 Conversion functions
Slicing

7 6 5 4 3 2 1 0

V(2 to 5)

variable V: Std_logic_vector(0 to 7);


variable W: Std_logic_vector(3 downto 0);

W := V(2 to 5);

W: V(2) V(3) V(4) V(5)

W(1 downto 0) := "10";

W: V(2) V(3) 1 0
Concatenation

 Operator “&”
Example:

signal A: Std_logic_vector(7 downto 0);


signal B, C: Std_logic_vector(3 downto 0);
signal F: Std_logic_vector(15 downto 0);
.....
F <= A & B & C; -- F(15) = A(7)
-- F(8) = A(0)
-- F(7) = B(3)
-- F(3) = C(3)
-- F(0) = C(0)
Shift

 Logical shift left


 Example:

 signal RegisterA: Std_logic_vector(N-1 downto 0);


 RegisterA <= RegisterA (N-2 downto 0) & '0';

 Shifting function available since VHDL 93 only


 sll srl sla sra rol ror
 Only on one dimensional arrays of
 Bit
 Boolean
Operator Overloading

 Logical operators
 Defined only for types BIT and BOOLEAN
 IEEE.STD_LOGIC_1164 overloads logical operators for
types
 STD_LOGIC
 STD_LOGIC_VECTOR

 Arithmetic operators
 Defined only for type INTEGER
 Packages can overload operators to work with
STD_LOGIC_VECTORS
Operator Overloading

library IEEE;
use IEEE.Std_logic_1164.all;

library Arith_Lib;
use Arith_Lib.Arith.all: -- proprietary package

entity Adder is
port (A, B: in Std_logic_vector(7 downto 0);
Sum: out Std_logic_vector(7 downto 0));
end;

architecture Version1 of Adder is


begin
Sum <= A + B; -- '+' overload from proprietary package
end;
Reference

 “VHDL: Programming by Example” by Douglas L.


Perry, 4th ed., McGraw Hill.

Das könnte Ihnen auch gefallen