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AN805

Vishay Siliconix

PWM Optimized Power MOSFETs


for Low-Voltage DC/DC Conversion

Designers of low-voltage dc-to-dc converters have two main [ ] The value of the parameter before the parenthesis is dependent
concerns: reducing size and reducing losses. As a way of reducing on the parameter within the parenthesis.
size, designers are increasing switching frequencies. But the result
has been reduced converter efficiency. To minimize losses, Drain
MOSFET manufacturers have generally focused on lowering IRMS
on-resistance. But the results have not been optimal for dc-to-dc
conversion designs, since gate charge and switching speed issues
have been largely ignored. The dominant losses associated with Crss
MOSFETs were once conduction losses, but this is no longer the RG
case. Coss
Gate

Vishay Siliconix’s new family of PWM optimized MOSFETs has Ciss rDS(on)
been designed to give the highest efficiency available for a given
on-resistance in switching applications such as dc-to-dc
conversion. These new devices provide a very low gate charge
per unit of on-resistance, in addition to fast switching times. The Source
result is reduced gate drive and crossover losses, allowing
designers of dc-to-dc converters to simultaneously reduce the FIGURE 1. Generic MOSFET model with body diode omitted.
design footprint and increase efficiency.
MOSFET Losses where:

A simplistic model of power loss in a MOSFET used in a dc-to-dc I2RMS The RMS current in the MOSFET (A)
converter (Figure 1) can be calculated if we know the RMS, the rDS(on) On-resistance of the device for a given drive voltage
current through the MOSFET, the duty cycle, the gate voltage, and and junction temperature.
the rDS(on) of the MOSFET. This model can then be used to VGS The peak driver gate voltage for the MOSFET (V)
compare the efficiency of designs using Vishay Siliconix’s new
PWM optimized MOSFETs versus conventional and low-threshold [TJ] Junction temperature of the MOSFET
power MOSFETs. D Duty factor of the MOSFET (Ratio of on time to off
time)
The equation that defines the losses associated only with Qg Total gate charge for the MOSFET at a given gate
on-resistance and the gate drive is: voltage (C)
f Frequency of MOSFET switching (Hz)
P  I 2RMS  r DS(on)
VGS T J Using Equation 1 we can obtain a plot of power loss (gate loss +
 D  Q  VGS  f (Watts) Eq1 rDS(on) loss) as a function of gate voltage at varying switching
g V GS
 frequencies (Figure 2). [1]

Si6801 Power Loss, QG, rDS VGS Technology Comparison: 1 MHz Power Loss
40 40 0.8 50
Conduction + Gate Charge
Gate Charge (nC)

Power Loss (mW)

30 30 0.6 40
r DS(on) (  )

Loss (mW)

20 20 0.4 30

10 10 0.2 20

0 0 0 10
0 1 2 3 4 5 6 7 1 2 3 4 5 6 7
V GS V GS
FIGURE 2. Power loss for PWM optimized Si6801 p-channel FIGURE 3. Gate losses and on-resistance losses for PWM
MOSFET as a function of VGS and switching optimized power MOSFET (Si6801DQ) versus
frequency. conventional (Si6542DQ) and low-threshold
(Si6552DQ) power MOSFETs.

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Vishay Siliconix

Figure 2 shows the respective contribution of on-resistance and The PWM Optimized MOSFET in a Real Application
gate charge to overall losses for the p-channel Si6801DQ at three
different switching frequencies. At low gate-source voltages, the
rDS(on) of the MOSFET is high and therefore on-resistance losses
The PWM optimized power MOSFET is best viewed in the context
dominate. At higher gate-source voltages, on-resistance becomes
of a real application. In the example used here, the Si6801DQ is
almost a constant and the gate charge losses controlled by Qg
paired with the Si9160BQ switching regulator IC to create a
dominate. Gate losses increase with the switching frequency,
synchronous boost converter for cellular telephones with the
causing a narrowing in the optimum gate voltage. Therefore, the
following specifications:
optimum drive voltage will be at a level which is just enough to take
the rDS(on) into its constant region, but no further. Typically, this
drive voltage is between 3 and 5 V, which is what most controller
ICs provide. Input voltage: 2.7 V to 5 V (single-cell lithium ion battery is
2.7 V to 4.2 V)
Output voltage: 5V
Figure 3 compares the power losses, at a switching frequency of 1 Output current: 1 A maximum
MHz, of Vishay Siliconix’s PWM optimized Si6801DQ, a Gate drive voltage: 4.5 V
conventional power MOSFET (Si6542DQ), and a low-threshold Control scheme: Constant frequency voltage mode control
power MOSFET (Si6552DQ). Switching frequency: Varied by RC value from 300 kHz to
1.8 MHz
Power losses for the PWM optimized MOSFET at gate drives
between 2.5 and 5.5 V are significantly lower than both
conventional and low-threshold MOSFETs, making the optimized All results shown are with VIN = 3.6 V, VOUT = 5 V, IOUT = 600 mA, f
device the obvious choice for all switching applications.[7.] = 1 MHz unless otherwise stated.

ML ML
1-Cell D1 D2 C1 C2 4.7 mH
LiIon LS4148 LS4148 10 mF 10 mF
R5
100 k
1 8
D D2
SYNC 2 1 7
S S2
3 1 6
S S2
4 1 5
C10 G1 G2
C10 Si9160 0.1 mF
0.33 mF Si6801
C2 1 16
VDD VS
0.1 mF 2 15
NC DR
3 14
DMAX/SS DS
C3 R3 4 13
COMP PGND
0.1 mF 2.2 k 5 12
R4 FB UVLOSET
2.2 K 6 11
R2, 270 W NI COSC
7 10 R9 R10
VREF ROSC
8 9 100 W 3.6 k
R1 GND ENABLE C9
10 k 0.1 mF
R6 C8
C6 C4 C5 12 k C11
22 pF 0.1 mF 0.1 mF 5600 pF
36 pF
ML ML
R11 C3 C4
1.2 k 10 mF 10 mF

FIGURE 4. Si9160 Boost converter test circuit used to compare MOSFET technologies.

7. Neither Figure 2 nor Figure 3 is intended for exacting power loss calculations. These figures should only be used as a comparative measure for various MOSFET technologies.

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The following complementary n- and p-channel MOSFETs, all The switching speeds are 4 ns for the Si6801DQ PWM optimized
LITTLE FOOT TSSOP-8 devices, represent the three MOSFET and 11 ns for the conventional MOSFET. The Si6801DQ
technologies under test: provides a nearly threefold improvement and thus lower losses. In
addition to the increase in basic switching speed, notice that the
PWM optimized MOSFET Si6801DQ PWM optimized MOSFET does not exhibit a large characteristic
Conventional MOSFET . . . . . . . . . . Si6542DQ step in the voltage waveform. This step is due to the feedback
Low-threshold MOSFET . . . . . . . . . . Si6552DQ capacitance from drain to gate of the MOSFET or “Miller”
capacitance (Crss in Figure 1) being charged when the drain
voltage is lower than the gate voltage during a switching transition
Figure 4 shows test circuit used. from an OFF state to an ON state. Effectively the gate voltage is
“stalled” while the Miller capacitance is charged, and this is
reflected in the voltage waveform from drain to source. This is
obviously an unwanted characteristic and has largely been
PWM Optimized MOSFET Performance
eliminated with PWM optimized MOSFET technology.

Reducing gate charge is one way in which PWM optimized


MOSFETs cut power losses. In a real application, another
component of power loss is crossover losses. These are also A final component that affects the switching speed of a MOSFET is
minimized by the PWM optimized power MOSFET design, and the effective gate resistance (RG in Figure 1). The effective gate
are discussed in detail in Appendix A. resistance defines how fast the MOSFET capacitance can be
charged. It is therefore one of the dominant factors in determining
Figure 5 shows oscillograms of the boost converter switching how fast a MOSFET will switch. Vishay Siliconix’s PWM optimized
waveform using the three different types of power MOSFETs. MOSFETs provide a minimum effective gate resistance.

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N-Channel Turn Off 5 ns/dv N-Channel Turn On 5 ns/dv

Si6801 Si6801

High-Frequency
MOSFET
Technology
4 ns 3 ns

Si6542 Si6542

Conventional
MOSFET
11 ns Technology 11 ns

Si6552 Si6552

Low-Threshold
MOSFET
14 ns Technology 10 ns

FIGURE 5. Switching speed comparison between high-frequency, conventional, and low-threshold power MOSFETs.

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A power MOSFET is made up of many single MOSFET cells Figures 6, 7, and 8 show efficiency at switching frequencies
arranged in a parallel combination. In an ideal MOSFET all the ranging from 300 kHz to 1.8 MHz, while Figure 9 summarizes the
cells will turn on together when activated by a gate signal, and a efficiencies of the three technologies against switching frequency
minimum switching time transition will be obtained. This does not at an output current of 400 mA. For all the results shown, the input
happen in a conventional MOSFET layout because the gate signal voltage for the synchronous boost converter was 3.6 V, with an
has to propagate across the silicon in a turn-on “wave,” where the output voltage of 5 V.
cells nearest the gate bus turn on first with the outer cells following.
The PWM optimized MOSFET has symmetrical gate bussing, and The PWM optimized MOSFET surpasses all other technologies
its bonding and layout structures minimize the turn-on “wave,” thus while maintaining the highest efficiencies over the broadest load
increasing the switching speed of the device. ranges at all switching frequencies. The conventional MOSFET
technology provides the same breadth of efficiency but at a
reduced value. The low- threshold technology is clearly unsuited to
Efficiency
switching at higher switching frequencies with a gate voltage of
4.5 V.
How much extra efficiency does the PWM optimized MOSFET
provide? A comparison of the efficiency of the synchronous boost As summarized in Table 1, at all switching frequencies the PWM
converter (Figure 4) using three different MOSFET technologies optimized MOSFET technology gives superior performance, both
shows that an improvement on the order of 5% can be made if an in highest peak efficiencies and over the broadest load range,
optimized device is used. making it the ideal choice for most low-voltage dc-to-dc designs.

100.00 100.00

90.00 90.00

h% 80.00 80.00
h%

70.00 h % 6801 300 kHz 70.00 h % 6801 1 kHz


h % 6542 300 kHz h % 6542 1 kHz
h % 6552 300 kHz h % 6552 1 kHz
60.00 60.00
0.0 200.0 400.0 600.0 800.0 1000.0 0.0 200.0 400.0 600.0 800.0 1000.0
Output Current 0 to 1000 mA
Output Current 0 to 1000mA

FIGURE 6. Efficiency comparison between high-frequency, FIGURE 7. Efficiency comparison between high-frequency,
conventional, and low-threshold MOSFETs at a conventional and low-threshold MOSFETs at a
switching frequency of 300 kHz. switching frequency of 300 kHz

100
100.00
95

90.00 90

h% 85
80.00
h%
80

70.00 h % 6801 400 mA


h % 6801 1.8 MHz 75 h % 6542 400 mA
h % 6542 1.8 MHz
h % 6552 400 mA
h % 6552 1.8 MHz
60.00 70
0.0 200.0 400.0 600.0 800.0 1000.0 0 500 1000 1500 2000
Output Current 0 to 1000mA Switching Frequency (kHz)
FIGURE 8. Efficiency comparison between high-frequency, FIGURE 9. Efficiency vs. switching frequency comparing the
conventional, and low-threshold MOSFETs at a PWM optimized MOSFET technology with
switching frequency of 1.8 MHz. conventional and low-threshold technologies

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Type of Typical On-Resistance Specific Normalized Gate Charge
MOSFET at 4.5 V (m) Gate Charge per 100 m (nc)
PWM Optimized 120 1.7 1.4
Conventional 100 4.0 4.0
Low- Threshold 73 16.0 22.0

Figure of Merit for the PWM Optimized MOSFET have a lower gate charge per unit ohm, making it a lot easier and
Technology more efficient to implement a given drive scheme.

Normalized gate charge serves as a quick figure of merit for


comparing the high-frequency, conventional, and low-threshold
MOSFETs. This was calculated by normalizing the on-resistance
All N-Channel or
and gate charge of the n-channel MOSFET to 100 m: N- and P-Control IC,
eg.,
Si9140, Si9145

Similar performance advantages will be seen for the p-channel FIGURE 10. All n-channel synchronous buck converter.
process as well.

Application Areas

Ideal applications for Vishay Siliconix’s PWM optimized MOSFETs


include mobile communication equipment and other hand-held
battery-operated systems, where dc-to-dc converters are
becoming essential, and any other application where small size FIGURE 11. Implementation for synchronous rectification in a
and high efficiency are design criteria. A good example is the resonant reset forward converter.
demonstration board used as an example in this application note.
The Si9160BQ and Si6801DQ chip set is targeted for the cellular
phone market where single-cell lithium ion batteries are becoming Conclusions
more popular and high-efficiency boost converters are required. Vishay Siliconix’s PWM optimized MOSFET technology goes
The buck converter in notebook computers is another key beyond the traditional improvements in on-resistance that have
application for Vishay Siliconix’s PWM optimized MOSFETs. Most been the standard benchmark for MOSFETs. This technology
buck converter controller ICs today support synchronous addresses gate, crossover and conduction losses giving the
operation and require all n-channel MOSFETs. A typical dc-to-dc converter designer several valuable advantages,
synchronous buck converter is shown in Figure 10. including faster switching times, lower gate losses, and higher
overall converter efficiency with a minimum footprint.

References
In addition to non-isolated buck and boost topologies, Spice Analysis of low loss control/Power MOSFET Chip set for
Vishay Siliconix’s PWM optimized MOSFETs are also very useful High Frequency DC-DC Converter Design. Jeff Berwick,
in the application of synchronous rectification for isolated John Huang, Wayne Grabowski and Richard K. Williams.
converters (Figure 11). The replacement of Schottky diodes with Siliconix Inc. Charles Hymowitz and Steve Sandler. Intusoft Inc.
MOSFETs on the output of isolated topologies is becoming more HFPC Power Conversion, September 1996 Proceedings.
popular and even a necessity as output voltages drop below the
3-V level. This makes Schottky diodes impractical for efficiency Jerry Fennel, “DO Cross Talk”, Advance Power Supplies, Bishop’s
reasons. The biggest disadvantage to MOSFETs in isolated Stortford, England.
synchronous rectification is that MOSFETs have to be driven and Andrew Cowell, Si9160 Boost Converter for Mobile
Schottkies don’t. Vishay Siliconix’s PWM optimized MOSFETs Communications, May 1996.

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Power loss due to crossover or switching transition loss can be calculated from the generic expression below

ƪ ŕ ŕV ƫ
ts1 ts2
P S + f tts 1 V DS I D dt ) ts 2 DS I D dt
0 0

From this equation we can define the crossover losses generically for both resistive and clamped inductive loads.

Resistive Cross over Losses

Vdd
Vdd / RL
Vds
RL

Ids
ts1 ts2

Power
Dissipation

Vds . Ids (ts1 + ts2) f


P=
6

Clamped Inductive Cross over Losses


Vdd ts2
Id1

Vds
RL

+
Ids

ts1 ts2

Power
Dissipation

Vds (Id1 . ts1 + Id2 . ts2) f


P=
2

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