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The SP605 evaluation board



The SP605 board enables hardware and software developers to create or evaluate designs targeting the
Spartan-6 XC6SLX45T-3FGG484 FPGA.

The Spartan-6 family

The Spartan-6 family provides system integration capabilities with the lowest total cost for high-volume
applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443
logic cells, with half the power consumption of previous Spartan families, and faster, more
comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that
delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more
efficient, dual-register 6-input look-up table (LUT) logic and a rich selection of built-in system-level
blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory
controllers, enhanced mixed-mode clock management blocks, SelectIOTM technology, power-optimized
high-speed serial transceiver blocks, PCI Express compatible Endpoint blocks, advanced system-level
power management modes, auto-detect configuration options, and enhanced IP security with AES and
Device DNA protection.

Spartan-6 FPGA feature summary

Block Diagram

This figure shows a high-level block diagram of the SP605 and its peripherals.
Detailed description

This figure shows a board photo with numbered features corresponding to table here below.

Number Featue Notes

1 Spartan-6 FPGA ZC6SLX45T-3FGG484 FPGA

2 DDR3 Memory Micron MT41J64M16LA-187E

3 SPI Header Ext. x4 Winbond W25Q64VSFIG

4 Linear BPI Flash x16 Numonyx JS28F256P30T95

5 SystemACE CompactFlash Socket XCCACE-TQ144I Controller

6 USB JTAG Connector (USB Mini-B) USB JTAG Download Circuit

Number Featue Notes

7 Clock generation 200 MHz Osc

8 GTP port SMA x4 MGT RX, TX Pairs x4 SMA MGT REFCLK x2 SMA

9 PCIe 1-lane edge connector Card Edge Connector 1-lane

10 SPF Module Cage/Connector AMP 136073-1

11 Ethernet 10/100/1000 Marwell M88E1111 EPHY

12 USB UART Silicon Labs CP2103GM

13 DVI Codec and Video Connector Chrontel CH7301C-TF

14 IIC EEPROM (on backside) ST Micro M24C08-WDW6TP

15 Status LEDs

16 User LEDs, pushbuttons, DIP switches

17 Switches

18 FMC LPC Connector Samtec ASP-134603-01

19 Power Management 2 x TI UCD9240PFC

Status LEDs

The typical Xilinx FPGA power up and configuration status LEDs are present on the SP605. The red INIT
LED DS17 comes on momentarily after the FPGA powers up and during its internal power-on process.
The DONE LED DS2 comes on after the FPGA programming bitstream has been downloaded and the
FPGA successfully configured
Configuring the SP605 board

Configuring the Spartan-6 FPGA


The SP605 supports configuration in the following modes:

 JTAG (using the included USB-A to Mini-B cable)

 JTAG (using System ACE CF and CompactFlash card)

 Master SPI x4

 Master SPI x4 with off-board device

 Linear BPI Flash

USB JTAG configuration

JTAG configuration is provided through onboard USB-to-JTAG configuration logic where a computer host
accesses the SP605 JTAG chain through a Type-A (computer host side) to Type-Mini-B (SP605 side) USB
cable. The JTAG chain of the board is illustrated in figure below. JTAG configuration is allowable at any
time under any mode pin setting. JTAG initiated configuration takes priority over the mode pin settings.
The JTAG chain can be used to program the FPGA and access the FPGA for hardware and software
debug. The JTAG connector (USB Mini-B J4) allows a host computer to download bitstreams to the FPGA
using the Xilinx iMPACT software tool. In addition, the JTAG connector allows debug tools such as the
ChipScope Pro Analyzer tool or a software debugger to access the FPGA. The iMPACT software tool can
also program the BPI flash via the USB J4 connection. iMPACT can download a temporary design to the
FPGA through the JTAG. This provides a connection within the FPGA from the FPGAs JTAG port to the
FPGAs BPI interface. Through the connection made by the temporary design in the FPGA, iMPACT can
indirectly program the BPI flash from the JTAG USB J4 connector.

Configuring through External ROM

Spartan-6 FPGAs store the customized configuration data in SRAM-type internal latches. The number of
configuration bits is between 3Mb and 33Mb depending on the device size and user-design
implementation options. The configuration storage is volatile and must be reloaded whenever the FPGA
is powered up. This storage can also be reloaded at any time by pulling the PROGRAM_B pin low
(pressing the push button SW3). Several methods and data formats for loading configurations are
available. For this to work the configuration data must be stored in the on-board SPI flash. This tutorial
will show how to program the SPI flash.

Bit-serial configurations can either be master serial mode, where the FPGA generates the configuration
clock (CCLK) signal, or slave serial mode, where the external configuration data source also clocks the
FPGA. The available JTAG pins use boundary-scan protocols to load bit serial configuration data. The
bitstream configuration information (download.bit) is generated by the ISE software using a program
called IMPACT.
The Xilinx ISE IMPACT software takes an FPGA bitstream (.bit) file as input and, with the appropriate
options, generates a memory image file for the data array of an SPI serial flash. The output memory
image file format is chosen through a IMPACT software option. Typical file formats include Intel Hex
(.mcs) and Motorola Hex (.exo).

Note: Throughout this document, the word configuration applies to downloading a bitstream to the
FPGA whereas the word programming applies to downloading a flash image to the on-board serial flash.

Internal configuration process

The configuration process typically executes the following sequence:

 Detects power-up (power-on reset) or PROGRAM_B (Program Load Pin) when low.

 Clears the whole configuration memory

 Samples the mode pins (M1 M0) to determine the configuration mode, master or slave, bit-
serial or parallel.

 Loads the configuration data starting with the bus-width detection pattern followed by a
synchronization word, checks for the proper device code and ends with a cyclic redundancy
check (CRC) of the complete bitstream.

 Starts a user-defined sequence of events: realizing the internal reset of flip-flops, optionally
waiting for the DCMs and/or PLLs to lock, activating the output drivers, and transitioning the
DONE pin to high.

Internal configuration interfaces

The Master Serial Peripheral Interface (SPI) and the Master Byte-wide Peripheral Interface (BPI) are two
common methods used for configuring the FPGA. The Spartan-6 FPGA configures itself from a directly
attached industry-standard SPI serial flash PROM. The Spartan-6 can also configure itself via a BPI when
connected to an industry-standard parallel NOR flash.

Configuring the Spartan-6 upon power-up

The Spartan-6 FPGA is pre-set to Master Serial Mode, which means it initiates configuration upon
power-up and generates a configuration clock. It reads configuration data from an on-board Serial Flash
memory. This flash can be programmed through either of the two aforementioned interfaces. This
tutorial will illustrate how to use these interfaces to configure the FPGA and program the on-board serial
SPI x4 flash

The Xilinx Spartan-6 FPGA hosts a SPI interface which is visible to the Xilinx iMPACT configuration tool.
The SPI memory device operates at 3.0V. The Spartan-6 FPGA I/Os are 3.3V tolerant and provide
electrically compatible logic levels to directly access the SPI flash . The FPGA is a master device when
accessing an external SPI flash memory device. The SP605 SPI interface has two parallel connected
configuration options: an SPI X4 (Winbond W25Q64VSFIG) 8-Mb flash memory device (U32) and a flash
programming header (J17). J17 supports a user-defined SPI mezzanine board. The SPI configuration
source is selected via SPI select jumper J46.

Preparing for power-up booting

We will set the configuration mode to Master Serial/SPI: M[1:0] = 01 . Set the left switch (M0) in the
upper position and push the SW3 push button.