EVALUATION KIT AVAILABLE

MAX5051 Parallelable, Clamped Two-Switch

Power-Supply Controller IC

General Description Features

The MAX5051 is a clamped, two-switch power-supply
controller IC. This device can be used both in forward or
flyback configurations with input voltage ranges from 11V
to 76V. It provides comprehensive protection mechanisms
against possible faults, resulting in very high reliability
power supplies. When used in conjunction with secondary
side synchronous rectification, power-supply efficiencies
can easily reach 92% for a +3.3V output power supply
operated from a 48V bus. The integrated high- and low-
side gate drivers provide more than 2A of peak gate-drive
current to two external N-channel MOSFETs. Low startup
current reduces the power loss across the bootstrap
resistor. A feed-forward voltagemode topology provides
excellent line rejection while avoiding the pitfalls of tradi-
tional current-mode control.
The MAX5051 power-supply controller is primary as well
as secondary-side parallelable, allowing the design of
scaleable power systems when necessary. When paral-
leling the primary side, dedicated pins allow for simultane-
ous wakeup or shutdown of all paralleled units, thus pre-
venting current-hogging during startup or fault conditions.
The MAX5051 generates a lookahead signal for driving
secondary-side synchronous MOSFETs. Special primary-
side synchronization inputs/outputs allow two primaries to
be operated 180° out of phase for increased output power
and lower input ripple currents.
The MAX5051 is available in a 28-pin TSSOP-EP pack-
age and operates over a wide -40°C to +125°C tempera-
ture range.
Warning: The MAX5051 is designed to work with high
voltages. Exercise caution.
●● Wide Input Voltage Range, 11V to 76V
●● Voltage Mode with Input Voltage Feed-Forward
●● Ripple-Phased Parallel Topology for High Current/
Power Output
●● 2A Integrated High- and Low-Side MOSFET Drivers
●● SYNCIN And SYNCOUT Pins Enable 180° Out-Of-
Phase Operation
●● Programmable Brownout and Bootstrap UVLOs
●● High-Side Driver Bootstrap Capacitor Precharge
Driver
●● Low Current-Limit Threshold for High Efficiency
●● Programmable Switching Frequency
●● Reference Voltage Soft-Start for Startup Without
Overshoots
●● Startup Synchronization with Multiple Paralleled
Primaries
●● Programmable Integrating Current-Limit Fault
Protection
●● Look-Ahead PWM Signal for Secondary-Side
Synchronous Rectifier Drivers
●● Look-Ahead Drivers for Either A High-Speed
Optocoupler or Pulse Transformer
●● Wide -40°C to +125°C Operating Range
●● Thermally Enhanced 28-Pin TSSOP Package
Ordering Information
PART TEMP RANGE PIN-PACKAGE

Applications MAX5051AUI* -40°C to +85°C 28-TSSOP-EP**

●● High-Efficiency, Isolated Telecom/Datacom *Contact factory for availability.

Power Supplies **EP = Exposed pad.
●● 48V and 12V Server Power Supplies
Pin Configuration appears at end of data sheet.
●● 48V Power-Supply Modules
●● Industrial Power Supplies

19-2964; Rev 2; 5/14

MAX5051 Parallelable, Clamped Two-Switch
Power-Supply Controller IC

Absolute Maximum Ratings

AVIN, PVIN, XFRMRH to GND..............................-0.3V to +80V DRVL, DRVH Peak Current (<500ns)....................................±5A
BST to GND...........................................................-0.3V to +95V PVIN, REG9 Continuous Current....................................+120mA
BST, DRVH to XFRMRH........................................-0.3V to +12V REG5 Continuous Current................................................+80mA
REG9, DRVDD, DRVL to GND..............................-0.3V to +12V DRVB, RCFF, RCOSC, CSS Continuous Current............±20mA
DRVB, LXVDD, LXL, LXH to GND.........................-0.3V to +12V COMP, SYNCOUT Continuous Current............................±20mA
UVLO, STT, COMP, CON to GND.........................-0.3V to +12V REG9, REG5, and COMP Short to GND...................Continuous
FLTINT, RCFF to GND...........................................-0.3V to +12V Continuous Power Dissipation (TA = +70°C)
REG5, CS, CSS, FB to GND...................................-0.3V to +6V 28-Pin TSSOP (derate 23.8mW/°C above +70°C).....1905mW
STARTUP, SYNCIN to GND.....................................-0.3V to +6V Operating Temperature Range.......................... -40°C to +125°C
SYNCOUT, RCOSC to GND....................................-0.3V to +6V Maximum Junction Temperature (TJ)............................... +150°C
PGND to GND.......................................................-0.3V to +0.3V Storage Temperature Range............................. -65°C to +150°C
LXL, LXH Current Continuous...........................................±50mA Lead Temperature (soldering, 10s).................................. +300°C
DRVL, DRVH Current Continuous..................................±100mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Package Thermal Characteristics (Note 1)

TSSOP
Junction-to-Ambient Thermal Resistance (θJA)...........42°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Electrical Characteristics
(AVIN = 12V, PVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24kΩ, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7μF,
CREG5 = 4.7μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. All driver, voltage-regulator, and refer-
ence outputs unconnected except for bypass capacitors.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SUPPLY CURRENT (AVIN, PVIN)
VAVIN = VPVIN = 11V to 76V;
AVIN Standby Current IASTBY 300 450 µA
VSTARTUP = VCS = 0V;
VBST = VXFRMRH = VDRVDD = VREG9;
PVIN Standby Current IPSTBY 400 650 µA
RCFF floating
VAVIN = VPVIN = 11V to 76V;
AVIN Supply Current IAVIN 0.65 1 mA
VCS = 0V; VBST = VDRVDD = VREG9;
VXFRMRH = 0V; STARTUP,
PVIN Supply Current IPVIN 8 12 mA
RCFF floating
AVIN Input Voltage Range Inferred from AVIN supply current test 11 76 V
+9V LDO (REG9)
PVIN Input Voltage Range VPVIN Inferred from PVIN supply current test 11 76 V
REG9 Output-Voltage Set Point VREG9 VPVIN = 11V 8.3 9.0 V
REG9 Line Regulation VPVIN = 11V to 76V 0.1 mV/V
REG9 Load Regulation IREG9 = 0 to 80mA 250 mV

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MAX5051 Parallelable, Clamped Two-Switch
Power-Supply Controller IC

Electrical Characteristics (continued)

(AVIN = 12V, PVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24kΩ, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7μF,
CREG5 = 4.7μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. All driver, voltage-regulator, and refer-
ence outputs unconnected except for bypass capacitors.)

REG9 Dropout Voltage IREG9 = 80mA 0.5 V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REG9 Undervoltage Lockout
VREG9 falling 5.7 6.7 V
Threshold
REG9 Undervoltage Lockout
750 mV
Threshold Hysteresis
+5V LDO (REG5)
REG5 Output-Voltage Set Point VREG5 4.8 5.1 V
REG5 Load Regulation IREG5 = 0 to 40mA 50 mV
IREG5 = 40mA, measured with respect
REG5 Dropout Voltage 0.5 V
to VREG9
SOFT-START/REFERENCE (CSS)
Reference Voltage VCSS 1.125 1.235 1.255 V
Soft-Start Pullup Current ICSS 70 µA
ERROR AMPLIFIER (CSS, FB, COMP)
FB Input Range VFB Inferred from FB offset voltage test 0 3 V
FB Input Current IFB VFB = VREF ±250 nA
COMP Output Range Inferred from FB offset voltage test 2.1 6.0 V
COMP Output Sink Current VFB = 3V 20 mA
COMP Output Source Current VFB = 0V 30 mA
Open-Loop Gain GA 2.1V < VCOMP < 6V 80 dB
Unity-Gain Bandwidth BW CCOMP = 50pF, ICOMP = ±5mA 3 MHz
VFB = 0 to 3V; VCOMP = 2.1V to 6V;
FB Offset Voltage VOS -3 +3 mV
ICOMP = -5mA to +5mA
COMP Output Slew Rate SR CCOMP = 50pF 1 v/µs
PVIN UNDERVOLTAGE LOCKOUT (STT)
PVIN Undervoltage Lockout VPVIN rising 22 23.5 25 V
STT Threshold VSTT VSTT rising 1.18 1.24 1.30 V
STT Input Impedance RSTT 100 kΩ
INTEGRATING FAULT PROTECTION (FLTINT)
FLTINT Source Current IFLTINT μA
FLTINT Shutdown Threshold VFLTINTSD V
FLTINT Restart Hysteresis VFLTINTHY V

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MAX5051 Parallelable, Clamped Two-Switch
Power-Supply Controller IC

Electrical Characteristics (continued)

(AVIN = 12V, PVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24kΩ, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7μF,
CREG5 = 4.7μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. All driver, voltage-regulator, and refer-
ence outputs unconnected except for bypass capacitors.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OSCILLATOR (RCOSC, SYNCIN, SYNCOUT)
PWM Period tS RRCOSC = 24kΩ, CRCOSC = 100pF 3.9 μs
Maximum PWM Duty Cycle DMAX RRCOSC = 24kΩ, CRCOSC = 100pF 48 %
Maximum RCOSC Frequency fRCOSCMAX 1 MHz
Maximum SYNCIN Frequency fSYNCIN 50% duty cycle 500 kHz
SYNCIN High-Level Voltage VHSYNCIN Pulse rising 2.1 V
SYNCIN Low-Level Voltage VLSYNCIN Pulse falling 0.8 V
SYNCIN Pulldown Resistor 100 kΩ
SYNCIN Rising to SYNCOUT
30 ns
Falling Delay
SYNCIN Falling to SYNCOUT
70 ns
Rising Delay
SYNCOUT Voltage High Sourcing 1.2mA 4.5 5.1 V
SYNCOUT Voltage Low Sinking 2.4mA 0.3 V
RCOSC Peak Trip Level VTH 2.5 V
RCOSC Valley Trip Level 0.2 V
RCOSC Input Bias Current -0.3 μA
RCOSC Discharge MOSFET
Sinking 10mA 50 100 Ω
RDS(ON)
RCOSC Discharge Pulse Width 50 ns
UNDERVOLTAGE LOCKOUT (UVLO)
UVLO Threshold VUVLO VUVLO rising 1.18 1.24 1.30 V
UVLO Hysteresis VHYS 130 mV
UVLO Input Bias Current IBUVLO VUVLO = 2.5V -100 +100 nA
PWM COMPARATOR
RCFF Input Voltage Range 0 3 V
Feed-Forward Discharge
RDS(RCFF) Sinking 10mA 50 100 Ω
MOSFET RDS(ON)
CON Input Voltage Range 0 6 V
RCFF Level-Shift Voltage VCPWM 2.2 2.4 V

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MAX5051 Parallelable, Clamped Two-Switch
Power-Supply Controller IC

Electrical Characteristics (continued)

(AVIN = 12V, PVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24kΩ, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7μF,
CREG5 = 4.7μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. All driver, voltage-regulator, and refer-
ence outputs unconnected except for bypass capacitors.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CON Input Bias Current ICON -2 +2 μA
DRVH, DRVL = unconnected, overdrive
Propagation Delay to Output tdCPWM 90 ns
= 50mV, measured from CON to DRVL
SYNCHRONOUS RECTIFIER PULSE TRANSFORMER DRIVER (LXVDD, LXH, LXL)
High-Side MOSFET R DS(ON) RDSLXH LXH sourcing 10mA, VLXVDD = VREG5 3 6.5 12 Ω
Low-Side MOSFET RDS(ON) RDSLXL LXL sinking 10mA, VLXVDD = VREG5 2.0 5 10 Ω
LXH Rising to DRVL Rising
90 ns
Delay
CURRENT-LIMIT COMPARATOR (CS)
Current-Limit Threshold Voltage VILIM 144 154 164 mV
Current-Limit Input Bias Current IBILIM 0 < VCS < 0.3V -2 +2 μA
DRVH, DRVL = unconnected, overdrive
Propagation Delay to Output tdILIM 100 ns
= 10mV, measured from CS to DRVL
LOW-SIDE MOSFET DRIVER (DRVDD, DRVL, PGND)
VDRVL = 0V, pulse width < 100ns;
Peak Source Current 2 A
VDRVDD = VREG9
VDRVL = VREG9, pulse width < 100ns;
Peak Sink Current 3 A
VDRVDD = VREG9
DRVL Resistance Sourcing IDRVL = 50mA, VDRVDD = VREG9 1.7 3.5 Ω
DRVL Resistance Sinking IDRVL = -50mA, VDRVDD = VREG9 0.6 1.4 Ω
HIGH-SIDE MOSFET DRIVER (BST, DRVH, XFRMRH)
VDRVH = GND, pulse width < 100ns,
Peak Source Current 2 A
VBST = VREG9, VXFRMRH = 0V
VDRVH = VBST, pulse width < 100ns,
Peak Sink Current 5 A
VBST = VREG9, VXFRMRH = 0V
IDRVH = 50mA, VBST = VREG9,
DRVH Resistance Sourcing 1.7 3.5 Ω
VXFRMRH = 0V
IDRVH = -50mA, VBST = VREG9,
DRVH Resistance Sinking 0.6 1.4 Ω
VXFRMRH = 0V
Skew Between Low-Side and
0 ns
High-Side Drivers

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MAX5051 Parallelable, Clamped Two-Switch
Power-Supply Controller IC

Electrical Characteristics (continued)

(AVIN = 12V, PVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24kΩ, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7μF,
CREG5 = 4.7μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. All driver, voltage-regulator, and refer-
ence outputs unconnected except for bypass capacitors.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

BOOST CAPACITOR CHARGE MOSFET (DRVB)
DRVB Resistance Sourcing IDRVB = 50mA 8 35 Ω
DRVB Resistance Sinking IDRVB = 50mA 5 35 Ω
Delay from Clock Fall 200 ns
One-Shot Pulse Width 300 ns
STARTUP (STARTUP)
Startup Threshold VSTARTUP VSTARTUP rising 1.4 2.1 V
Startup Threshold Hysteresis 330 mV
Internal Pullup Current ISTARTUP 50 100 μA
STARTUP Pulldown MOSFET
Sinking 10mA Ω
RDS(ON)
OVERTEMPERATURE SHUTDOWN
Shutdown Junction Temperature Temperature rising 150 °C
Hysteresis 10 °C

Typical Operating Characteristics

(VAVIN = VPVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24kΩ, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7μF, CREG5 =
4.7μF, TA = +25°C, unless otherwise noted.)

AVIN STANDBY CURRENT AVIN STANDBY CURRENT PVIN STANDBY CURRENT

vs. AVIN SUPPLY VOLTAGE vs. TEMPERATURE vs. SUPPLY VOLTAGE
300 280 600
MAX5051 toc01

MAX5051 toc02

MAX5051 toc03
VUVLO = 0V VUVLO = 0V VUVLO = 0V
290 270
500
AVIN STANDBY CURRENT (µA)

PVIN STANDBY CURRENT (µA)

AVIN STANDBY CURRENT (µA)

280 260
270 250
400
260 240
250 230 300
240 220
200
230 210
220 200
100
210 190
200 180 0
10 20 30 40 50 60 70 80 -50 -25 0 25 50 75 100 125 10 20 30 40 50 60 70 80
AVIN SUPPLY VOLTAGE (V) TEMPERATURE (°C) PVIN SUPPLY VOLTAGE (V)

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MAX5051 Parallelable, Clamped Two-Switch
Power-Supply Controller IC

Typical Operating Characteristics (continued)

(VAVIN = VPVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24kΩ, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7μF, CREG5 =
4.7μF, TA = +25°C, unless otherwise noted.)

PVIN STANDBY CURRENT PVIN STARTUP VOLTAGE REG9 OUTPUT VOLTAGE

vs. TEMPERATURE vs. TEMPERATURE vs. PVIN VOLTAGE
600 MAX5051 toc04
23.6 8.805

MAX5051 toc05

MAX5051 toc06
VUVLO = 0V STT = FLOATING

500 23.5
PVIN STANDBY CURRENT (µA)

8.802
PVIN STARTUP VOLTAGE (V)

REG9 OUTPUT VOLTAGE (V)

400 23.4
8.799
300 23.3
8.796
200 23.2

8.793
100 23.1

0 23.0 8.970
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 10 20 30 40 50 60 70 80
TEMPERATURE (°C) TEMPERATURE (°C) PVIN VOLTAGE (V)

REG9 OUTPUT VOLTAGE REG9 OUTPUT VOLTAGE REG5 OUTPUT VOLTAGE

vs. TEMPERATURE vs. REG9 OUTPUT CURRENT vs. REG5 OUTPUT CURRENT
8.90 9.0 6.0
MAX5051 toc07

MAX5051 toc08

MAX5051 toc09
8.88 8.9
8.86 8.8 5.6
REG9 OUTPUT VOLTAGE (V)

REG9 OUTPUT VOLTAGE (V)

REG5 OUTPUT VOLTAGE (V)

8.84 8.7
8.82 8.6 5.2
8.80 8.5
8.78 8.4 4.8
8.76 8.3
8.74 8.2 4.4
8.72 8.1
8.70 8.0 4.0
-50 -25 0 25 50 75 100 125 0 20 40 60 80 100 120 140 160 0 10 20 30 40 50 60 70 80 90
TEMPERATURE (°C) REG9 OUTPUT CURRENT (mA) REG5 OUTPUT CURRENT (mA)

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MAX5051 Parallelable, Clamped Two-Switch
Power-Supply Controller IC

Typical Operating Characteristics (continued)

(VAVIN = VPVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24kΩ, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7μF, CREG5 =
4.7μF, TA = +25°C, unless otherwise noted.)

REG5 OUTPUT VOLTAGE AVIN SUPPLY CURRENT PVIN SUPPLY CURRENT

vs. TEMPERATURE vs. TEMPERATURE vs. TEMPERATURE
5.001 MAX5051 toc10
700 7.2

MAX5051 toc11

MAX5051 toc12
VUVLO = 0V VPVIN = 12V
5.000
600 7.1
4.999

PVIN SUPPLY CURRENT (mA)

AVIN SUPPLY CURRENT (µA)

4.998
OUTPUT VOLTAGE (V)

500
7.0
4.997
4.996 400
6.9
4.995 300
4.994
6.8
4.993 200
4.992 6.7
100
4.991
4.990 0 6.6
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)

SOFT-START/REFERENCE VOLTAGE CSS SOFT-START CURRENT

vs. TEMPERATURE vs. TEMPERATURE UVLO THRESHOLD vs. TEMPERATURE
1.245 90 1.240
MAX5051 toc13

MAX5051 toc14

MAX5051 toc15
SOFT-START/REFERENCE VOLTAGE (V)

1.240 1.235
CSS SOFT-START CURRENT (µA)

85
1.235
1.230
1.230 80
1.225
UVLO (V)

1.225
75 1.220
1.220
1.215
1.215 70
1.210 1.210
65
1.205 1.205

1.200 60 1.200
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
STT STARTUP THRESHOLD RCFF LEVEL-SHIFT VOLTAGE
vs. TEMPERATURE FLTINT CURRENT vs. TEMPERATURE vs. TEMPERATURE
1.240 95 2.30
MAX5051 toc16

MAX5051 toc17

MAX5051 toc18

1.235 94 2.29
RCFF LEVEL-SHIFT VOLTAGE (V)

93 2.28
1.230
FLTINT CURRENT (µA)

92 2.27
1.225 91 2.26
STT (V)

1.220 90 2.25
89 2.24
1.215
88 2.23
1.210
87 2.22
1.205 86 2.21
1.200 85 2.20
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)

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 MAX5051 Parallelable, Clamped Two-Switch
Power-Supply Controller IC

Typical Operating Characteristics (continued)

(VAVIN = VPVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24kΩ, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7μF, CREG5 =
4.7μF, TA = +25°C, unless otherwise noted.)

CURRENT-LIMIT THRESHOLD OPEN-LOOP GAIN/PHASE COMP OUTPUT VOLTAGE

vs. TEMPERATURE vs. FREQUENCY vs. TEMPERATURE
MAX5051 toc20
170 100 270 8
MAX5051 toc19

MAX5051 toc21
ISOURCE = 5mA
240 7
165 80
CS THRESHOLD VOLTAGE (mV)

GAIN

COMP OUTPUT VOLTAGE (V)

210
6
60 180

PHASE (DEGREES)
160
5
150
GAIN (dB)

155 40 4
120
3
150 20 90
PHASE 2 ISINK = 5mA
60
145 0
30 1

140 -20 0 0
-50 -25 0 25 50 75 100 125 0.01 0.1 1 10 100 1000 10,000 -50 -25 0 25 50 75 100 125
TEMPERATURE (°C) FREQUENCY (kHz) TEMPERATURE (°C)
DRVH AND DRVL RDSON LXL AND LXH RDSON SWITCHING PERIOD vs. RRCOSC
vs. TEMPERATURE vs. TEMPERATURE 50

MAX5051 toc24
4.0 12
45
MAX5051 toc23
MAX5051 toc22

3.5 11 SWITCHING PERIOD (µs) 40

10 35
3.0
DRVH AND DRVL SOURCING 50mA 30
2.5 9
RDSON (Ω)
RDSON (Ω)

LXH SOURCING 10mA 25

2.0 8
20
1.5 7 15

6 10
1.0
LXH SINKING 10mA 5
0.5 5
DRVH AND DRVL SINKING 50mA 0
0 4 0 40 80 120 160 200
-50 -25 0 25 50 75 100 125 -40 -15 10 35 60 85 110 RRCOSC (kΩ)
TEMPERATURE (°C) TEMPERATURE (°C)

NORMALIZED SWITCHING FREQUENCY SYNCIN TO SYNCOUT PROPAGATION DRVH MAXIMUM DUTY CYCLE
vs. TEMPERATURE DELAY vs. TEMPERATURE vs. TEMPERATURE
1.020 130 50.0
MAX5051 toc26
MAX5051 toc25

MAX5051 toc27
NORMALIZED SWITCHING FREQUENCY

120 SYNCIN FALL 49.6

1.010 TO SYNCOUT RISE
110 49.2
PROPAGATION DELAY (ns)

DRVH DUTY CYCLE (%)

1.000 100 48.8

90 48.4
0.990
80 48.0
0.980 70 47.6

0.970 60 47.2
50 SYNCIN RISE TO SYNCOUT FALL 46.8
0.960
40 46.4
SWITCHING
0.950 30 46.0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)

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MAX5051 Parallelable, Clamped Two-Switch
Power-Supply Controller IC

Typical Operating Characteristics (continued)

(VAVIN = VPVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24kΩ, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7μF, CREG5 =
4.7μF, TA = +25°C, unless otherwise noted.)

CON TO DRVL PROPAGATION DELAY CS CURRENT LIMIT TO DRVH

vs. TEMPERATURE PROPAGATION DELAY vs. TEMPERATURE
110 150

MAX5051 toc28

MAX5051 toc29
50mV OVERDRIVE 50mV OVERDRIVE
105
140
100
PROPAGATION DELAY (ns)

PROPAGATION DELAY (ns)

95 130

90
120
85
110
80
75 100
70
90
65
60 80
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Pin Description
PIN NAME
1 RCOSC
2 SYNCOUT
3 RCFF
4 CON
5 CSS
6 COMP
7 FB
8 REG5
9 REG9
10 PVIN
FUNCTION
Reset Input. Drive RESET low to clear all latches and registers (all outputs are turned off). All OUT
pulldown currents are disabled when RESET = low.
Synchronization Output. Synchronization signal to drive SYNCIN of a second MAX5051, if used.
Feed-Forward Input. Connect a resistor from RCFF to AVIN and a capacitor from RCFF to GND. This is
the PWM ramp.
PWM Comparator Noninverting Input. Connect CON to the optocoupler output for isolated applications,
or to COMP for nonisolated applications.
Soft-Start and Reference. Connect a 0.01μF or greater capacitor from CSS to GND. The 1.24V
reference voltage appears across this capacitor.
Internal Error Amplifier Output.
Feedback Input. Inverting input of the internal error amplifier. The soft-started reference is connected to
the noninverting input of this amplifier.
5V Linear Regulator Output. Bypass REG5 to GND with a 4.7μF ceramic capacitor.
9V Linear Regulator Output. Bypass REG9 to GND with a 4.7μF ceramic capacitor.
Regulator Voltage Input. Voltage input to the internal 5V and 9V linear regulators. A high-value resistor
connected from the input supply to PVIN provides the necessary current to charge up the startup
capacitor, and the 400μA standby current required by the MAX5051. After startup, the output of a tertiary
winding is used to provide continued bias to the controller.

Startup Threshold Input. Leave STT floating for a default startup voltage of 24V at PVIN. STT can be
11 STT modified by connecting external resistors. For high accuracy, choose external resistors with 50kΩ or less
impedance looking back into the divider.
Supply Input for the Secondary-Side Synchronous Pulse Transformer or Optocoupler Driver. LXVDD is
12 LXVDD
normally connected to REG5.

www.maximintegrated.com Maxim Integrated │  10

MAX5051 Parallelable, Clamped Two-Switch
Power-Supply Controller IC

Pin Description (continued)

PIN NAME FUNCTION
Synchronous-Pulse Transformer Driver, PMOS Open Drain. LXH is the high-side driver for the
13 LXH secondaryside synchronous-pulse transformer. LXH can also drive a high-speed switching optocoupler.
If not used, connect LXH to LXVDD.
Synchronous-Pulse Transformer Driver, NMOS Open Drain. LXL is the low-side driver for the
14 LXL secondaryside synchronous-pulse transformer. LXL can also drive a high-speed switching optocoupler. If
not used, connect LXL to PGND.
Current-Sense Input. The current-limit threshold is internally set to 156mV relative to PGND. The device
15 CS
has an internal noise filter. If necessary, connect an additional external RC filter.
Gate-Drive Output for Low-Side MOSFET. DRVL is capable of sourcing and sinking approximately 2A
16 DRVL
peak current.
17 PGND Power Ground.
Supply Input for Low-Side MOSFET Driver. Bypass DRVDD locally with good quality 1μF || 0.1μF
18 DRVDD
ceramic capacitors. DRVDD is normally connected to REG9.
Gate-Drive Output for Boost MOSFET. Connect the gate of a small high-voltage external FET to this pin
19 DRVB to enable charging of the high-side boost capacitor connected between pins 20 and 22. This FET may
be necessary to keep the boost capacitor charged at light loads.
20 XFRMRH Transformer Input. Transformer primary high-side connection.
21 DRVH Gate-Drive Output for High-Side MOSFET.
Boost Input. Boost supply connection point for the high-side MOSFET driver. Connect at least a 1μF
|| 0.1μF ceramic capacitor from BST to XFRMRH with short and wide PC board traces. If the voltage
22 BST
across the boost capacitor falls below the high-side undervoltage lockout threshold, the DRVH output
stops switching.
23 AVIN Supply Voltage Input. Connect AVIN directly to the input supply line.
24 GND Analog Signal Ground
Undervoltage Lockout Input. An external voltage-divider from the input supply sets the startup voltage;
25 UVLO the threshold is 1.24V with 130mV hysteresis. UVLO can also be used as a shutdown input. If unused,
connect UVLO to REG5
Startup Input. STARTUP coordinates simultaneous startup of multiple units from faults, during initial
26 STARTUP turnon, and UVLO recovery. When paralleling the secondaries of two MAX5051’s, the STARTUP inputs
of each device must be connected together.

Fault Integration Input. During persistent current-limit faults, a capacitor connected to FLTINT is charged
with an internal 90µA current source. Switching is terminated when the voltage reaches 2.9V. An
27 FLTINT
external resistor connected in parallel discharges the capacitor. Switching resumes when the voltage
drops to 2V.

Synchronization Input. SYNCIN accepts the synchronization signal from SYNCOUT of another
MAX5051 and shifts the switching of the synchronized unit by 180° allowing the reduction of input
28 SYNCIN
bypass capacitors. The MAX5051 switches at the same frequency at SYNCIN. SYNCIN must be 50%
duty cycle. Leave SYNCIN floating if unused.

www.maximintegrated.com Maxim Integrated │  11

MAX5051 Parallelable, Clamped Two-Switch
Power-Supply Controller IC

Functional Diagram

9V
PVIN REG9
LDO
5V
REG9 OK LDO REG5
18R REG5 OK
MAX5051
OVER
STT TEMP THERMAL
SHUTDOWN BST

R LEVEL
1.25V DRVH
SHIFT
1.125V 60ns
25µs XFRMRH
SHDN RISING-
RISING- EDGE
EDGE DRVDD
DELAY
DELAY
UVLO DRVL

PGND
1.25V
1.125V
LXVDD

INTERNAL
INTERNAL SUPPLY
AVIN LEVEL
REGULATOR 1.25V LXH
REFERENCE SHIFT LXL

80µA

RCOSC OSC

FLTINT
SYNCIN
SYNCOUT 2.7V/1.8V

RCFF CS

2.34V CILIM 156mV 10MHz

CPWM SHDN

1
S
D Q

CON Q
R 50µA
COMP 2.7V/1.8V
FB
STARTUP
E/A 64µA

CSS
DRVDD

200ns
300ns
RISING- LEVEL
SHDN SSA ONE DRVB
EDGE SHIFT
SHOT
GND 1.25V DELAY

www.maximintegrated.com Maxim Integrated │  12

MAX5051
Detailed Description
The MAX5051 controller IC is designed for two-switch
forward converter power-supply topologies. It incorpo-
rates an advanced set of protection features that makes
it uniquely suitable when high reliability and comprehen-
sive fault protection are required, as in power supplies
intended for telecommunication equipment. The device
operates over a wide 11V to 76V supply range. By using
the MAX5051 with a secondary-side synchronous rectifier
circuit, a very efficient low output voltage and high output-
current power supply can be designed.
In a typical application, the AVIN pin is connected directly
to the input supply. The PVIN pin is connected to the input
supply through a bleed resistor. This is used to charge up
a reservoir capacitor. When the voltage across this capac-
itor reaches approximately 24V, then primary switching
commences. If the tertiary winding is able to supply bias
to the IC, then self boot-strapping takes place and opera-
tion continues normally. If the voltage across the reser-
voir capacitor connected to PVIN falls below 6.2V, then
switching stops and the capacitor starts charging up again
until the voltage across it reaches 24V.
This device incorporates synchronization circuitry,
enabling the direct paralleling of two devices for higher
output power and lower input ripple current. Using a
single pin, the circuitry synchronizes and shifts the phase
of the second device by 180°. To enable simultaneous
wakeup and shutdown, a STARTUP pin is provided.
Connect all the STARTUP pins of all MAX5051 devices
together to facilitate parallel operation in the primary side.
When each power supply generates different output volt-
ages, connecting the STARTUP pins is not necessary.
Power Topology
The two-switch forward-converter topology offers out-
standing robustness against faults and transformer satu-
ration while allowing the use of SO-8 power MOSFETs
with a voltage rating equal to only that of the input supply
voltage.
Voltage-mode control with feed-forward compensation
allows the rejection of input supply disturbances within
a single cycle, similar to that of current-mode controlled
topologies. This control method offers some significant
benefits not possible with current-mode control. These
benefits are:
●● No minimum duty-cycle requirement because of
current-signal blanking;
www.maximintegrated.com
Parallelable, Clamped Two-Switch
Power-Supply Controller IC
●● Clean modulator ramp and higher amplitude for
increased stability;
●● Stable operating current of the optocoupler LED and
phototransistor for maximized control-loop bandwidth
(in current-mode applications, the optocoupler bias
point is output-load dependent);
●● Predictable loop dynamics simplifying the design of
the control loop.
The two-switch power topology has the added benefit of
recovering practically all magnetizing as well as the leak-
age energy stored in the parasitics of the isolation trans-
former. The lower clamped voltages on the primary power
FETs allow for the use of low RDS(ON) devices. Figure 2
shows the schematic diagram of a 48V input 3.3V/10A
output power supply built around the MAX5051.
MOSFET Drivers
The MAX5051’s integrated high- and low-side MOSFET
drivers source and sink up to 2A of peak currents, resulting
in very low losses even when switching high gate charge
MOSFETs. The high-side gate driver requires its own
bypass capacitor connected between BST and XFRMRH.
Use high-quality ceramic capacitors close to these two
pins for bypass. Under normal operating conditions, the
energy stored in the transformer parasitics swings the
XFRMRH pin to ground while the transformer is resetting.
During this time, the charge on the boost capacitor con-
nected to the BST pin is replenished. However, under cer-
tain conditions, such as when the magnetizing inductance
of the transformer is very high or when using conventional
rectification at the output, the duty cycle with light loads
may become very small. Thus, the energy stored could
be insufficient to swing XFRMRH to ground and replenish
the boost capacitor. Figure 3 shows the equivalent circuit
during the magnetizing inductance reset interval, assum-
ing synchronous rectification where the output inductor is
not allowed to run discontinuous.
If the magnetizing inductance is kept below the follow-
ing minimum, then the boost capacitor charge will not
deplete:
VIN
L M ≤ 0.294 d 2
2
f M Qg total + (0.005A) f S
where d is the duty cycle, VIN is the input voltage, fS is the
switching frequency, and Qgtotal is the total gate charge
for the high-side MOSFET. The above formula is only
an approximation; the actual value will depend on other
parasitics as well.
Maxim Integrated │  13
MAX5051 Parallelable, Clamped Two-Switch
Power-Supply Controller IC

VIN+
D4 R6
MA111CT 47Ω

R9 C8
15kΩ 4.7µF R5 D3
C11 10Ω BAT46W
0.1µF
R12
1MΩ C7 C5
4.7µF 1µF T1
C12

BST
STT

CSS

AVIN

PVIN

SYNCIN

REG9
LM: 150µH fs = 250kHz
220nF
P: 14T
FLTINT XFRMRH
N1 S: 4T
SI4486 T: 6T
GND DRVDD
D1 L1

B2100
RCOSC DRVH 2µH
N3 D5
C13 MAX5051 BSS123 T1 3.3V
STARTUP USED FOR
100pF 10A
BOOST C4
DRVB CAPACITOR 3 x 270µF
RCFF N2 RLOAD
PRECHARGE
C14 SI4486
390pF CON DRVL
CS D2
SYNCOUT

COMP PGND B2100

LXVDD

R13
UVLO

REG5

LXH

R3
LXL

100kΩ C3
FB

R4 475Ω
28mΩ 150nF
R14
24.9kΩ U2

R8
R15 2.2kΩ
1MΩ R10
10Ω R7 PS2913
C1
360Ω
47nF R1
R11 C10 C9
39.2kΩ 11.5kΩ
4.7µF 1µF C2
C6 220nF
270nF MAX8515
R2
2.55kΩ
VIN-

Figure 2. Typical Application Circuit

If the charge stored on the boost capacitor is not ade-

quately replenished then the gate-driver lockout for the
high-side MOSFET is triggered, stopping the high side IBST
BST
IBST
from switching. The low side continues switching, even-
IGD
tually recharging the capacitor, at which point the high DRVH
side starts switching again. To prevent this behavior, use
XFMRH ILM
the boost capacitor’s cycle-by-cycle charging circuit to
prevent unwanted shutdowns of the high side (Figure 2). VIN REG9 LM
Connect the gate of a small high-voltage FET (with the
same voltage rating or higher as the main FETs) to the DRVL
DRVB output of the MAX5051. Connect the drain of this
FET to XFRMRH, and connect the source to the primary
ground. DRVB will briefly (300ns) turn this FET ON every
cycle after the main PWM clock terminates. This allows
Figure 3. Boost Capacitor Charging Path During Transformer
the boost capacitor to be replenished under all conditions,
Reset
even when switching stops completely. A suitable FET for
this is BSS123 or equivalent (100V, 170mA rated). The
boost-capacitor charge diode is a high-voltage, small-sig-

www.maximintegrated.com Maxim Integrated │  14

MAX5051 Parallelable, Clamped Two-Switch
Power-Supply Controller IC

nal Schottky type. It may be helpful to connect a resistor in

series with this diode to minimize noise as well as reduce
the peak charging currents. As in any other switching
powersupply circuit, the gate-drive loops must be kept to
a minimum. Plan PC board layout with the critical current
carrying loops of the circuit as a starting point.
Secondary-Side Synchronization
The MAX5051 has additional (LXH and LXL) outputs to
make the driving of secondary-side synchronous rectifiers
possible with a signal from the primary. These signals
lead in time, the actual gate drive applied to the main
power FETs, and allow the secondary-side synchronous
FETs to be commutated in advance of the power pulse.
The synchronizing pulse is generated approximately 90ns
ahead of the main pulse that drives the two power FETs.
Synchronization is accomplished by connecting a small
pulse transformer between LXH and LXL, along with
some clamp diodes (D1 and D2 in Figure 4). This is
a small integrated two-switch driver configuration that
allows for full recovery of the stored energy in the magne-
tizing inductance of the pulse transformer, thereby signifi-
cantly reducing the running bias current of the controller. It
also allows for correct transfer of DC levels without requir-
ing series capacitors with large time constants, assuring
correct drive levels for the secondary circuit.
Select a pulse transformer, T1, so the current buildup in
its magnetizing inductance is low enough not to create a
significant voltage droop across the internal driver FETs.
Use the following formula to calculate the approximate
value of the primary magnetizing inductance of T1:
R dsLXH + R dsLXL tS
2.5 ≤ LM ≤
fS 16 C ds f S
where RdsLXH and RdsLXL are the internal high- and
lowside pulse transformer driver on-resistances, fs is the
switching frequency, LM is the pulse transformer primary
magnetizing inductance, ts is the transition time at the
drains of these FETs (typically < 40ns), and Cds is the total
drain-source capacitance (approximately 10pF).
Alternatively, a high-speed optocoupler (Figure 5) can
be used instead of the pulse transformer. The lookahead
pulse accommodates the propagation delays of the high-
speed optocoupler as well as the delays through the gate
drivers of the secondary-side FETs. Choose optocouplers
with propagation delays of less than 50ns.
Error Amplifier And Reference Soft-Start
The error amplifier in the MAX5051 has an uncommitted
inverting input (FB) and output (COMP). Use this amplifier
when secondary isolation is not required. COMP can then
be directly connected to CON (the input of the PWM com-
parator). The noninverting input of the error amplifier is
connected to the soft-start generator and is also available
externally at CSS. A capacitor connected to CSS is slewed
linearly during initial startup with the 70μA internal current
source (see Figure 2). This provides a linearly increasing
reference to the noninverting input of the error amplifier
forcing the output voltage also to slew proportionally. This
method of soft-start is superior to other methods because
the loop is always in control. Thus, the output-voltage slew

R1
MAX5051 4.7Ω MAX5051 R1
REG5 4.7Ω
REG5
LXVDD D3 5V
C1 1N4148 LXVDD
D1 R3
1µF
LXH T1 560W U2
R2 LXH
2kΩ
C1
LXL R2
LXL 1µF
2kΩ PS9715
D2 C2
HIGH-SPEED
PGND OPTO
PGND
T1: PULSE ENGINEERING, PE-68386.
D1, D2: CENTRAL SEMICONDUCTOR, CMOSH-3.

Figure 4. Secondary-Side Synchronous Rectifier Driver Using Figure 5. Secondary-Side Synchronous Rectifier Driver Using
Pulse Transformer High-Speed Optocoupler

www.maximintegrated.com Maxim Integrated │  15

MAX5051
rate is constant at light or heavy loads. Once the soft-start
ends, the voltage on CSS regulates to 1.24V. Do not load
CSS with external circuitry. A suitable range of capacitors
connected to CSS is from 10nF to 0.1μF. Calculate the
required soft-start capacitor based on the total output volt-
age startup time as follows:
CCSS = 56μF/s × tSS
where CCSS is the capacitor connected to CSS, tSS is the
soft-start time required for the output voltage to rise from
0V to the rated output voltage. This only applies when this
amplifier is used for output voltage regulation.
PWM Ramp
The PWM ramp is generated at RCFF. Connect a capaci-
tor CRCFF from RCFF to ground and a resistor RRCFF
from RCFF to AVIN. The ramp generated on RCFF is in-
ternally offset by 2.3V and applied to the noninverting in-
put of the PWM comparator. The slope of the ramp is part
of the overall loop gain. The dynamic range of RCFF is 0
to 3V, and so the ramp peak must be kept below that. As-
suming the maximum duty cycle approaches 50% at mini-
mum input voltage, use the following formula to calculate
the minimum value of either the ramp capacitor or resistor:
VINUVLO
R RCFF C RCFF ≥
2 f S VRPP
where VINUVLO is the minimum input supply voltage (typi-
cally the PWM UVLO turn-on voltage), fS is the switching
frequency, and VRPP is the peak-to-peak ramp voltage,
typically 2V.
Allow the ramp peak to be as high as possible to maximize
the signal-to-noise ratio. The low-frequency smallsignal
gain of the power stage, Gps (the gain from the inverting
input of the PWM comparator to the output) can be calcu-
lated by using the following formula:
Gps = NspRRCFFCRCFF fs
where Nsp is the secondary-to-primary power transformer
turns ratio.
Internal Regulators
The MAX5051 has two internal linear regulators that
are used to power internal and external control circuits.
The 9V regulator, REG9, is primarily used to power the
highand low-side gate drivers. Bypass REG9 with a 4.7μF
ceramic capacitor or any other high-quality capacitor; use
www.maximintegrated.com
Parallelable, Clamped Two-Switch
Power-Supply Controller IC
low-value ceramics in parallel as necessary. A 5V regu-
lator also is provided, REG5, primarily used to bias the
internal circuitry of the MAX5051. Bypass REG5 with a
4.7μF ceramic capacitor similar to the one used for REG9.
Both of these regulators are always powered. When using
bootstrapped startup through a bleed resistor, do not load
these outputs while the MAX5051 is in standby as it may
fail to start. Any external loading to this output should be
such that the sum of their load and the standby current
through PVIN of the MAX5051 is less than the current that
the bleed resistor can supply.
Startup Modes
The MAX5051 can be configured for two different startup
modes, allowing operation in either bootstrapped or direct
power mode.
Direct Power Mode
In direct power mode, AVIN and PVIN are connected
directly to the input supply. This is typical in 12V to 24V
systems. The undervoltage lockout set at STT needs to
be adjusted down with an external resistor-divider to an
appropriate level.
Bootstrapped Startup
In bootstrap mode, a resistor is connected from the in-
put supply to PVIN, where a capacitor to GND is charged
towards the input supply. When this voltage reaches the
startup threshold, the device wakes up and begins switch-
ing. A tertiary winding from the transformer is then used to
sustain operation. The MAX5051 draws little current from
PVIN before reaching the threshold, which allows a large-
value bootstrap resistor and reduces its power dissipation
after startup. A large startup hysteresis helps the design
of the bootstrap circuit by providing longer running times
during startup.
After coming out of standby and before initiating the soft-
start, the MAX5051 turns on the low-side FET to charge
up the boost capacitor. A voltage detector has been in-
corporated in the high-side driver that prevents the high-
side switch from turning on with insufficient voltage. It is
also used to indicate when the boost capacitor has been
charged. Once the capacitor is charged, soft-start com-
mences. If the duty cycle is low, the magnetizing energy in
the transformer may be insufficient to keep the bootstrap
capacitor charged. DRVB (see Figure 2 dotted lines) has
been provided to drive a small external FET connected
between XFRMRH and PGND, and is pulsed every cycle
to keep the capacitor charged.
Maxim Integrated │  16
MAX5051
Normally PVIN is derived from a tertiary winding of the
transformer. However, at startup there is no energy de-
livered through the transformer, hence, a special boot-
strap sequence is required. Figure 6 shows the voltages
on PVIN, REG9, and REG5 during startup. Initially, PVIN,
REG9, and REG5 are 0V. After the input voltage is ap-
plied, C21 (Figure 8) charges PVIN through the startup
resistor, R22, to an intermediate voltage. At this point,
the internal regulators begin charging C3 and C4. The
MAX5051 uses only 400μA (typ) of the current supplied
by R22, and the remaining current charges C21, C3, and
C4. The charging of C4 and C3 stops when their voltages
reach approximately 5V and 9V, respectively, while PVIN
continues rising until it reaches the wakeup level of 24V.
Once PVIN exceeds this wakeup level, switching of the
external MOSFETs begins and energy is transferred to
the secondary and tertiary outputs. When the voltage on
the tertiary output builds to higher than 9V, startup has
been accomplished and operation is sustained. However,
if REG9 drops below 6.2V (typ) before startup is complete,
the device goes back into standby. In this case, increase
the value of C21 to store enough energy allowing for volt-
age buildup at the tertiary winding.
Startup Time Considerations
The PVIN bypass capacitor, C21, supplies current imme-
diately after wakeup (see Figure 8). The size of C21 and
the connection of the tertiary winding determine the num-
ber of cycles available for startup. Large values of C21
increase the startup time and supply gate charge for more
cycles during initial startup. If the value of C21 is too small,
REG9 drops below 6.2V because the MOSFETs did not
PVIN
10V/div
REG9
5V/div
REG5
5V/div
40ms/div
Figure 5. Secondary-Side Synchronous Rectifier Driver Using
High-Speed Optocoupler
www.maximintegrated.com
Parallelable, Clamped Two-Switch
Power-Supply Controller IC
have enough time to switch and build up sufficient voltage
across the tertiary output to power the device. The device
goes back into standby and will not attempt to restart until
PVIN rises above 24V. Use a low-leakage capacitor for
C21, C3, and C4 (see Figure 8). Generally, power sup-
plies keep typical startup times to less than 500ms even
in low-line conditions (36VDC for telecom applications).
Size the startup resistor, R22 (Figure 8) to supply both the
maximum startup bias of the device and the charging cur-
rent for C21, C3, and C4.
Oscillator and Synchronization
The MAX5051 oscillator is externally programmable
through a resistor and capacitor connected to RCOSC.
The PWM frequency will be 1/2 the frequency at RCOSC
with a 50% duty cycle, and is available at SYNCOUT. The
maximum duty cycle is limited to < 50% by a 60ns internal
blanking circuit in the power drivers in addition to the gate
and driver delays.
Use the following formula to calculate the oscillator com-
ponents:
1
R RCOSC =
 REG5 
2 f S ( C RCOSC + C PCB ) In  
 REG5 − V TH 
where CPCB is the stray capacitance on the PC board
(about 14pF), REG5 = 5V, VTH is the RCOSC peak trip
level, and fs is the switching frequency.
The MAX5051 contains circuitry that allows it to be syn-
chronized to an external clock whose duty cycle is 50%.
For proper synchronization, the frequency of this clock
should be 15% to 20% higher than half the RCOSC fre-
quency of the MAX5051’s internal oscillator. This is be-
cause the external source SYNCIN directly drives the
power stage, whereas the internal clock is divided by two.
The synchronization feature in the MAX5051 has been
designed primarily for two devices connected to the same
power source with a short physical distance between the
two circuits. Under these circumstances, the SYNCOUT
from one of the circuits can be connected to the SYNCIN
of the other one; this forces the power cycle of the sec-
ond unit to be 180° out-of-phase. To synchronize a second
MAX5051, feed the SYNCOUT of the first device to the
SYNCIN of the second device. If necessary, many devices
can be daisy-chained in this manner. Each device will then
have 180° phase difference from the device that drives it.
Maxim Integrated │  17
MAX5051 Parallelable, Clamped Two-Switch
Power-Supply Controller IC

Integrating Fault Protection

The integrating fault protection feature allows transient #1
overcurrent conditions to be ignored for a programmable
amount of time, giving the power supply time to behave RCOSC SYNCIN
like a current source to the load. This can happen, for MAX5051
example, under load-current transients when the control SYNCOUT FLTINT

loop requests maximum current to keep the output voltage

RCFF STARTUP
from going out of regulation. The fault integration time can
be programmed externally by connecting a suitably sized CON UVLO
capacitor to the FLTINT pin. Under sustained overcurrent
faults, the voltage across this capacitor is allowed to ramp
up towards the FLTINT shutdown threshold (2.9V, typ). #2
Once the threshold is reached, the power supply shuts
down. A high-value bleed resistor connected in parallel RCOSC SYNCIN

with the FLTINT capacitor allows it to discharge towards MAX5051

SYNCOUT FLTINT
the restart threshold (1.8V, typ). Once this threshold is
reached, the supply restarts with a new soft-started cycle.
RCFF STARTUP
Note that cycle-by-cycle current limiting is provided at all
times by CS with a threshold of 154mV (typ). The fault CON UVLO

integration circuit works by forcing a 90μA current out

of FLTINT every time that the current-limit comparator
(Figure 1, CILIM) is tripped. Use the following formula
to calculate the value of the capacitor necessary for the Figure 7. Connection for Synchronized STARTUP of Two or
desired shutdown time of this circuit. More MAX5051s

IFLTINT t SH common connection of STARTUP ensures all paralleled

C FLTINT = modules wakeup and shutdown in tandem. This helps
0.9V
prevent startup conflicts when the secondaries of the
power supplies are paralleled. Connecting SYNCOUT
where IFLTINT = 90μA, tSH is the desired fault integration to SYNCIN is not necessary; however, when used, this
time after the first shutdown cycle during which current- minimizes the ripple current though the input bypass
limit events from the current-limit comparator are ignored. capacitors.
For example, a 0.1μF capacitor gives a fault integration
time of 2.25ms. Applications Information
Some testing may be required to fine-tune the actual Isolated Telecom Power Supply
value of the capacitor. To calculate the required bleed
Figure 8 shows a complete design of an isolated synchro-
resistance RFLTINT, use the following formula:
nously rectified power supply with a 36V to 72V telecom
t RT voltage range. This power supply is fully protected and
R FLTINT = can sustain a continuous short circuit at its output termi-
0.9V × C FLTINT
nals. Figures 9 though 14 show some of the performance
aspects of this power-supply design. This circuit is avail-
where tRT is the desired recovery time. able as a completely built and tested evaluation kit.
Typically choose tRT = 10 x tSH. Typical values for tSH
range from a few hundred microseconds to a few milli-
seconds.
Synchronizing Primary-Side STARTUP For
Parallel Operation
Figure 7 shows the connection diagram of two or more
MAX5051s for synchronized primary-side operation. The

www.maximintegrated.com Maxim Integrated │  18

 REG5 R21
24.9kΩ
XFRMRH
MAX5051

1% R4
1 28
RCOSC U1 SYNCIN 1MΩ
C1 +VIN
1% +VIN
100pF D2 3
MAX5051 C7 2 1 2 N1 8 7
+VIN -VIN
27 0.22µF R6 C10 C11 C12 C25

www.maximintegrated.com
+VIN FLTINT 1 6 0.47µF 0.47µF 1µF 0.07µF
R25 TP1 2 1MΩ 5
SYNCOUT R5 4 100V 100V 100V 100V
100kΩ 1% XFRMRH
3 26 38.3kΩ 3
RCFF STARTUP ON/OFF 1% C35 5V R29
C2 25 1µF
390pF UVLO N5 1Ω
24 1 8 1
GND
+VIN IN OUT DRVB
4 R7 REG9 D6 U5 C16 2
COM 23 2 1 2 7
D1 0Ω EN WDI 3.3µF
5 AVIN 2 C32
CSS
D8 C5 C8 1µF 3 GND N.C. 6
2 1 4700pF 6 22 4.7µF
COMP BST
4 5
R16 R15 RESET HOLD
21
10.5kΩ 31.6kΩ DRVH L1 VOUT
20 R13
1% 1% 7 XFRMRH XFRMRH R8 XFRMRH 2.4µH
47Ω
FB 19 8.2Ω
REG5 DRVB DRVB 2 VOUT
C4 T1 1 87
56 C13 C14 C15 C33
4.7µF 8 REG9 C34 270µF 270µF 270µF 1µF
REG5 18 D4 N4
REG9 DRVDD +VIN 330pF 8T 8 R10 2 3 4V 4V 4V 10V
C3 C9 D3 20Ω 2 1 4
4.7µF 9 1µF 5 SGND
REG9 17
PVIN PGND 1 2 65 8 1 3 4
C6 R9 7 2T C23 N_OUT GND
0.1µF 10 8.2Ω N2 1000pF U4
PVIN 16 4 5V 2 5
DRVL 2 4T P_OUT IN-
11 15 3 10 6
1 2 5
STT CS D5 6 1 6
C18 C20
1 87
V+ IN+
REG5 R14 1
100pF R17 D7 N3 C29
12 220pF 150Ω
LXVDD 0.027Ω 2 3 0.1µF
2 4
R27 C19 1% 1
R18
10Ω 1µF LXH
4.7Ω
IC_PADDLE C31 5V R26
13 C30 5V 5V 0.1µF
LXH LXH PVIN R22 +VIN 560Ω
VOUT 0.1µF 5 1
14 15kΩ 6 VCC AN
TP3 LXL 1
V+ IN+
R20 C27 U6
REG5 C21 U7
0Ω 0.15µF 2 4 R28
4.7µF P_OUT IN- 5 OUT
2kΩ
80V 3 4
R3 R19 M_OUT GND 3 2
475Ω GND CA
2.2kΩ 4 1
U2
R12
100kΩ
C24 1%
R11 3 2 VOUT
1000pF C22 REG9 U1: MAX5051
360Ω
4 2200pF U2: PS2913-1-M
3 U3 IN U3: MAX8515

Figure 8. Schematic of a 48V Input 3.3V at 15A Output Synchronously Rectified, Isolated Power Supply
OUT 1 2kV
C17 PGND C26 U4, U7: MAX5048A
0.33µF TRIM
5 2 0.1µF U5: MAX5023M
FB GND
U6: PS9715
C36 C28 R1 R2 N1, N2: SI4486
0.22µF 0.047µF 11.5kΩ 2.55kΩ N3, N4: SI4864
VOUT 1% 1% R24
N5: BSS123
10Ω

R23
10Ω
SENSE (+) SENSE (-)
Power-Supply Controller IC

Maxim Integrated │  19
Parallelable, Clamped Two-Switch
MAX5051 Parallelable, Clamped Two-Switch
Power-Supply Controller IC

95 8

90 7

POWER DISSIPATION (W)

6
85
EFFICIENCY (%)

5
80
4
75
3
70
2

65 1

60 0
0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14
LOAD CURRENT (A) LOAD CURRENT (A)

Figure 9. Efficiency at Nominal Output Voltage vs. Load Current Figure 10. Power Dissipation at Nominal Output Voltage vs.
48V Nominal Input Voltage Load Current for 48V Input Voltage.

RL = 0.22Ω

VOUT
VOUT
100mV/div
1V/div

IOUT
5A/div
IOUT
5A/div

4ms/div 1ms/div
50% > 75% > 50% OF IOUT(MAX), dl/dt = 5A/µs

Figure 11. Turn-On Transient at Full Load (Resistive Load) Figure 12. Output Voltage Response to Step-Change in Load
Current

www.maximintegrated.com Maxim Integrated │  20

MAX5051 Parallelable, Clamped Two-Switch
Power-Supply Controller IC

IOUT
A
10A/div
VOUT
50mV/div

IOUT
B
10A/div

2s/div A: 1ms/div
B: 20ms/div

Figure 13. Output Voltage Ripple At Nominal Input Voltage and Figure 14. Load Current (10A/div) as a Function of Time When
Full Load Current (Scope Bandwidth = 20MHz) the Converter Attempts to Turn On into a 50mΩ Short Circuit

Pin Configuration Chip Information

TRANSISTOR COUNT: 2049
TOP VIEW PROCESS: BiCMOS/DMOS
RCOSC 1 28 SYNCIN
Exposed Paddle Connected to GND
SYNCOUT 2 27 FLTINT

RCFF 3 26 STARTUP

CON 4 25 UVLO Package Information

CSS 5 24 GND
For the latest package outline information and land patterns
MAX5051 (footprints), go to www.maximintegrated.com/packages. Note
COMP 6 23 AVIN that a “+”, “#”, or “-” in the package code indicates RoHS status
FB 7 22 BST only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
REG5 8 21 DRVH

REG9 9 20 XFRMRH PACKAGE PACKAGE OUTLINE LAND

PVIN 10 19 DRVB TYPE CODE NO. PATTERN NO.
STT 11 18 DRVDD 28 TSSOP U28E-4 21-0108 90-0146
LXVDD 12 17 PGND

LXH 13 16 DRVL

LXL 14 15 CS

TSSOP
EXPOSED PADDLE IS INTERNALLY CONNECTED TO GND.

www.maximintegrated.com Maxim Integrated │  21

MAX5051 Parallelable, Clamped Two-Switch
Power-Supply Controller IC

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
2 5/14 No /V OPNs; removed automotive reference from Applications section 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2014 Maxim Integrated Products, Inc. │  22